International Journal of Latest Research in Science and Technology

Vol.1,Issue 2 :Page No.179-182 ,July-August (2012)

http://www.mnkjournals.com/ijlrst.htm

ISSN (Online):2278-5299

ANALYSIS OF ADIABATIC LOGIC NOR GATE FOR

POWER REDUCTION
Ritu Sharma1, Pooja Nagpal2, Nidhi Sharma3
Department of Electronics and Communication
* JCVD College, Sirsa-125055, India
1
ritusharmagemini@yahoo.co.in
#JCVD College, Sirsa-125055, India
2
poojamehra80@rediffmail.com
^YMCA University of Science and Technology, Faridabad-121006, India
3
nidhi1318@gmail.com
1,2,3

Abstract- This paper presents a new adiabatic logic family for NOR gate. The Paper discussed design of NOR gate
using adiabatic technology namely 2pascl,2padcl,Adcl,Quassi and QSERL technology The proposed two phase clocked
adiabatic static CMOS logic (2PASCL) circuit utilizes the principle of adiabatic switching and energy recovery. We
design and simulate NOR logic gates based on 2PASCL, 2PADCL, ADCL ,QUASI and QSERL with Tanner tool
version 13 implemented using 0.18m CMOS technology. From the simulation results and compared with all
technologies ,it is shown that 2PASCL NOR logic gives lowest power dissipiation at transition frequencies of 10 to 100
MHz. The transient analysis of the circuits is performed on tanners tool at a supply voltage ranging 1.8V using TSMC
0.18m CMOS process. A constant output load capacitance of 1pF is used for power and delay measurements.
Keywords - CMOS, 2PASCL, adiabatic, QUASI and TSMC

I.

INTRODUCTION

As demand for Portable products is increasing the need for

low-power design is becoming a major issue in highperformance digital systems, such as microprocessors, digital
signal processors (DSPs) and other applications. Increasing
chip density and higher operating speed lead to the design of
very complex chips with high clock frequencies. Low power
design of VLSI circuits has been identified as a critical
technological need in recent years due to the high demand for
portable consumer electronics products..In this paper NOR
gate is designed by using adiabatic technology namely
2pascl,2padcl,adcl,quasi and qserl.Paper discussed the design
of nor gates by all these technologies and compared the
power dissipiation in all the technologies
I.

DESIGN OF CIRCUITS

The Operation of the 2PASCL NOR illustrated by circuit

diagram and waveform shown in Figure. Two diodes
differentiate between 2PASCL [5] and static CMOS logic
gate. One diode from the output node to the power clock
supply and another one is placed next to the nMOS logic to
another power clock. . Both MOSFET-diodes are used to recycle the charges from the output node, to improve
discharging speed of internal signal nodes. Signal nodes got
the advantage due to the long chain of switches before them.
The other
difference is that split-level sinusoidal power clock supplies,
and are used to replace the Vdd and the Vss. Substrate of
nMOS, it is connected to clk(bar) whereas for pMOS is
connected to clk. Figure 1 illustrate the ciruit diagram and
figure 2 output waveform. In output waveform sinusoidal
clock used as power supplies as clk and clk(bar) and output
of nor is shown in second row.

A. TWO PHASE CLOCKED ADIABATIC STATIC

CMOS LOGIC (2PASCL)

Fig.1 Schematic of 2pascl nor gate

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Fig. 2 Output waveform of nor 2pascl

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B. TWO PHASE ADIABATIC DYNAMIC CMOS

LOGIC (2PADCL)

Fig 3 Schematic of 2padcl nor gate

Fig 3,4 illustrate proposed 2PADCL NOR. In 2PADCL NOR
operated with complementary phases of power supply signals.
Supply waveform having two modes in. evaluation. and .hold,
assumption made for adiabatic mode in which clk and
clk(bar) are in evaluation mode, then there is conducting
path(s) in either PMOS devices or NMOS devices.
Evaluation of output node made from low to high or from
high to low or remain unchanged, which resembles to the
CMOS circuit. Thus, there is no need to restore the node
voltage to 0 (or Vdd) every cycle. On the other side When clk
and clk(bar) are in hold mode, Output node holds its value in
spite of the fact that clk and clk(bar) are changing their values.
By observing the function of diodes and the fact that the
inputs of a gate have a different phase with the output we can
find the above mentioned facts. Reduction of node switching
activity subsequently takes place due to not necessarily
charging and discharging of circuit nodes with every clock
cycle. Therefore, the speed of 2PADCL [6] circuits is faster
than that of ADCL circuits. Other feature of the 2PADCL is
that the logical .1. State does not reach the peak value of the
power supply but is lower by the amount of drain-source
voltage VDS of the MOS-switch and the diode voltage Vd,
i.e. V (1) = Vclk - VDS- Vd. In a similar manner, the
logical .0. State is not equal to the ground potential but
remains above that, i.e. V (0) = VDS +Vd. The circuit
diagram of 2padcl and its output waveform is shown in figure
below:

Fig.5 Schematic of adcl nor gate

Takahashi and Mizunuma [2] has provided ADCL logic
which was later modified by, Kaishita et al [2]. Placement of
rectifying diode was the main difference between the two
logic circuits. The number of diodes get reduced in the
modified ADCL logic circuit and that modified ADCL design
we have used. A low energy system is achieved by using one
sinusoidal and triangular clock supply. Two rectifying diodes
are used each in charging path and discharging path to
control the charge flow. By using MOSFET as diode, gate
and drain are shorted of mosfet together. Threshold voltage
of Mosfet or potential drop between drain and source in
conducting mosfet may cause energy dissipiation in this logic
circuit because diode in this logic circuit cut in potential and
thus energy is dissipiated in resistance of MOS devices.And
further use of slowly varying power clock provides small
energy dissipiation in the ON resistance of MOS devices. The
output waveform of ADCL logic circuit is shown in fig 5 in
first row, input given to the inverter is shown in row second
and waveform in third row shows the power clock.

D.

Fig. 6 Output waveform of adcl nor gate

QUASI ADIABATIC NOR

Fig. 4 Output waveform of nor gate

C.

ADIABATIC DYNAMIC CMOS LOGIC NOR

(ADCL)

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Fig. 7 Schematic of adcl nor gate

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Ritu Sharma et.al, International Journal of Latest Research in Science and Technology

In fully adiabatic circuits no loss occurs neither adiabatic-loss

and nor non-adiabatic loss where as in Quasi-adiabatic
circuits the non adiabatic losses are present. In quasi
adiabatic circuits [4] range of frequency is divided in three
regions namely high frequency ,low frequency and mid
frequency range.In low frequency range adiabatic losses are
minimum, leakage losses are minimum in high frequency
range and in mid frequency range overall energy dissipiation
is low.Due to different numbers of transistors, power-clock
schemes these ranges of frequency are different for different
quasi adiabatic circuits .Quasi adiabatic circuits [3] is better
as it consumes less silicon area because circuits do not
requires isolation switches. The timing of input signal and
power clock supply is not critical

varies from 0 to 1.8V and first two row shows the sinusoidal
clock clk and clk(bar) in complementary phase is shown.

Fig. 10 Output Waveform Of Qserl

III SIMULATION RESULTS
Two-Input2PASCL,2PADCL,ADCL,QUASI,QSERL NOR
Gate structure is designed in Tanners Tool (TSPICE) and
simulated with capacitance of 1pf. The transient simulated
results are shown in table .
Table 1.

Fig. 8 Output waveform of quasi

E. QUASI-STATIC ENERGY RECOVERY LOGIC NOR
GATE (QSERL)

In
pu
tA
0

Inp
utB

2pascl

2padcl

Adcl

Quasi

Qserl

Weak0

Weak1

Strong0

Strong
0
Strong
0
Strong
0

Strong
1
Strong
0
Strong
0
Strong
0

Strong
1
Strong
0
Strong
0
Strong
0

Strong
1
Strong
0
Strong
0
Strong
0

Strong0
Strong0

Fig. 9 Schematic of qserl nor gate

Fig. 11 Power dissipation graph for nor gate at 500Hz
QSERL resembles the static CMOS logic. Diodes present at
top of p-mos tree helps in control of charging path while
discharging path is controlled by diode at bottom of n-mos
tree. Cascaded gates are in alternate phases are used.The
sinusoidal clock clk and clk(bar) in complementary phases
are used.The first gate is in evaluation mode where as first
gate is in hold phase. QSERL is static in contrast to dynamic
adiabatic logic . In QSERL [5] diodes are used to control for
charging and discharging paths which later replaced by low
threshold voltage mosfet.The output of QSERL waveform is
shown in fig in which input in form of pulse form and its
corresponding output is shown in second row whose voltage

ISSN 2278-5299

From the results, 2PASCL based inverter gives the lowest

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Ritu Sharma et.al, International Journal of Latest Research in Science and Technology

Fig. 12 Power dissipation at different freq.

IV. CONCLUSIONS AND FUTURE WORK
This paper has described a simulation of NOR logic gate
based on adiabatic technology using five technologies
namely 2pascl,2padcl,adcl,quasi and qserl.By implementing
the adiabatic charging and energy recovery theory, 2PASCL
NOR gives the lowest result in power dissipation of all the
simulated adiabatic NOR . It has been seen that at different
frequencies power disipiation for nor gate using 2pascl
technology has the lowest power reduction . In future these
logics can be designed at other technologies to further reduce
the power consumption and voltage swing can be improved
and future work on minimization of chip area can also be
done on various technologies.
ACKNOWLEDGMENT
I would like to express my appreciation to all those whom
have made this paper a reality. My greatest appreciation and
thanks goes out to Asst. Prof. Pooja Nagpal for the support
and advice given throughout. Also I would like to thank Asst
Prof. Prashant Kumar for his expert advice throughout the
paper.
References
[1] Sung Mo kang Yusuf Leblebici CMOS digital Integrated circuits,
3rd edition, Tata McGraw-Hill,2003.
[2] Nazrul Anuar, Yasuhiro Takahashi Toshikazu Sekine Faculty of
Engineering Gifu University, Adiabatic Logic versus CMOS for Low Power
Applications.
[3] J. M. RABAEY, AND M. PEDRAM, Low Power Design
Methodologies, Kluwer Academic Publishers, 2002
[4]T. INDERMAUER AND M. HOROWITZ, Evaluation of Charge
Recovery Circuits and Adiabatic Switching for Low Power Design,
Technical Digest IEEE Symposium Low Power Electronics, San Diego, pp.
102-103, October 2002.
[5] Y. Ye and K. Roy, QSERL: Quasi-static energy recovery logic, IEEE J.
Solid-States Circuits, vol.36, no.2, pp.239248, Feb. 2001.
[6] N. Anuar, Y. Takahashi and T. Sekine, Two phase clocked adiabatic
static logic circuit: a proposal for digital low power applications, Proc.
IEICE Gen. Conf., p.102, Mar. 2009.

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