IS61LV25616AL

256K x 16 HIGH SPEED ASYNCHRONOUS

CMOS STATIC RAM WITH 3.3V SUPPLY

DECEMBER 2011

DESCRIPTION
The ISSI IS61LV25616AL is a high-speed, 4,194,304-bit

FEATURES
High-speed access time:
10, 12 ns
CMOS low power operation
Low stand-by power:
Less than 5 mA (typ.) CMOS stand-by
TTL compatible interface levels
Single 3.3V power supply
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
Lead-free available

static RAM organized as 262,144 words by 16 bits. It is

fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative
circuit design techniques, yields high-performance and low
power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61LV25616AL is packaged in the JEDEC standard
44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP
and 48-pin Mini BGA (8mm x 10mm).

FUNCTIONAL BLOCK DIAGRAM

A0-A17

DECODER

256K x 16
MEMORY ARRAY

I/O
DATA
CIRCUIT

COLUMN I/O

VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte

CE
OE
WE
UB
LB

CONTROL
CIRCUIT

Copyright 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774

Rev. F
12/15/2011

IS61LV25616AL

TRUTH TABLE

Mode
Not Selected
Output Disabled

Read


Write

WE
X
H
X
H
H
H
L
L
L

CE
H
L
L
L
L
L
L
L
L

OE
X
H
X
L
L
L
X
X
X

LB
X
X
H
L
H
L
L
H
L

PIN CONFIGURATIONS
44-Pin TSOP (Type II) and SOJ

A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

UB
X
X
H
H
L
L
H
L
L

I/O PIN
I/O0-I/O7
I/O8-I/O15
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
High-Z
High-Z
Dout
Dout
Dout
Din
High-Z
High-Z
Din
Din
Din

Vdd Current
Isb1, Isb2
Icc
Icc

Icc

PIN DESCRIPTIONS

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A17
A16
A15
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10

A0-A17
I/O0-I/O15
CE
OE
WE
LB
UB
NC
Vdd
GND

Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
Power
Ground

Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774

Rev. F
12/15/2011

IS61LV25616AL

PIN CONFIGURATIONS
44-Pin LQFP

48-Pin mini BGA

2

LB

OE

A0

A1

A2

N/C

I/O8

UB

A3

A4

CE

I/O0

I/O9

I/O10

A5

A6

I/O1

I/O2

GND

I/O11

A17

A7

I/O3

VDD

VDD

I/O12

NC

A16

I/O4

GND

I/O14

I/O13

A14

A15

I/O5

I/O6

I/O15

NC

A12

A13

WE

I/O7

NC

A8

A9

A10

A11

NC

A17
A16
A15
A14
A13
A12
A11
A10
OE
UB
LB

44 43 42 41 40 39 38 37 36 35 34
33
1
32
2
31
3
30
4
29
5
TOP VIEW
28
6
27
7
26
8
25
9
24
10
23
11
12 13 14 15 16 17 18 19 20 21 22

I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC

WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7

PIN DESCRIPTIONS
A0-A17
I/O0-I/O15
CE
OE
WE
LB
UB
NC
Vdd
GND

Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
Power
Ground

Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774

Rev. F
12/15/2011

IS61LV25616AL

ABSOLUTE MAXIMUM RATINGS(1)

Symbol
Vterm
Tstg
Pt

Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation

Value
0.5 to Vdd+0.5
65 to +150
1.0

Unit
V
C
W

Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

OPERATING RANGE

Range
Commercial
Industrial

Ambient Temperature
0C to +70C
40C to +85C

Vdd
10ns
3.3V +10%, -5%
3.3V +10%, -5%

12ns
3.3V + 10%
3.3V + 10%

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol
Voh
Vol
Vih
Vil
Ili

Ilo

Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage

Output Leakage

Test Conditions
Vdd = Min., Ioh = 4.0 mA
Vdd = Min., Iol = 8.0 mA


GND Vin Vdd

GND Vout Vdd
Outputs Disabled

Com.
Ind.
Com.
Ind.

Min.
2.4

2.0
0.3
2
5
2
5

Max.

0.4
Vdd + 0.3
0.8
2
5
2
5

Unit
V
V
V
V
A
A

Notes:
1. Vil (min.) = 2.0V for pulse width less than 10 ns.

Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774

Rev. F
12/15/2011

IS61LV25616AL

POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)

Symbol Parameter
Test Conditions
Icc
Vdd Dynamic Operating Vdd = Max.,
Com.



Supply Current
Iout = 0 mA, f = fmax Ind.


Isb
TTL Standby Current
Vdd = Max.,
Com.

(TTL Inputs)
Vin = Vih or Vil
Ind.



CE Vih, f = fmax.
Isb1
TTL Standby Current
Vdd = Max.,
Com.

(TTL Inputs)
Vin = Vih or Vil
Ind.



CE Vih, f = 0
Isb2
CMOS Standby
Vdd = Max.,
Com.

Current (CMOS Inputs) CE Vdd 0.2V,
Ind.

Vin Vdd 0.2V, or


Vin 0.2V, f = 0

-10
Min. Max.
100
110
50
55

-12
Min. Max.
90
100
45
50

Unit
mA
mA

20
25

20
25

mA

15
20

15
20

mA

Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Shaded area product in development

CAPACITANCE(1)
Symbol
Cin
Cout

Parameter
Input Capacitance
Input/Output Capacitance

Conditions
Vin = 0V
Vout = 0V

Max.
6
8

Unit
pF
pF

Note:
1. Tested initially and after any design or process changes that may affect these parameters.

Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774

Rev. F
12/15/2011

IS61LV25616AL

READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)

Symbol
Parameter
trc
Read Cycle Time


taa
Address Access Time


toha
Output Hold Time


tace
CE Access Time


tdoe
OE Access Time


thzoe(2)
OE to High-Z Output


tlzoe(2)
OE to Low-Z Output


thzce(2
CE to High-Z Output


tlzce(2)
CE to Low-Z Output


tba
LB, UB Access Time


thzb(2)
LB, UB to High-Z Output


tlzb(2)
LB, UB to Low-Z Output


tpu
Power Up Time


tpd
Power Down Time

-10
Min. Max.
10
10
2

10

4

4
0

0
4
3


4
0
3
0

0

10

-12
Min. Max.
12

12

2


12


5


5

0


0
6

3



5

0
4

0


0


12

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage.

AC TEST LOADS
319

319
3.3V

3.3V

OUTPUT

OUTPUT
30 pF
Including
jig and
scope

5 pF
Including
jig and
scope

353

Figure 1

353

Figure 2

AC TEST CONDITIONS

Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing and Reference Level
Output Load

Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2

Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774

Rev. F
12/15/2011

IS61LV25616AL

AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil, UB or LB = Vil)

t RC
ADDRESS

t OHA
DOUT

t AA

t OHA
DATA VALID

PREVIOUS DATA VALID

READ1.eps

READ CYCLE NO. 2(1,3)

tRC
ADDRESS

tAA

tOHA

OE

tHZOE

tDOE
tLZOE

CE

tACE

tLZCE

tHZCE

LB, UB

DOUT

VDD

Supply
Current

HIGH-Z

tBA

tLZB

tHZB

tRC
DATA VALID

tPU

50%

tPD

50%

ICC
ISB
UB_CEDR2.eps

Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = Vil.
3. Address is valid prior to or coincident with CE LOW transition.

Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774

Rev. F
12/15/2011

IS61LV25616AL

READ CYCLE NO. 2(1,3)

tRC
ADDRESS

tAA

tOHA

OE

tHZOE

tDOE
tLZOE

CE

tACE

tLZCE

tHZCE

LB, UB

DOUT

VDD

Supply
Current

HIGH-Z

tBA

tLZB

tHZB

tRC
DATA VALID

tPU

tPD

50%

50%

ICC
ISB
UB_CEDR2.eps

Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = Vil.
3. Address is valid prior to or coincident with CE LOW transition.

WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)

Symbol
Parameter
twc
Write Cycle Time


tsce
CE to Write End


taw
Address Setup Time to Write End

tha
Address Hold from Write End


tsa
Address Setup Time


tpwb
LB, UB Valid to End of Write


WE Pulse Width


tpwe1
tpwe2
WE Pulse Width (OE = LOW)


tsd
Data Setup to Write End


thd
Data Hold from Write End


thzwe(2) WE LOW to High-Z Output


(2)
tlzwe
WE HIGH to Low-Z Output

-10
Min. Max.
10
8
8
0
0
8
8
10
6
0
5
2

-12
Min. Max.
12

8

8

0

0

8

8

12

6

0

6

2

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V
to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing
are referenced to the rising or falling edge of the signal that terminates the write.

Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774

Rev. F
12/15/2011

IS61LV25616AL

AC WAVEFORMS
WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1)
t WC
VALID ADDRESS

ADDRESS

t SA

t SCE

t HA

CE

t AW
t PWE1
t PWE2

WE

t PBW
UB, LB

t HZWE
DOUT

t LZWE
HIGH-Z

DATA UNDEFINED

t SD

t HD

DATAIN VALID

DIN

UB_CEWR1.eps

Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).

WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2)
t WC
ADDRESS

VALID ADDRESS

t HA
OE

CE

LOW

t AW

t PWE1

WE

t SA

t PBW

UB, LB

t HZWE
DOUT

DATA UNDEFINED

t LZWE
HIGH-Z

t SD
DIN

t HD

DATAIN VALID
UB_CEWR2.eps

Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774

Rev. F
12/15/2011

IS61LV25616AL

AC WAVEFORMS
WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1)
t WC
ADDRESS

VALID ADDRESS

OE

LOW

CE

LOW

t HA

t AW

t PWE2

WE

t SA

t PBW

UB, LB

t HZWE
DOUT

t LZWE
HIGH-Z

DATA UNDEFINED

t SD

t HD

DATAIN VALID

DIN

UB_CEWR3.eps

WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3)

t WC
ADDRESS

t WC

ADDRESS 1

ADDRESS 2

OE

t SA
CE

LOW

t HA
t SA

WE

UB, LB

t HA

t PBW

t PBW

WORD 1

WORD 2

t HZWE
DOUT

t LZWE
HIGH-Z

DATA UNDEFINED

t HD

t SD
DIN

DATAIN
VALID

t HD

t SD
DATAIN
VALID

UB_CEWR4.eps

Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in
valid states to initiate a Write, but any can be deasserted to terminate the Write. The t sa, t ha, t sd, and t hd timing is referenced
to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.

10

Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774

Rev. F
12/15/2011

IS61LV25616AL

DATA RETENTION SWITCHING CHARACTERISTICS (LL)

Symbol
Parameter
Test Condition
Vdr
Vdd for Data Retention
See Data Retention Waveform
Idr
Data Retention Current
Vdd = 2.0V, CE Vdd 0.2V



tsdr
Data Retention Setup Time See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25 C and not 100% tested.

Options

Com.
Ind.

Min.
2.0


0
trc

Typ.(1)

5

Max.
3.6
10
15

Unit
V
mA
ns
ns

DATA RETENTION WAVEFORM (CE Controlled)

tSDR

Data Retention Mode

tRDR

VDD
1.65V

1.4V

VDR

CE
GND

CE VDD - 0.2V

Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774

Rev. F
12/15/2011

11

IS61LV25616AL

ORDERING INFORMATION
Commercial Range: 0C to +70C
Speed (ns)

10





12

Order Part No.

IS61LV25616AL-10T
IS61LV25616AL-10TL
IS61LV25616AL-10K
IS61LV25616AL-12T

Package
TSOP (Type II)

TSOP (Type II), Lead-free
400-mil SOJ
TSOP (Type II)

Industrial Range: 40C to +85C

Speed (ns)

10















12

12

Order Part No.

IS61LV25616AL-10TI
IS61LV25616AL-10TLI
IS61LV25616AL-10KI
IS61LV25616AL-10KLI
IS61LV25616AL-10LQI
IS61LV25616AL-10LQLI
IS61LV25616AL-10BI
IS61LV25616AL-10BLI
IS61LV25616AL-12TI

Package
TSOP (Type II)

TSOP (Type II), Lead-free
400-mil SOJ


400-mil SOJ, Lead-free
LQFP


LQFP, Lead-free
Mini BGA (8mm x 10mm)
Mini BGA (8mm x 10mm), Lead-free
TSOP (Type II)

Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774

Rev. F
12/15/2011

IS61LV25616AL

Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774

Rev. F
12/15/2011

13

14
SEATING PLANE

4. Formed leads shall be planar with respect to one another within 0.1mm
at the seating plane after final test.
5. Reference document : JEDEC SPEC MS-027.

3. Dimension b2 does not include dambar protrusion/intrusion.

2. Dimension D and E1 do not include mold protrusion .

1. Controlling dimension : mm

NOTE :

12/21/2007

IS61LV25616AL

Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774

Rev. F
12/15/2011

Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774

Rev. F
12/15/2011

Package Outline

06/04/2008

3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.

2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.

1. CONTROLLING DIMENSION : MM

NOTE :

IS61LV25616AL

15

16

08/12/2008

Package Outline

2. Reference document : JEDEC MO-207

1. Controlling dimension : mm

NOTE :

IS61LV25616AL

Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774

Rev. F
12/15/2011