A 1.6-880MHz Synthesizable ADPLL in O.

13um CMOS
Hsiang-Hui Chang, Shang-Ming Lee, Chao-Wen Chou, Yu-Tung Chang and Yi-Li Cheng
MediaTek Inc., Hsin-Chu, Taiwan
Abstract
A synthesizable all digital phase-locked loop (ADPLL)
with an improved DCO and a frequency-bouncing-reduced
algorithm is presented. The ADPLL covers 1.6 - 880 MHz
frequency range while maintaining high frequency
resolution. The synthesizable ADPLL can be easily migrated
to different processes and foundries; requires less design
time and maintain effort; and directly benefit from CMOS
technology scaling. The PLL is fabricated in a 0.13-um
IP6M high-Vt CMOS process and occupies an active area of
220x220 um2 The PLL consumes a maximum power of 16
mW and has 114ps peak-to-peakjitter at 880MHz.

"",--,""'CCDCO
Offset compensation
circuit

TH[S:O]. ----"MAXG 8:0

Gain
MING[8:0] controller

M[2:0]

1M

Fig.1 Proposed PLL architecture

I. Introduction
Traditionally, analog phase-locked loops (PLLs) have
better jitter and skew performance when compared to digital
PLLs. However, their migration to different technology
nodes requires time-consuming redesign. In addition, the
associated loop filter capacitor usually occupies considerable
area, and potentially has leakage problem if MOS capacitors
are used. The leakage problem becomes more severe as
CMOS feature size continues to scale down. Alternatively,
digital PLLs can easily migrate to different processes,
provide re-configurability, and solve the leakage issue by
using digital loop filter. Thanks to process scaling, the
digital PLLs also operate at a lower supply voltage and has
the potential for good power-management. [1-5]
To successfully achieve a wide operating range, the
conventional digital PLL demands a digital-controlled
oscillator (DCO) composed of high-bandwidth delay units.
To implement such a PLL under reasonable area constraint,
the tradeoff between the bandwidth ofa single delay unit and
the number of stages in a DCO will substantially limit the
ratio of the highest to the lowest operating frequency. The
PLLs usually need a calibration circuit to pre-determine the
suitable frequency band to achieve such as wide frequency
range. Even if the PLLs are in lock both temperature
variation and changing in dividing ratio can cause the PLLs
to lose lock, and the correct sub-bands must be determined
again through recalibration. If the reference clock varies to
meet different product's specifications, the calibration
circuits must be redesigned accordingly.
In this paper, the proposed DCO breaks the trade off
between the delay cell bandwidth and the number of delay
stages. The overall hardware complexity is reduced at a
given operating frequency range and timing resolution. The
frequency-bouncing-reduced algorithm maximizes the
re-configurability of the ADPLL. This algorithm guarantees
the ADPLL lock without any aid from calibration circuits,
even during sub-band switching, during dividing ratio
changing, or under temperature variation. No switching
back-and-forth between sub-bands also improves jitter
performance. The proposed ADPLL can be synthesized with

978-1-4244-1616-5/08/$25.00 2008 IEEE

GAIN[8:0]

Control codes

Dca

1M
Cycle[8:0]

Fig.2 Conventional wide-range DCO

a standard cell library and is suitable for advanced
deep-submicron technologies.
II. Architecture of the ADPLL
The architecture of the proposed ADPLL is shown in Fig.
I. It is composed of a PFD, a TDC, an offset compensation
circuit, a digital loop filter (DLP), a gain controller, a
decoder, a programmable divider, and a cycle-controlled
DCO (CCDCO). Initially, unavoidable static phase error
caused by automatically synthesis of PFD and TOC can be
calibrated by the offset compensation circuit. The TOC
generates T[5:0] according to the phase difference between
the reference clock (REF) and feedback clock (FB). The
gain controller will continuously monitor the difference
between T[5:0} and TH[5:0} and dynamically adjust the
gain of the DLF to reduce lock time. The gain range of the
DLF is limited by MAXG[8:0} and MING[8:0},
respectively. After digital filtering, the decoder applies the
frequency-bouncing-reduced algorithm to determine the
optimal values of Cycle[8:0}, /[4:0}, and F[4:0},
respectively, and controls the frequency of CCDeO. With
the proposed algorithm, the AOPLL automatically locks
over a wide range operation regardless of the initial
condition, without any auxiliary circuit. All building blocks
in the ADPLL are RTL-based and are synthesizable,
considerably reducing the design time and maintain efforts.
III. Circuit description
A. Cycle-controlled DCO
In Fig.2, a DCO with a post divider can achieve a wide
operating range. The period of DCa is determined by

T_conventional=Cycle[8:0]NTd

(1)

Pi(i=O-15)

114:0J

-Nstages' ) Re-cycle loop

01

Digital phase
selector

' ) Normal loop

F14:01

Trig

2nd-order
Sigma-Delta
Modulator

WI2:0]

Digital
Interpolator

DCO_CU<J4

Fig.5

Fig. 5 shows the L6 digital interpolator. The parallel

tri-stage buffers serve as a digital interpolator. The
weighting number of interpolation is dithered by a 2nd order
digital L6 modulator. An edge-triggered DFF is inserted in
the re-cycle loop to avoid incomplete switching of output
clock due to mismatch of NMOS and PMOS driving
capability. No analog or custom-designed circuit is used.
The synthesizability of the proposed CCDCO is especially
attractive for advanced deep-submicron technologies.

1[4:0),F[4:0)

Fig.3 Schematic of the proposed CCDCO

o -.~-----JlJ1M-Con

02

Re-cycle loop

B. Frequency-bouncing-reduced algorithm
To ensure the ADPLL lock without any aid from
calibration circuits and avoid frequency bouncing between
two adjacent sub-bands in a DCO, the frequency
-bouncing-reduced algorithm is proposed. Fig. 6 shows the
implementation of the decoder. First, LF[16:0] is divided by
N. The decoder will generate two sets of control codes: one
is Cyclel[8:0J and IJ[4:0J; the other is Cycle2[8:0J and
12[4:0J according the following equation.

.. Normal loop

Fig.4 Timing diagram of the CCDCO

where Td is the delay time of one delay stage, N is the
number of delay stage in the DCO, and Cycle[8:0J is the
dividing ratio, respectively. As indicated in (I), the
minimum timing step is increased by a factor of Cycle[8:0J,
degrading the frequency resolution at larger frequency
dividing ratio.
The proposed CCDCO in Fig.3 solves this problem. It is
composed of a multiplexer (MUX), a de-multiplexer
(DEMUX), one DFF, N delay stages in the re-cycle loop,
2N delay stages in the nonnal loop, one control circuit, and
one L6 digital interpolator. Each delay stage is composed of
two inverters. The timing diagram is illustrated in Fig. 4.
Con controls the CCDCO to operate in a re-cycle loop or a
normal loop. Once the clock propagates through the re-cycle
loop, Trig will trigger the control circuit to count
downward. The count value is detennined by the DLF. The
state of the re-cycle loop will be held until the count value
of the control circuit reaches O. The DCO will be
re-configured and work in a nonnal loop. The coarse tuning
is detennined by the delay of the re-cycle loop. The fine
tuning is achieved by digital interpolation with high speed
dithering. No analog tuning technique is used. The period
of the CCDCO is digitally controlled and can be expressed
as:

T--Pfoposed=Cycle[8:0}N-Td+I[4:0]-Td
+SDM(F[4:0]}(Td/8)

Schematic of the L6 digital interpolator

Cycle2[8:0]=Cyclel [8:0]-1
12[4:0]=11 [4:0]+N

(3)

The Cycle_d[4:0] is the selected value in previous decision.

Control is detennined by the following equation:

Contfol=if(D1>D2)
Dl =Cyclel [8:0]-Cycle_d[8:0]
D2=Cycle2[8:0]-Cycle_d[8:0]

(4)

The MUX selects final output according to the value of

Control. An example operation of the proposed algorithm is
described in Fig. 7. The tuning characteristic of DCO is
distributed over multiples of overlapped sub-bands. A
DCO with such a frequency characteristic can cover
wide-range and produces low jitters. In this example, the
PLL searches the optimal point upward and N=8. In step 1,
Dl> D2, Cycle2[8:0J(=1) and 12[4:0J(=15) are selected as
final outputs. In step 2, Dl< D2, Cyclel[8:0J(=2) and I
[4:0J(=8) are selected as final outputs. When the frequency
search approaches the band edges, the next searching point is
set to the center of next sub-band. The new frequency of
DCO will be slightly different from the pervious decision.
The frequency-bouncing-reduced algorithm produces m~ch
smaller frequency discontinuity than the sequentIal
frequency search algorithm. In the sequential search
algorithm, the next searching point will be in the beginning
of the next sub-band. If the locked point is near the band

(2)

where SDMO represents the high speed L6 dithering

function and N=8. Compared to eq. (I), the proposed
CCDCO can operate over a wide frequency range while
maintaining highest frequency resolution.

10

LF[16:0]

T[5:0]

Cycle1[8:0]

11[4:0]

o
Cycle[8:0]

Fig.6

Implementation of the proposed algorithm

T=1/Frequency
I
I
I
I
Locked pOin~

C,,',[8,0]

Fig.9

~tepl
I
I

Sequential search algorithm

Initial
step 1

step 2

'1eP3
step 4

IF(16:0)
22
23

Cyde_d(8:0] Cydel(8:0)

24
25
26

Fig.7

1
1

2
3

2
2

3
3

11(4:0)

7
0
1
2

D.DLF
To stabilize the loop, all poles of the close-loop transfer
function must be within the unit circle [4]. The latency of
individual blocks should be also taken into account. The gain
of the DLF can be dynamically controlled to reduce the lock
time. In this design, the Z-domain representation of the DLF
can be expressed as

1[4:0),F[4:0)

Cycle2t8:0)

12(4:0)

Cyde{8:0]

114:01
14

15

1
1

2
2

2
2

10

Die photograph

15

r1

DLF(Z)=G(l-O.8Z-4f(1-Z-4

10

(5)

Example of the locking process

IV. Measurement results
The ADPLL is fabricated as an IP in a IP6M high-Vt
O.13um CMOS process as shown in Fig.9. The
measurements presented are after packaging in QFN44. The
active area of the proposed ADPLL is 220x220 um2
including 3-wire control. The DCO output clock has a low
duty cycle and is not suitable for driving test pads and
instruments. Instead, the divided-by-2 clock of the DCO is
measured. In high and low operating frequency bands, the
measured maximum timing steps are 31 and 35 ps,
respectively. The dividing ratio is 8 and supply voltage is
1.2V. Fig. 10 and Fig 11 show the measured jitter when the
ADPLL operates at 880MHz and 1.6MHz, respectively.
When input frequency is 110MHz, the measured
peak-to-peak of the cycle-to-cycle jitter is 114 ps. The
proposed CCDCO operates over a wide frequency range
while maintaining high frequency resolution. Fig. 12 shows
the jitter performance over different operating frequency.
Since the number of cycle time of the CCDCO is
proportional to the period of the input clock, the clock
propagation path will be longer in the low-frequency
operation. For this reason, the absolute jitters in low

edge, the sequential frequency search algorithm may cause

the sub-band to switch back and forth, leading to higher jitter
or even PLL instability. With the proposed algorithm, the
decoder will update Cycle[8:0J and 1[4:0J between two sets
of control code in each decision. Only a small discontinuity
in DCO frequency occurs when the sub-bands switch. It
guarantees the PLL lock and avoids locking near the band
edges to reduce jitter. The ADPLL will automatically lock
over a wide range operation regardless of the initial
condition without any auxiliary circuit. For different
products, the overhead ofthe ADPL can be minimized.
e. PFD+TDC
The PFD and counting-based TDC [5] provide frequency
and phase locking function and are shown in Fig. 8. UP and
DN pulses generated by the tri-state PFD are digitized by the
TDe. Unavoidable static phase error caused by
automatically synthesis can be digitally calibrated by the
offset compensation circuit. To reduce hardware complexity,
a NAND gate is used as a unit cell in the TDC so that the
decoder can be replaced by a simple summer.

11

TablIP
e
erfiormance summa y
II

21

~.5um

Process

k::MOS
150-550MHz
125ps
125ps

Operation frequency
ITiming/freQuency resolution
putput p.p. jitter

~200MHz

pesign type

nalog
full custom

!Yes

Yes
1.0S*1.0S
1mm"2

~OOOgates

Area

CMOS
150K-60MHz
170ps
1.59ns
Cii160.S09MHz

~alog

ifull custom

Svnthesizable

~.65um

31
O.6um
CMOS
10-SOMHz
1.5ns
I.5ns
(tiJ.7SMHz
~TL

i+analog
full custom
No
I.S
nun"2

i--------~---------;---------------

.-

"

~_C

11:U","

1137)7,.

=.

113.'''''

.-

42S.1_

,-"'-

11:1.7 ...

.:

15.225<1.]
J

Fig. 10 Measured e r diaram @880MHZ

[:I=I~~:~"~~ft~~~~:=~_~=;=::,]
~- ---,----~--- ---------------;---_______ __
P1:~)

P2:1rIq(C3)

1.2..
1.2 ..

17822_
lI01.56_
1.2t8llllttl
,5.31:ze,.3

_ .:

---=-::=:1

1.2.._
1.242 ..
800.2210_

1
J

Fig. 11 Measured jitter diagram @1.6MHz

i 1~~~
~

600

~ :~~

1mm"2

N/A

'RTL

i+analog
full custom
l'lo

NA

114ps

~SSOMHz

IRTL
lYes
~.22*0.22

Imm"2

VI. References

1400

1200

~.26*0.26

1.6-SS0MHz

12000/256 Hz !<35ps

[1] J. Dunning, et aI., "An All-Digital Phase-Locked Loop with

50-Cycle Lock Time Suitable for High-Performance
Microprocessors," IEEE J. Solid-State Circuits, vol. 30, pp. 412
- 422, Apr. 1995.
[2] T. Watanabe, et aI., "An All-Digital PLL for Frequency
Multiplication by 4 to 1022 With Seven-Cycle Lock Time,"
IEEE J Solid-State Circuits, vol. 2, pp. 198 - 204, Feb. 2003.
[3] L. Xiu, et aI., "A Novel All-Digital PLL With Software
Adaptive Filter," IEEE J Solid-State Circuits, vol. 39, pp. 476 483, Mar. 2004.
[4] T. Olsson, et aI., "A Digitally Controlled PLL for SoC
Applications," IEEE J Solid-State Circuits, vol. 39, pp. 751 760, May. 2004.
[5] R. B. Staszewski, et aI., "A Digitally Controlled Oscillator in a
90nm Digital CMOS Process for Mobile Phones," IEEE J.
Solid-State Circuits, vol. 40, pp. 2203 - 2211, Nov. 2005.

31S1200710.202S .......

"E

lYes

~MOS

VI. Acknowledgments
The authors appreciate the supports from the colleagues of
MideaTek RF/ACD, DT, and WCP/SA divisions. The
authors also would like to thank Professor S. -I. Liu and Dr.
J. -H. C. Zhan for useful discussions.

f--=E=:=:_;::=-L:lrT:_E-J=:=:~-'

-..
......
_

IRTL-

~.13um

V. Conclusions
This paper presents a wide-range synthesizable ADPLL.
The improved CCDCD increases the operating frequency
range of the proposed ADPLL without sacrificing timing
resolution. The frequency-bouncing-reduced algorithm
ensures the ADPLL lock to the input clock automatically
and improves jitters. The proposed ADPLL can be
automatically synthesized with a standard cell library and is
suitable for the advanced deep-submicron technologies. The
operating frequency, frequency resolution, clock jitter,
power -consumption and die area of the ADPLL improves
with technology scaling. The ADPLL provides great
flexibility while requires much less design and maintain
efforts.

--_.-

Plr.-.gl(l'l)

~5MHz

tI'his work

1'1.

Fr~+JiTJ+~~!m-F~j
_.-

CMOS
I52-366MHz
ISOps
l664ps

51
90nm
('MOS
3.6GHz

frequency are worse than those in high frequency. After

normalization to the period of the input clock period, the
jitters are relatively small. Table I summaries the
performance summary of the proposed ADPLL.

;,[ -------------------------

I::

41
~.35um

-\-

--

o
10

100

Frequency (MHz)

1000

Fig.l2 Jitter performance over different operating frequency

12