CML Circuit

Advantages of Using CMOS
Compact (shared diffusion regions)

Very low static power dissipation
High noise margin (nearly ideal inverter voltage transfer characteristic)
Very well modeled and characterized
Mechanically robust
Lends itself very well to high integration levels
Analog CMOS process usually includes non-salicided poly layer for
linear resistors.
SiGe BiCMOS is very useful but is a generation behind currently
available standard CMOS
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
Transistor fT Calculation
VDD
id
ig
vgs
Cgs
fT is the frequency at which

W
VGS Vt
L
= WLCox
gm = Cox
Cgs
VGS
id
gm
=
i g 2fCgs
becomes 1.
T = 2fT =
VGS Vt
2
L
fT gives a fundamental speed measure of a technology.
0.25 m CMOS: fT ~ 23GHz

0.18 m CMOS: fT ~ 57GHz
(VDD = 2.5V)
(VDD = 1.8V)
2
Static CMOS propagation delay:
Wp
Lp
Vout
Vin
Wn
Ln
Wp
Lp
Wn
Ln
Wn
VDD Vt
Ln
CL
rise
Wp
VDD Vt
Lp
Assume: Wp = 3Wn for optimum noise margin.

Lp = Ln = Lmin
rise = fall =
CL
fall
Lmin (Wp +Wn )Cox

W
nCox n (VDD Vt )
Lmin
L2min
=
n
# W &
1
4
=
%%1+ p ((
$ Wn ' VDD Vt T
Operation is 4X slower than theoretical
maximum due to n-channel & p-channel

gates connected in parallel.
(Actual values will be higher

due to high diffusion
capacitances present in submicron transistors.)
3
Verifying with simulation:

n-channel ac simulation
to determine fT:
CMOS inverter transient simulation:

IG
Vin
Vout
ID
= 18ps
fT = 57GHz
6.4
T
4
Single-Ended Signaling in CMOS
VDD
Vin
IDD
Vin
Vout
Vout
ISS
ISS
sub
IDD
VSS
Series R & L cause supply/ground bounce.

Resulting modulation of transistor Vts result in pattern-dependent jitter.
Effect of Supply/Ground Bounce on Jitter

VDD
"
data in
data out
clock in
clock out
VSS
"
Rs = 5 Ls = 5nH
VDD
"
clock out
Rs = 0
Ls = 0
clock out
Rs = 5
Ls = 5nH
VSS
"
data out
Summary of CMOS Gate Performance

Advantages of static CMOS gates:
1.
2.
3.
Simple & straightforward design.

Robust operation.
Nearly zero static power dissipation.
Disdvantages of static CMOS gates:

1.
2.
3.
Full speed of transistors not exploited due to n-channel & pchannel gate in parallel at load.
Single-ended operation causes current spikes leading to VDD/
VSS bounce.
Single-ended operation also highly sensitive to VDD/VSS bounce
leading to jitter.
Current-Mode Logic (CML)

CML inverter:
VDD
R
Vout+
Vin+
Based on conventional differential pair
Vout-
CL
CL
ISS
Differential operation
Vin-
Inherent common-mode rejection

Very robust in the presence of commonmode disturbances (e.g., VDD / VSS bounce)
DC Biasing of CML Inverter

VDD
R
VIN(DC )
1
ISS R
2_
1
ISS R
2 _
VOUT(DC )
VOUT(DC )
W
L
VGS _
1
Vin(DC ) = Vout (DC ) = VDD ISS R
2
VS
W
L
ISS
To keep current source transistor in saturation:
)
VIN(DC
+
VGS
VS > VBIAS Vt
VS = Vin(DC ) VGS
VBIAS
Vin(DC ) > VBIAS + (VGS Vt )
Logic Swing & Gain of CML Inverter

Vhigh = VDD
Vlow = VDD ISS R
VDD
R
VDD-ISSR
ISS
VDD
VDD
CL
CL
W
L
W
L
To achieve full current switching:
VDD-ISS
R
ISS
Vswing = ISS R
Vswing VGS Vt
|I D =ISS
2ISS
nCox
W
L
Vmin
Vswing
1
W
=R
Cox
ISS
Vmin
2
L
Vswing
> 1 for correct operation
Vmin
10
Small-Signal Behavior of CML Inverter
Small-signal voltage gain:
Av = gm R = R Cox
Recall
rise/fall time constant:
W
L SS
Vswing
1
W
=R
Cox
ISS > 1
Vmin
2
L
Vswing Av
=
Vmin
2
= RCL (Assuming fanout of 1)

CL = CoxWL
Av 2
for full switching
= R(WLCox )
Note: rising & falling
time constants are the same
11
Speed vs. Gain in Logic Circuits
fast input transition:
step response determined by
slow input transition:
step response determined by Av
Largest possible gain-bandwidth product is desirable.
12
Relationship between Av , , and Vswing

Av = R nCox
Av2 = nCox
W
L SS
ISSR2 = n2 RWLCox ISSR

L
L
)(
n
A = 2 Vswing
L
2
v
Vswing
Av2 n
= 2 Vswing
large-signal gain-bandwidth product
Larger logic swing preferred for higher gain-bandwidth product

Larger Vswing Larger Vmin smaller W/L larger current density
13
Thought Experiment
W
L
W
L
W
L
W
L
ISS
ISS
Suppose we decrease current density by increasing W/L:
W
1
2 Vmin
, CL 2
L
2
= RC 2
R
Slower!
2
14
Note that the load is only one gate capacitance:

= RCL = R
gm Av
2
=
T T T
CML speed ~ 2.5 times faster than static CMOS
n-channel ac simulation
to determine fT:
CML buffer transient simulation:

IG
ID
= 8ps
2.9
T
fT = 57GHz
Irvine
Prof. M. Green / U.C.
15
Typical Vswing: 0.3 VDD

Should be large enough to allow sufficient gain-bandwidth product.
Should be small enough to prevent transistors from going into triode.
* CML
will still work in triode (unlike BJT), but there is no additional
speed benefit.
Vswing = ISS R
Once Vswing has been chosen, designer can trade off between gain &
bandwidth by parameterizing between R & ISS:
= R(WLCox )
Av = R Cox
W
L SS
Higher speed: ISS
Higher gain:
ISS
16
Other Benefits of CML Gates
1.
Constant current bias VDD / VSS bounce greatly reduced

ISS
KCL sets this current to be nearly constant.
ISS
17
VDD
"
data in
data out
clock in
clock out
VSS
"
Rs = 5 Ls = 5nH
clock out
Rs = 0
Ls = 0
VDD
"
VSS
"
clock out
Rs = 5
Ls = 5nH
data out
18
2. Non-inverting buffer available without additional delay:

CMOS:
tp
2tp
inverter
buffer
CML:
Vout+
Vin+
Vout
Vout
Vin
buffer
inverter
Vin
Vin+
Vout+
19
Fanout & Scaling of CML Gates
R
Vout-
1x
Vin+
W
L
R
Vout+
W
L
Vin-
ISS
R/n
Vout-
R/n
Vout+
W
L
W
n
L
nx
Vin+
Vin-
All voltages unchanged from unit-sized buffer.

Currents & power increase by factor of n.
nISS
20
For fanout of n:
= nCL R
Av2
2
=
V
2 swing
nL
increases linearly with fanout.
21
From interconnect, etc.; assumed not to scale with buffer sizes
%
C
= nCL + Cp R / n = WLCox R ''1+ p
& nCL
)(
nW
ox L
2
v
A = 2nC
)(
nISS R / n
= 2nCox
(
**
)
W
L
ISSR2
1
%
(
C
A
2
p
**
= 2n Vswing ''1+
L
& nCL )
2
v
Should set n 0.1 Cp / CL to minimize

degradation due to interconnect capacitance
Power (proportional to n) determined primarily by interconnect capacitance!
22
Sub-micron MOSFETs obey square-law characteristics only in a limited region!

ID
ID
Mobility reduction (linear)
+
V
GS _
Square-law behavior
Weak inversion (exponential)
VGS
CML buffer design procedure:

1.
2.
Determine largest allowable ISS (usually limited by electromigration constraints)

Choose unit-sized n-channel transistor (typically W/L=20)
3.
Run a series of simulations to determine optimum value of R:

R too small: full current switching not achieved
R too large: slower than necessary
4.
Choose minimum scaling factor after laying out some test buffers of various
sizes and determining approximate value of interconnect capacitance Cp.
23
1. Determine largest allowable ISS
standard layout
shared drain
(1/2 diffusion capacitance)
ID I max
Imax independent of W
determined by electromigration limits
24
CML Design Procedure

Example
Choose: ISS = 400A
R = 900
ISSR = 360mV
tp = 10ps
R too small
W
4 m
=
L 0.18 m
R = 1200
ISSR = 480mV
tp = 12ps
*R optimum*
R = 1500
ISSR = 600mV
tp = 14ps
R too large
25
Parameterizing Between Gain & Bandwidth

ISS = 100 A
R = 4.8 k
Av = 9.3 dB
BW = 2.6 GHz
ISS = 200 A
R = 2.4 k
Av = 7.1 dB
BW = 5.5 GHz
ISS = 400 A
R = 1.2 k
Av = 3.9 dB
BW = 11.5 GHz
26
Parameterized CML Buffer

R
GBW
GSCALE MSCALE
W
GSCALE MSCALE
L
GSCALE MSCALE
ISS
GBW
GSCALE: Global scaling parameter

(depends on Cp)
MSCALE: Local scaling parameter
(depends on fanout or bit rate)
GBW:
Gain-bandwidth parameter
27
CML with p-channel Active Load

Can be used if linear resistors
are not available.
p-channel load transistors operates in triode region:

Increased capacitance and mismatch result
28
Capacitance Comparison (1)
Poly resistor:
p-channel MOSFET:
1
C Cpoly sub
2
1
C Cdepletion + Cchannel gate + Cchannel sub
2
gate
channel
sub
29

(Numbers based on TSMC 180nm CMOS process)
Cpoly-sub Cchannel-sub : 0.13 fF/m2

Cdepletion : 1.20 fF/m2
Cchannel-gate : 7.80 fF/m2
Poly resistor:
p-channel MOSFET:
1
C Cpoly sub
2
Wpoly = 0.6
Lpoly = 2.5
= 0.1 fF
= Wdiff = 2.5 m
Wchannel
Lchannel = 0.18 m
Ldiff = 0.3 m
C Cdepletion +
=
0.9 fF
1
Cchannel gate + Cchannel sub
2
+ 1.8 fF + .03 fF
)
= 2.8 fF
30

R = 1.2 k
s = 235 /!
Wr = 0.6 m
Lr = 2.5 m
Cres = 0.1 fF
M1
Wp = 2.5 m
Ldiff = 0.3 m
Cd2 = 2.8 fF
M1
M2
M2
M1
M1
Cd1 = 3.7 fF
Cg1 = 5.8 fF
31
Pulse Response Comparison

PWin = 100ps
resistor load
R = 1.2 k
td = 16 ps; PWout = 100 ps
p-channel load
(W/L)p = 2.5 m / 0.18 m
td = 20 ps; PWout = 98 ps
32
Eye Diagram Comparison

including mismatch effects
resistor load
p-channel load
ID
R
= 1.5% mismatch
R
ID
= 4% mismatch
160mV gate-referred mismatch
DCD
ISI
33
Series-Gated CML Topology

XOR gate:
MA
MA
MA
MB
MA
MB
Common-mode voltage of BP/N critical:

Too low current source transistor biased in triode
Too high Transistors MB biased in triode

34
Series-Gated CML (2)

VS
I1
BP
I2
BN
VBP VBN
I1 I2
ISS
Transistors should be biased in saturation

to realize maximum gm .
Especially important when gate voltages exhibit
slow slew rates
VBP VBN
Slope = gm
-ISS
35
IBP IBN
VB(cm) = 1.0
VB(cm) = 1.3
VB(cm) = 1.6
DC current:
IBP IBN
VB(cm) = 1.3
VB(cm) = 1.0
VBP VBN
Transient response:
(400mV amplitude sine
wave applied to BP/BN)
VB(cm) = 1.6
t
36
Level-Shifting CML Buffer

Used to drive clock inputs
of series-gated CML gates
VDD
Output levels:
+
ISS Rcm
Rcm
Vlow
(
= (V
)
) I
Vhigh = VDD ISSRcm
DD
ISSRcm
SS
Vswing = ISSR
ISS
DC levels shifted down by ISSRcm

Vswing unchanged
37
CML Select Circuit

Be reassigning the inputs, the XOR can be transformed into a Select
circuit. Used in a 2:1 multiplexer.
SELA
R
OUTP
OUTN
AP
AN
BP
SELA
BN
SELB
ISS
AP/N
BP/N
OUTP/N
38
CML Latch
By setting BP/N = OUTP/N, we can construct a CML latch:
OUTP
OUTN
DP
DN
CKP
CKN
ISS
39
CML D Flip-Flop
XP
XN
OUTP
OUTN
DP
DN
CKP
XP
CKN
XN
CKN
CKP
CKP/N
Output OUTP/N is synchronized with
CKP/N falling edge.
DP/N
OUTP/N
40
CML Latch Design Considerations

IGG
R
slope=1/rgg
VGG
1
ISS
2
dc operating points
VGG
Necessary criterion for bistability:

IGG
rgg =
2
2R
=
<0
1/ R gm 1 gm R
at middle operating point
(Equivalent to loop gain = gmR > 1)
41
Avoiding Latch Transparency
gm R > 1
gm R 1
XP/N
gm R 1
transparent latch
42
QIN
XN
DP
XP
QIP
OUTP
OUTN
QIP
XP
DN
CKP
CKN
QIN
XN
CKN
CKP
GBW parameter
can be increased to
ensure bistability.
R=1000
gmR > 1
R=800
gmR 1
R=600
gmR < 1
43
Buffering Clock Signals (1)

Clock signals (generated from VCO or clock divider) often drive large capacitive loads.
1x
1x
1x
C
Fanout = n
= nRC f3dB =
1
2
For a large fanout, attenuation of clock amplitude will occur.

44

ktp
1x
nx
kx
k2
m stages
Now is increased by k << n
less attenuation at each stage
Delay = mktp
Power = P1(1 + k + k2 + + n)
Power dissipated by first stage
As fclock 1/tp then k 1; number of stages and total power become very large.
45

Since clock signal is made up of a single frequency (+ harmonics),
resonance can be used to increase gain with greatly reduced power dissipation.
1
1
(1 2LC) + j (L / R)
Y = + jC +
=
R
j L
jL
1
Resonant frequency: r =
LC
Y=
1
at resonance
R
If lossless inductors were available, we could achieve high gain at any frequency
simply by choosing the correct inductor value.
46
On-Chip Passive Elements

l
Resistor:
l
R=
t w
Capacitor:
C lw
(+ fringing)
substrate
Inductor:
t
) # 2 &
t +w,
l
0.2+ln%
. pH/m
( + 0.50049 +
t
+
w
3
'
l* $
Inductance calculation much more complicated!

47
l
t
) # 2 &
t +w,
l
0.2+ln%
. pH/m
( + 0.50049 +
t
+
w
3
'
l* $
Special case of Greenhouse result
Note for l >> w, L is a weak function of w

To increase effective inductance per unit length, we make use of
mutual inductance via spiral structure:
48
Modeling of Spiral Inductor

1
Accurate lumped model should include:

Series inductance (self + mutual) & resistance
Skin effect (frequency dependent series resistance)
Interwinding capacitance
Capacitance to substrate
Substrate capacitance & loss
number of turns n = 2
Design of inductor requires:

inductor simulation package
(e.g., asitic)
trial and error
conversion to lumped
element model
Procedure for constructing lumped model:

1. 2-port s-parameters over frequency range of interest
(this comes from the inductor simulator)
2. Choose lumped circuit topology.
3. Run simulations to find the optimal lumped circuit
element values such that the the circuit s-parameters
are sufficiently close to the inductors s-parameters
(can use .net and .optimize in HSPICE)
49
Modeling of Spiral Inductor (cont.)

Link to asitic web pages:
http://rfic.eecs.berkeley.edu/~niknejad/asitic.html
Inductor magnitude impedance vs. frequency
Parameters most relevant to circuit designers:

Inductance
Series resistance
Self-resonant frequency
50
Modeling of Spiral Inductor (cont.)

Cint
1
Cox1
Rsub1 Csub1
L:
Rs:
Cint:
Cox:
Csub/Rsub:
Rs
Cox2
Csub2 Rsub2
Self/mutual inductance
Series resistance
Interwinding capacitance
Oxide capacitance
Substrate capacitance/resistance
Values of L and Rs in lumped model should correlate with physical parameters.

Values of other lumped model elements need not necessarily correlate with physical parameters.
51
Parasitic capacitances usually combine with load capacitance L should be decreased slightly
Series Rs has more important effect:
L
C
L'
Rs
Y=
1
1
+ jC +
R
Rs + jL
Y" =
1
1
+ jC +
R"
jL"
At resonance, Im [Y(jr)] = 0:
2
1 $ Rs '
r =
& )
LC % L (
r =
( )
( )
1
R"
L" =
L
1 CRs
2
L
# L &
R
"
=
R
||
%
(
$ CRs '
Slight increase in effective inductance
Very important effect!
1
L#C
Y " j r =
1 CRs
Y j r = +
R
L
52
CML Tuned Amplifiers (1)
Differential-mode ground
Sets common-mode
output voltage
CL resonates out with L

Gain at resonant frequency = gm R
53

Symmetric inductor structure can be used:
Single structure allows more inductance to

be realized from mutual coupling
less series resistance
54

Higher-gain topology:
Gain is much higher at resonance, but depends completely on Rs.

Variation in gain correlates with variation in metal (not resistor) sheet resistance.
55

Watch out for ac current amplitude in inductors!
Iin
IL
Vswing
Vswing
Iin =
R"
Vswing
IL =
L#
Let Vswing = 500mV, L=0.5nH, f =10GHz:
IL = 16mA
Spiral inductor should be wide enough
to meet ac electromigration specs.
56
Inductors in Broadband Circuits

R
LC lossless
transmission line
(Z0)
+
R
Vin
1
H(s) =
2
| H( j ) |
Vout
1
CR
1+ s
2
+
R
Vin
H(s) =
| H( j ) |
0.5
0.5
Vout
_
1 sTd
e
2
for R = Z0
Td = LC
H( j )
2
CR
H( j )
90 !
slope = -Td
57
Series Peaking (1)

With direct connection of 2 buffers,
output & input capacitances are in parallel:
Cd
Cg
By connecting an inductor between the

capacitors, the bandwidth and delay increase:
Lser
Cd
Cg
Series peaking
58
Series Peaking (2)

R
Using R
Vx-
Vin+
Vin-
Lser
Cd
Vx+
Lser
Cd
set Lser Cd R2
Series peaking provides speed at the
expense
of extra delay.
Cg
Cd = Cg = 16 fF
R = 400
Frequency response:
Vx
Vin
Lser = 0
BW = 6.3 GHz
Transient response:
Vx (Lser = 3.5 nH)
Lser = 3.5 nH
BW = 8.3 GHz
Vx (Lser = 0)
#V &
% x (
$ Vin '
Vin
Lser = 3.5 nH
Lser = 0
59
Shunt-Peaking (1)
By connecting an inductor in series with the load

resistor (series connection in shunt with output),
more current is used, for a longer time, to charge
the load capacitance.
60
Properties of Shunt-Peaking
Frequency response:
L
R
Z( j ) = R
2
1 LCL + jCL R
1+ j
CL
L
R
Z(s) = R
1+ sCL R + s 2LCL
1+ s
Resonant frequency:
1 $ CL R2 '
r =
&1
)
LCL %
L (
2
Im s
OX
Re s
L = 0:
L 0:
zero at s = R/L pole at s = 1/RC
additional pole at
s (1/CR + R/L)
No resonance for
L
<1
2
CL R
61
Shunt-Peaking -- AC Response
L
= 0.3
CL R2
CL = 38 fF
L = 1.8 nH
BW = 9.4 GHz
R = 400
Use of shunt-peaking
increases small-signal bandwidth
L
= 0.6
CL R2
L=0
BW = 6.3 GHz
L = 3.7 nH
BW = 14.3 GHz
62
Shunt Peaking Transient Response

Step Response:
Pulse Response (tin = 50 ps):

L = 3.7 nH
tout = 50.8 ps
ISI = 16 mUI
L = 3.7 nH
td = 6.7 ps
L = 1.8 nH
td = 8.5 ps
L=0
td = 13.4 ps
L = 1.8 nH
tout = 50.0 ps
ISI = 0 mUI
L=0
tout = 48.7 ps
ISI = 26 mUI
63
Shunt Peaking ISI vs. Pulse Width

ISI (UI)
L
= 0.6
2
CL R
L
=0
2
CL R
L
= 0.3
2
CL R
Input pulse width

64
Other Advantages of Shunt-Peaking
CML load is passive & linear

Can be shown to be very robust in the presence of parasitic
series resistance and shunt capacitance inductors can be
placed far away from other CML circuit elements.
65
Effect of Shunt-Peaking Inductor Parasitics (1)
L
long metal lines
CL
CL
CP
CP
RP
L
RP
CL
CL
Series resistance RP simply adds to R
Shunt capacitance CP resonates with L

66
Effect of Shunt-Peaking Inductor Parasitics (2)

ISI (UI)
L
= 0.6
CL R2
CP = 0
L
=0
CL R2
Moderate amount of parasitic

capacitance
has similar effect to slightly larger inductor.
L
= 0.3
CL R2
Input pulse width
ISI (UI)
L
= 0.6
CL R2
CP = 0.2CL
L
=0
CL R2
Disadvantages of using passive inductors:

Consume huge die area
Difficult to design & model
L
= 0.3
CL R2
Input pulse width

67
Multi-layer Inductors (1)
metal 6
metal 6
d
metal 5
metal 5
d
Distance d between two metal layers is much smaller than lateral distances
(e.g., w, l, s)
68

2-port representation of coupled inductors:
M = k L1L2
i1
+
1
_
i1
i2
L1
series connection of coupled inductors:
L2
+
1 L1
_
+
2
_
+
L2 2
_
i2
Passivity constraint: k 1
series = 1 + 2 = (L1 + M)i 1 + (L2 + M)i 2
# & ) L M ,# i &
1
% 1(=+ 1
.% (
$ 2 ' *M L2 -$i 2 '
i series = i 1 = i 2
For metal geometries close to each other,

k is close to unity.
Lseries =
series
= L1 + L2 + 2M
i series
For L1 = L2 = L, we have: Lseries = 2L + 2M = 2L(1+ k) 4L

2
In general, for n layers we have: Lseries n L
Multi-layer inductors are more appropriate for shunt-peaking than resonant structures
due to additionalcontact resistance.
69
Effective Capacitance:
Leffective 4L
Ci
1
1
Ceffective Ci + C j
3
12
Cj
For more details, see:

A. Zolfaghari, A. Chan & B. Razavi, Stacked inductors and transformers in
CMOS technology,
IEEE Journal of Solid-State Circuits, vol. 36, April 2001, pp. 620-628.
70

Area comparison:
metal 6 only
100 x 100
w = 4; s = 2; n = 4
L=2.0 nH
R=6.9
metal 6 over metal 4

46 x 46
w = 4; s = 2; n = 2.5
L=2.0 nH
R=12.5
71
Active Inductors (1)
Impedance inversion:
Ideal gyrator:
i1
Rgyr
i2
iin
v1
v2
vin
Rgyr
v 2 = Rgyr i1
( )
2
Zin = Rgyr
sC
v1 = Rgyr i 2
Matrix representation (Z-parameters):
" % )
$ v1 ' = + 0
#v 2 & *Rgyr
Rgyr ," i1 %
.$ '
0 -#i 2 &
Port 1 exhibits inductance when

port 2 is connected to a capacitance.
72

Consider common-drain configuration:
i1 applied with port 2 open-circuited:
v2 =
i2
RG
1
i1
gm
i2 applied with port 1 open-circuited:

v2
_
i1
v1
#
1&
v1 = % RG (i 2
gm '
$
(Assume RG gm > 1)
+
Complete Z-parameters (lossy/active gyrator):
" v % )1 g
$ 1' = + m
#v 2 & +*1 gm
RG 1 gm ," i1 %
.$ '
.-# i 2 &
1 gm
73

Interpretation of non-ideal matrix entries:
" v % )1 g 1 g R ," i %
m
G
1
$ 1' = + m
.$ '
1 gm -#i 2 &
#v 2 & *1 gm
vin
74

Impedance at port 1 with port 2 terminated with transistor Cgs:
At low frequencies (Cgs open) Zsource = 1/gm

At high frequencies (Cgs short) Zsource = RG
Zsource
1 " 1+ sCgs RG %
=
$
'
gm #1+ s Cgs gm &
75

Equivalent circuit:
Zsource
Leff
Cgs RG RG
=
gm
T
RG
1
gm
vin
1
gm
Cgs
gm
Cgs
1
Cgs RG
gmRG > 1
RG
gm
RG
1
gm
76
CML Buffer with Active Inductor Load
Low-frequency gain:
Av =
gm 1
W1
=
gm 2
W2
For shunt peaking:
L 0.3CL R2
"W %
4
$ ' =
# L &1 0.18
gm 2RG = 0.3
CL
Cgs
"W %
2.5
$ ' =
# L &2 0.18
ISS = 400 A
Cgs RG
C
= 0.3 2L
gm 2
gm 2
77
Active Inductor AC Response
RG = 4k
RG = 2k
RG = 0
78
Active Inductor Transient Response (1)
Differential signals:
RG = 0
PW = 97ps
RG = 5k
PW = 100 ps
RG = 10k
PW = 104 ps
79
Active Inductor Transient Response (2)

Single-ended signals:
Problem: n-channel load shifts output by Vt.
Vsb > 0; body effects exacerbates this effect..
Single-ended
input
Single-ended
outputs
80
Active Inductor Alternate Topology

Alternate topology:
p-channel load exhibits lower Vt
(Vbs = 0)
differential
single-ended
81

CML Circuit

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CML Circuit

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Advantages of Using CMOS

Compact (shared diffusion regions)

EECS 270C / Winter 2014

Prof. M. Green / U.C. Irvine

fT is the frequency at which

fT gives a fundamental speed measure of a technology.

0.25 m CMOS: fT ~ 23GHz

Prof. M. Green / U.C. Irvine

Static CMOS propagation delay:

Assume: Wp = 3Wn for optimum noise margin.

Lmin (Wp +Wn )Cox

Operation is 4X slower than theoretical

maximum due to n-channel & p-channel

Prof. M. Green / U.C. Irvine

(Actual values will be higher

Verifying with simulation:

CMOS inverter transient simulation:

Prof. M. Green / U.C. Irvine

Single-Ended Signaling in CMOS

Series R & L cause supply/ground bounce.

EECS 270C / Winter 2014

Prof. M. Green / U.C. Irvine

Effect of Supply/Ground Bounce on Jitter

EECS 270C / Winter 2014

Prof. M. Green / U.C. Irvine

Summary of CMOS Gate Performance

Simple & straightforward design.

Disdvantages of static CMOS gates:

EECS 270C / Winter 2014

Prof. M. Green / U.C. Irvine

Current-Mode Logic (CML)

Based on conventional differential pair

EECS 270C / Winter 2014

Inherent common-mode rejection

Prof. M. Green / U.C. Irvine

DC Biasing of CML Inverter

To keep current source transistor in saturation:

Vin(DC ) > VBIAS + (VGS Vt )

EECS 270C / Winter 2014

Prof. M. Green / U.C. Irvine

Logic Swing & Gain of CML Inverter

To achieve full current switching:

EECS 270C / Winter 2014

Prof. M. Green / U.C. Irvine

Small-Signal Behavior of CML Inverter

Small-signal voltage gain:

rise/fall time constant:

= RCL (Assuming fanout of 1)

EECS 270C / Winter 2014

for full switching

Prof. M. Green / U.C. Irvine

Speed vs. Gain in Logic Circuits

fast input transition:

step response determined by

slow input transition:

step response determined by Av

Largest possible gain-bandwidth product is desirable.

EECS 270C / Winter 2014

Prof. M. Green / U.C. Irvine

Relationship between Av , , and Vswing

ISSR2 = n2 RWLCox ISSR

large-signal gain-bandwidth product

Larger logic swing preferred for higher gain-bandwidth product

EECS 270C / Winter 2014