Вы находитесь на странице: 1из 13

VERIFICATION HORIZ ONS BLOG

SystemVerilog Coding Guidelines: Package import versus


`include
Another frequently asked question: Should I import my classes from
a package or `include them? To answer this properly, you need to
know more about SystemVerilogs type system, especially the
dierence between its strong and weak typing systems.
In programming languages, weak typing is characterized by implicit or ad-hoc
conversions without explicit casting between values of dierent data types.
Verilogs bit vectors, or integral types, represent these weak typing aspects by
implicitly padding and truncating values to be the proper bit lengths at least
proper by Verilog standards. If you perform a bitwise AND of a 7-bit and 8-bit
vector, Verilog implicitly zero pads an 8th bit to the 7-bit operand and returns an
8-bit result. In contrast using VHDL, you would have to explicitly state whether
you wanted the 7-bit operand to be padded, or the 8-bit operand to be truncated
so that you have an expression with operands of equal size.
With a few exceptions, all other types in SystemVerilog follow strong typing
rules. Strong typing rules require explicit conversions or casts when assigning or
expressing operands of unequal types. And understanding what SystemVerilog
considers equivalent types is key to understanding the eect of importing a class
from a package versus including it from a le.
Inheritance aside, SystemVerilog uses the name of a type alone to determine type
equivalence of a class. For example, suppose I have these two class denitions A
and B below:

class A;
int i;
endclass : A

class B;
int i;
endclass : B

SystemVerilog considers these two class denitions unequal types because they
have dierent names, even though their contents, or class bodies, are identical.
The name of a class includes more than just the simple names A and B; the
names also include the scope where the denition is declared. When you declare
a class in a package, the package name becomes a prex to the class name:

POST AUTHOR

Pos ted July 13th, 2010, by


Dave Rich

Share

POST TAGS

IEEE 1800, S, Sys temVerilog,


Verication

POST COMMENTS

21 Comments
ABOUT VERIFICATION
HORIZONS BLOG

This blog will provide an


online forum to provide
weekly updates on
concepts, values,
standards, methodologies
and examples to assist
with the understanding of
what advanced functional
verication technologies
can do and how to most
eectively apply them.
We're looking forward to
your comments and
suggestions on the posts
to make this a useful tool.

@dennisbrophy
Tweets
I love @Uber_SF! Sign up
using my promo code and
get $20 o your rst ride:
http://t.co/hiGLZ k6GRQ
54 minutes ago

package P;
class A;
int i;
endclass : A
A a1;
endpackage : P

package Q;
class A;
int i;
endclass : A
A a1;
endpackage : Q

Now there are two denitions of class A, one called P::A and the other called
Q::A. And the variables P::a1 and Q::a1 are type incompatible referencing two
dierent class As. Re-writing the above example using an include le creates the

After 37 years, we have


Triple Crown Winner!
http://t.co/qoRysr22RI
about 23 hours ago

RT @IEEESA: Guiding
Technology Policy for the
Internet: An IEEE initiative
will focus on governance,
#cybersecurity &
#privacy http://t.co/
2 days ago

same situation two incompatible class denitions.


File A.sv

File P.sv

class A;
int i;
endclass : A

File Q.sv

package P;
`include A.sv"
A a1;
endpackage : P

package Q;
`include A.sv"
A a1;
endpackage : Q

After `including class A into each package, you wind up with two denitions of
class A. Using `include is just a shortcut for cut and pasting text in a le.
Importing a name from a package does not duplicate text; it makes that name
visible from another package without copying the denition.
File A.sv
class A;
int i;
endclass : A

File P.sv
package P;
`include A.sv"
endpackage : P

File R.sv
package R;
import P::A;
A a1;
endpackage : R

File S.sv
package S;
import P::A;
A a1;
endpackage : S

Class A is declared in package P, and only in package P. The variables R::a1 and
S::a1 are type compatible because they are both of type P::A. The fact that class
A was `included from another le once it is expanded is no longer relevant once
you consider the placement of the text from the le.
When you get compiler errors claiming that two types are incompatible even
though they appear to have the same name, make sure you consider the scope
where the types are declared as part of the full name. Class names declared in a
module are prexed by the module instance name, so the same module
instantiated multiple times will create unique class names, all incompatible types.
For further information about packages, check out the June Verication
Horizons article entitled Using SystemVerilog Packages in Real Verication
Projects.

RT @Gizmodo: The world's


rst 10K TV is here and it's
totally unnecessary
http://t.co/Yj4tZ XPAGd
http://t.co/yESLNHupDL
2 days ago
Follow @dennisbrophy

@dave_59 Tweets
RT @mentor_graphics:
The Mixels are making their
way to San Francisco for
#52DAC! Get yours
Monday-Wednesday at
Mentor booth 1432
http://t.
1 day ago

Stop by and say hi


@52ndDAC Verication
Academy Booth 2408 June
8-9th 3-6 both days. Bring a
good #SystemVerilog or
#UVM question
2 days ago

RT @dennisbrophy: Its
Time for a New Verication
Debug Data API. Learn
more at #52DAC
Verication Academy Booth
2408 June 9th 5pm. http:
2 days ago

RT @DoulosLtd: Next
Doulos training webinar:
#SystemVerilog Synthesis
for @XilinxInc FPGAs.
Register now for free!
http://t.co/of0dmdIvcI
9 days ago

Dave Rich

Follow @dave_59

@jhupcey Tweets
RT @mentor_graphics:
The Mixels are making their
way to San Francisco for
#52DAC! Get yours
Monday-Wednesday at
Mentor booth 1432
http://t.
2 days ago

"Yikes - #52DAC is Monday


and I haven't asked my
boss for time o!" NP - use
the Justication Toolkit now
http://t.co/J1YeeIz0Qa
#SemiEDA

2 days ago

@mentor_graphics' Mark
Eslinger putting the
nishing touches on his
#52DAC Verication
Academy presentation next
wk
http://t.co/OBvaDthmw6
4 days ago

#52DAC is in 2 weeks &U


haven't spoken to UR boss
yet? NP: use the cover
letter &points in the
Justication
Toolkit:https://t.co/8z0y7FQHCs
10 days ago
Follow @jhupcey

Links
ARM SoC Design
Gabe on EDA
OVM Forum
SystemVerilog Forum
The Standards Game
UVM Forum
Verication Guild

MORE BLOG POSTS

The reports of OVMs death are greatly exaggerated (with

Redening Verication Performance (Part 1)

apologies to Mark Twain)

COMMENTS

21 comments on this post | Add Your Own


Commented on July 13, 2010 at 11:11 pm
By Greg Jaxon

Excellent illustration, Dave!


What you say about classes also applies to most structs, unions, and enums, too.
One situation to watch is `includes into the $unit scope (outside any module or other part description).
Whether the same include le brought into the $unit scope of distinct les can create matching types is a
delicate matter; users probably should not expect SV implementations to agree on every case of this.
Good thing packages are so easy to use to get this right!

Commented on July 17, 2010 at 11:34 am


By Vishnu

Excelent Article Dave

Commented on February 8, 2011 at 6:57 am


By Pranav Joshi

This is an excellent piece of explanation. I must use this to train engineers of my team.

Commented on June 28, 2011 at 5:07 pm


By geonerstiem

thanks

Commented on July 7, 2011 at 1:40 am


By MBS

good article, thanks or sharing, Dave.

Commented on September 9, 2011 at 12:00 pm


By Mark Curry

In the nal solution why bother using the include at all? The les not included anywhere else just put
the denition in the P package and be done with it.

Commented on September 9, 2011 at 1:02 pm


By Dave Rich

Hi Mark,
When you package starts having class A, B, C, etc. you need separate les for better revision control.
Then `include shows the required le dependencies and compilation order.

Commented on April 16, 2012 at 3:42 pm


By omer

Hello Dave,
Thank you very much for progressive explanation. I have been trying to understand the dierence
between the two a while now as I am new to OOP.
Take care

Commented on September 12, 2012 at 10:01 am


By Dave Rich

You can certainly use extern to separate class declarations from method declarations, but the methods
must be dened before closing the scope. So everything has to be inside the package.
For example
package p;
`include myclass_declarations.svh
`include myclass_methods.svh
endpackage

Commented on July 3, 2013 at 9:57 pm


By MBC

Hi Dave,

can you give an example of how P::A is type incompatible with Q::A (when you are showing the eects of
`include).
It would be nice if you can show a snippet of code that demonstrates the type incompatibility issue
between the two variables.

Commented on July 8, 2013 at 7:15 am


By Dave Rich

Shaun,
The code shown in the example showing the eects of `include behaves exactly as the previous example
where package P and Q are dened without `include. So if you had
P::A handle_a1;
Q::A handle_a2;
handle_a1 = new();
handle_a2=handle_a1; // this is illegal

Commented on September 16, 2013 at 2:40 pm


By Linh Nguyen

Very clear, thank you!

Commented on January 21, 2014 at 6:24 am


By Surya

HI Dave,
Thats a great explanation. Here is some issue I am facing with my compiler (vcs):
package test_lib_pkg;
import uvm_pkg::*;
`include uvm_macros.svh
import bus_agent_pkg::*;
import bus_seq_lib_pkg::*;
`include bus_test_base.sv
endpackage
My compiler give me an error saying, le could not be found when this included le is not in the same dir
as my Makele is, or else if both are in the same dir it comiples without error. Now how do I tell my
compiler to look into the same dir where my pakage les are ?

Commented on January 21, 2014 at 8:17 am


By Dave Rich

This is a tool issue, not a language issue. Please contact your vendor for support.

Commented on April 24, 2014 at 10:18 am


By Soha Sayed

Thank you DAVE .. you are a life saver

.. CHAPEAU!

Commented on May 27, 2014 at 12:18 am


By mukesh

Hi Dave,
Thanx for ur wonderful explanation .

Commented on August 26, 2014 at 9:04 am


By Cadence stops support for importing packages in class ? | eecad

[] http://blogs.mentor.com/vericationhorizons/blog/2010/07/13/package-import-versus-include/ []

Commented on September 20, 2014 at 8:23 am


By Christopher

Thanks for nally talking about > SystemVerilog Coding


Guidelines: Package import versus `include

Commented on March 10, 2015 at 7:46 pm


By SystemVerilog Coding Guidelines: Package import versus `include Verication Horizons BLOG ASIC Craftsman (
)

[] SystemVerilog Coding Guidelines: Package import versus `include Verication Horizons BLOG. []

Commented on March 13, 2015 at 12:59 am


By Yogaraj

Hi Dave,
Can you explain me the relationship between comparison scope and comparison unit with respect to
import package and include

Commented on March 16, 2015 at 9:55 am


By Dave Rich

Hi Yogaraj,
I assume you meant compilation not comparison. If so, please read http://go.mentor.com/unit-vs-root
and let me know if you have more questions. And remember, `include is just a text processor that knows
nothing about the text it is including.

Add Your Comment


Name (required)
Mail (will not be publis hed) (required)

Submit Comment

Recent Posts

Archives

Tags

Its Time for a New Verication Debug Data

June 2015

Standards

API (DDA)
Accellera Portable Stimulus Working Group
Accepting Technology Contributions
Part 6: The 2014 Wilson Research Group
Functional Verication Study
An Agile Evolution in SoC Verication Panel
@ DAC
UVM Debug. A contest using class based
testbench debug
No to Know VIP
Part 5: The 2014 Wilson Research Group
Functional Verication Study

Its Time for a New Verication Debug Data


API (DDA)

Accellera Portable Stimulus Working Group


Accepting Technology Contributions

Part 6: The 2014 Wilson Research Group


Functional Verication Study

An Agile Evolution in SoC Verication Panel


@ DAC

SystemVerilog
UVM
Accellera
functional verication
Verication
Verication Academy

May 2015

OVM

UVM Debug. A contest using class based


testbench debug

IEEE

No to Know VIP

ASYNC 2015: The Most Important CDC


Conference Youve Never Heard Of

Part 5: The 2014 Wilson Research Group


Functional Verication Study

Verication Academy: The Place to Meet at


DAC

ASYNC 2015: The Most Important CDC


Conference Youve Never Heard Of

Part 4: The 2014 Wilson Research Group


Functional Verication Study

Verication Academy: The Place to Meet


at DAC

April 2015
Part 4: The 2014 Wilson Research Group
Functional Verication Study
DVCon, Reuse, and Software-Driven
Verication
Do Formal Apps Help D&V Engineers
Cross the Chasm Into Direct Formal
Property Checking? This Oracle Case Study
Suggests They Do (Part 2 of 2)
Do Formal Apps Help D&V Engineers
Cross the Chasm Into Direct Formal
Property Checking? This Oracle Case Study
Suggests They Do (Part 1 of 2)
20 Years Ago 10 Years Ago Tomorrow
(DAC)
Part 3: The 2014 Wilson Research Group
Functional Verication Study

March 2015
March 2015 Edition of Verication
Horizons Available Online!
Part 2: The 2014 Wilson Research Group
Functional Verication Study

February 2015
Is Gate-Level Simulation Still Required
Nowadays??
From Tightly Coupled (Loosely Bolted) to
Verication Convergence!
Portable Stimulus at DVCon
Portable Stimulus: A Small Step in
Standardization
Part 1: The 2014 Wilson Research Group
Functional Verication Study

January 2015
Understanding and Minimizing Study Bias
Prologue: The 2014 Wilson Research
Group Functional Verication Study
Who Knew VIP?
3 Notable Formal-Related Conference
Papers of 2014

December 2014
Latest Issue of Verication Horizons
Available!

November 2014
SystemVerilog Testbench Debug Are we
having fun yet?
ARM Techcon Paper Report: How
Microsoft Saved 4 Man-Months Meeting
Their Coverage Closure Goals Using
Automated Verication Management &
Formal Apps
Preparing for the Perfect Storm with
New-School Verication Techniques

Simulation
MORE

On-Demand Webinar: UVM Sequences in


Depth

October 2014
DVCon India: A Smashing Hit!

September 2014
Portable and Productive Test Creation
with Graph-Based Stimulus
Supporting A Season of Learning

August 2014
DVCon Goes Global!
Better Late Than Never: Magical
Verication Horizons DAC Edition

July 2014
Accellera Approves UVM 1.2

May 2014
Getting More Value from your Stimulus
Constraints
The FPGA Verication Window Is Open

April 2014
UVM DVCon 2014 Tutorial Video Online
Mentor Enterprise Verication Platform
Debuts

March 2014
New Verication Academy ABV Course
DVCon 2014 Issue of Verication
Horizons Now Available

February 2014
DVConThe FREE Side
More DVConMore Mentor Tutorials!
UVM 1.2: Open Public Review
DVCon 2014: Standards on Display
Just because FPGAs are programmable
doesnt mean verication is dead

January 2014
Managing Verication Coverage
Information

November 2013
Epilogue: The 2012 Wilson Research
Group Functional Verication Study
New Verication Horizons Issue Available

October 2013
Happy Halloween from ARM TechCon
IEEE Standards Association Symposium
on EDA Interoperability
STMicroelectronics: Simulation +
Emulation = Verication Success

September 2013
A Decade of SystemVerilog: Unifying
Design and Verication?
Part 12: The 2012 Wilson Research Group
Functional Verication Study

August 2013
Part 11: The 2012 Wilson Research Group
Functional Verication Study
Part 10: The 2012 Wilson Research Group
Functional Verication Study
Part 9: The 2012 Wilson Research Group
Functional Verication Study
Part 8: The 2012 Wilson Research Group
Functional Verication Study

July 2013
Part 7: The 2012 Wilson Research Group
Functional Verication Study
Walking in the Desert or Drinking from a
Fire Hose?

Part 6: The 2012 Wilson Research Group


Functional Verication Study
A Short Class on SystemVerilog Classes
Part 5: The 2012 Wilson Research Group
Functional Verication Study
Part 4: The 2012 Wilson Research Group
Functional Verication Study

June 2013
Part 3: The 2012 Wilson Research Group
Functional Verication Study
Part 2: The 2012 Wilson Research Group
Functional Verication Study

May 2013
Texas-Sized DAC Edition of Verication
Horizons Now Up on Verication Academy
IEEE 1801-2013 UPF Standard Is
Published
Part 1: The 2012 Wilson Research Group
Functional Verication Study
Whats the deal with those wires and
regs in Verilog

April 2013
Getting AMPed Up on the IEEE LowPower Standard
Prologue: The 2012 Wilson Research
Group Functional Verication Study

March 2013
Even More UVM Debug in Questa 10.2
IEEE Approves New Low Power Standard

February 2013
Verication Horizons DVCon Issue Now
Available
Get your IEEE 1800-2012 SystemVerilog
LRM at no charge
IEEE 1800-2012 SystemVerilog Standard
Is Published
See You at DVCon 2013!
Get Ready for SystemVerilog 2012

January 2013
VHDL Update Comes to Verication
Academy!

December 2012
IEEE Approves Revised SystemVerilog
Standard

November 2012
Coverage Cookbook Debuts

October 2012
IoT: Internet of Things
Check out the October, 2012 Verication
Horizons
Improving simulation results with formalbased technology
Introducing Verication Academy 2.0

September 2012
OVM Gets Connected

August 2012
OpenStand & EDA Standardization

July 2012
Synthesizing Hardware Assertions and
Post-Silicon Debug
Virtual Emulation for Debugging
Verication Academy: Up Close &
Personal
SystemC Standardization Cycle
Completes

Verication Standards Take Another Step


Forward
New UVM Recipe of the Month:
Scoreboarding in UVM

June 2012
Intelligent Testbench Automation
Catching on Fast

May 2012
Two Articles You Need to Check Out
O to DAC!
Dave Rich Featured on EEWeb

March 2012
How Did I Get Here?

February 2012
Expanding the Verication Academy!
Get on the Fast Track to Advanced
Verication with UVM Express
Introducing UVM Connect
Tornado Alert!!!
UVM: Some Thoughts Before DVCon
UVM at DVCon 2012

January 2012
SystemC 2011 Standard Published
Verication solutions that help reduce
bug cost

December 2011
Instant Replay for Debugging SoC Level
Simulations
2011 IEEE Design Automation Standards
Awards

November 2011
Getting started with the UVM Using the
Register Modeling package
TLM Becomes an IEEE Standard

October 2011
Worlds Standards Day 2011
VHS or Betamax?
Verication Issues Take Center Stage

September 2011
New UVM Recipe-of-the-Month: Sequence
Layering

July 2011
Combining Intelligent Testbench
Automation with Constrained Random
Testing
Going from Standards Development to
Standards Practice
Verication Academy Now Includes
OVMWorld Content

June 2011
Intelligent Testbench Automation
Delivers 10X to 100X Faster Functional
Verication
Part 9: The 2010 Wilson Research Group
Functional Verication Study
Verication Horizons DAC Issue Now
Available Online
Accellera & OSCI Unite
The IEEEs Most Popular EDA Standards
UVM Register Kit Available for OVM 2.1.2

May 2011
Part 8: The 2010 Wilson Research Group
Functional Verication Study
Getting Your Standards Update @ DAC

2011

April 2011
User-2-Users Functional Verication
Track
Part 7: The 2010 Wilson Research Group
Functional Verication Study
Part 6: The 2010 Wilson Research Group
Functional Verication Study
SystemC Day 2011 Videos Available Now
Part 5: The 2010 Wilson Research Group
Functional Verication Study
Part 4: The 2010 Wilson Research Group
Functional Verication Study
Part 3: The 2010 Wilson Research Group
Functional Verication Study

March 2011
Part 2: The 2010 Wilson Research Group
Functional Verication Study
Part 1: The 2010 Wilson Research Group
Functional Verication Study
Prologue: The 2010 Wilson Research
Group Functional Verication Study
Language Transitions: The Dawning of
Age of Aquarius
Using the UVM libraries with Questa

February 2011
DVCon: The Present and the Future
Free at Last! UVM1.0 is Here!
Parameterized Classes, Static Members
and the Factory Macros
IEEE Standards in India

January 2011
Accellera Approves New Co-Emulation
Standard

December 2010
New Verication Horizons: Methodologies
Dont Have to be Scary
The Survey Says: Verication Planning

October 2010
Towards UVM Register Package
Interoperability
IECs 47th General Assembly Meeting
Opens
UVM: Giving Users What They Want

September 2010
UVM Takes Shape in the Accellera VIPTSC
Accellera VIP-TSC Selects RAL for UVM
1.0 Register Package
OVM Cookbook Available from
OVMWorld.org
UVM Register Package Candidate News

August 2010
Redening Verication Performance (Part
2)

July 2010
Making formal property checking easy to
use
Redening Verication Performance (Part
1)
SystemVerilog Coding Guidelines:
Package import versus `include

June 2010
The reports of OVMs death are greatly
exaggerated (with apologies to Mark
Twain)
New Verication Academy Advanced OVM

(&UVM) Module
OVM/UVM @DAC: The Dog That Didnt
Bark
DAC: Day 1; An Ode to an Old Friend
UVM: Joint Statement Issued by Mentor,
Cadence & Synopsys
Static Verication
OVM/UVM at DAC 2010
DAC Panel: Bridging Pre-Silicon
Verication and Post-Silicon Validation
Accelleras DAC Breakfast & Panel
Discussion

May 2010
Easier UVM Testbench Construction
UVM Sequence Layering
North American SystemC User Group
(NASCUG) Meeting at DAC
An Extension to UVM: The UVM Container
UVM Register Package 2.0 Available for
Download
Accelleras OVM: Omnimodus Verication
Methodology
High-Level Design Validation and Test
(HLDVT) 2010
New OVM Sequence Layering Package
For Easier Tests
OVM 2.0 Register Package Released
OVM Extensions for Testbench Reuse

April 2010
SystemC Day Videos from DVCon
Available Now
On Committees and Motivations
The Final Signatures (the meeting during
the meeting)
UVM Adoption: Go Native-UVM or use
OVM Compatibility Kit?
UVM-EA (Early Adopter) Starter Kit
Available for Download
Accellera Adopts OVM 2.1.1 for its
Universal Verication Methodology (UVM)

March 2010
The Art of Deprecation
OVM 2.1.1 Now Ready for Download
February 2010 Verication Horizons
Newsletter Now Available
IEEE Standards Meetings in India

February 2010
I Do It
SystemVerilog: A time for change? Maybe
not.
Partners Oer Support for OVM 1.0
Register Package
SystemC Day at DVCon
OVM/VMM Interoperability Kit: Its Ready!

January 2010
Three Perfect 10s
OVM 1.0 Register Package Released
Accellera Adopts OVM
SystemC (IEEE Std. 1666) Comes to
YouTube
Debugging requires a multifaceted
solution

December 2009

A Clihanger ABV Seminar, Jan 19, Santa


Clara, CA
Truth in Labeling: VMM2.0
IEEE Std. 1800-2009 (SystemVerilog)
Ready for Purchase & Download
December Verication Horizons Issue Out
Evolution is a tinkerer
It Is Better to Give than It Is to Receive
Zombie Alert! (Can the CEDA DTC User
Voice Be Heard When They Wont Let You
Listen)
DVCon is Just Around the Corner
The Standards Corner Becomes a Blog
I Am Honored to Honor
IEEE Standards Association Awards
Ceremony
ABV and being from Missouri
Time hogs, blogs, and evolving
underdogs
Full House and this is no gamble!
Welcome to the Verication Horizons
Blog!

September 2009
SystemVerilog: The ner details of $unit
versus $root.
SystemVerilog Coding Guidelines

July 2009
The Language versus The Methodology

May 2009
Are Program Blocks Necessary?