Diff Between Pakage and Include

VERIFICATION HORIZ ONS BLOG
SystemVerilog Coding Guidelines: Package import versus

ìnclude
Another frequently asked question: Should I import my classes from
a package or ìnclude them? To answer this properly, you need to
know more about SystemVerilogs type system, especially the
dierence between its strong and weak typing systems.
In programming languages, weak typing is characterized by implicit or ad-hoc
conversions without explicit casting between values of dierent data types.
Verilogs bit vectors, or integral types, represent these weak typing aspects by
implicitly padding and truncating values to be the proper bit lengths at least
proper by Verilog standards. If you perform a bitwise AND of a 7-bit and 8-bit
vector, Verilog implicitly zero pads an 8th bit to the 7-bit operand and returns an
8-bit result. In contrast using VHDL, you would have to explicitly state whether
you wanted the 7-bit operand to be padded, or the 8-bit operand to be truncated
so that you have an expression with operands of equal size.
With a few exceptions, all other types in SystemVerilog follow strong typing
rules. Strong typing rules require explicit conversions or casts when assigning or
expressing operands of unequal types. And understanding what SystemVerilog
considers equivalent types is key to understanding the eect of importing a class
from a package versus including it from a le.
Inheritance aside, SystemVerilog uses the name of a type alone to determine type
equivalence of a class. For example, suppose I have these two class denitions A
and B below:
class A;
int i;
endclass : A
class B;
int i;
endclass : B
SystemVerilog considers these two class denitions unequal types because they
have dierent names, even though their contents, or class bodies, are identical.
The name of a class includes more than just the simple names A and B; the
names also include the scope where the denition is declared. When you declare
a class in a package, the package name becomes a prex to the class name:
POST AUTHOR
Pos ted July 13th, 2010, by

Dave Rich
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package P;
class A;
int i;
endclass : A
A a1;
endpackage : P
package Q;
class A;
int i;
endclass : A
A a1;
endpackage : Q
Now there are two denitions of class A, one called P::A and the other called
Q::A. And the variables P::a1 and Q::a1 are type incompatible referencing two
dierent class As. Re-writing the above example using an include le creates the
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same situation two incompatible class denitions.

File A.sv
File P.sv
class A;
int i;
endclass : A
File Q.sv
package P;
ìnclude A.sv"
A a1;
endpackage : P
package Q;
ìnclude A.sv"
A a1;
endpackage : Q
After ìncluding class A into each package, you wind up with two denitions of
class A. Using ìnclude is just a shortcut for cut and pasting text in a le.
Importing a name from a package does not duplicate text; it makes that name
visible from another package without copying the denition.
File A.sv
class A;
int i;
endclass : A
File P.sv
package P;
ìnclude A.sv"
endpackage : P
File R.sv
package R;
import P::A;
A a1;
endpackage : R
File S.sv
package S;
import P::A;
A a1;
endpackage : S
Class A is declared in package P, and only in package P. The variables R::a1 and
S::a1 are type compatible because they are both of type P::A. The fact that class
A was ìncluded from another le once it is expanded is no longer relevant once
you consider the placement of the text from the le.
When you get compiler errors claiming that two types are incompatible even
though they appear to have the same name, make sure you consider the scope
where the types are declared as part of the full name. Class names declared in a
module are prexed by the module instance name, so the same module
instantiated multiple times will create unique class names, all incompatible types.
For further information about packages, check out the June Verication
Horizons article entitled Using SystemVerilog Packages in Real Verication
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COMMENTS
21 comments on this post | Add Your Own

Commented on July 13, 2010 at 11:11 pm
By Greg Jaxon
Excellent illustration, Dave!

What you say about classes also applies to most structs, unions, and enums, too.
One situation to watch is ìncludes into the $unit scope (outside any module or other part description).
Whether the same include le brought into the $unit scope of distinct les can create matching types is a
delicate matter; users probably should not expect SV implementations to agree on every case of this.
Good thing packages are so easy to use to get this right!
Commented on July 17, 2010 at 11:34 am

By Vishnu
Excelent Article Dave
Commented on February 8, 2011 at 6:57 am

By Pranav Joshi
This is an excellent piece of explanation. I must use this to train engineers of my team.
Commented on June 28, 2011 at 5:07 pm

By geonerstiem
thanks

By MBS
good article, thanks or sharing, Dave.
Commented on September 9, 2011 at 12:00 pm

By Mark Curry
In the nal solution why bother using the include at all? The les not included anywhere else just put
the denition in the P package and be done with it.

By Dave Rich
Hi Mark,
When you package starts having class A, B, C, etc. you need separate les for better revision control.
Then ìnclude shows the required le dependencies and compilation order.
Commented on April 16, 2012 at 3:42 pm

By omer
Hello Dave,
Thank you very much for progressive explanation. I have been trying to understand the dierence
between the two a while now as I am new to OOP.
Take care
Commented on September 12, 2012 at 10:01 am

By Dave Rich
You can certainly use extern to separate class declarations from method declarations, but the methods
must be dened before closing the scope. So everything has to be inside the package.
For example
package p;
ìnclude myclass_declarations.svh
ìnclude myclass_methods.svh
endpackage
Commented on July 3, 2013 at 9:57 pm

By MBC
Hi Dave,
can you give an example of how P::A is type incompatible with Q::A (when you are showing the eects of
ìnclude).
It would be nice if you can show a snippet of code that demonstrates the type incompatibility issue
between the two variables.

By Dave Rich
Shaun,
The code shown in the example showing the eects of ìnclude behaves exactly as the previous example
where package P and Q are dened without ìnclude. So if you had
P::A handle_a1;
Q::A handle_a2;
handle_a1 = new();
handle_a2=handle_a1; // this is illegal

By Linh Nguyen
Very clear, thank you!
Commented on January 21, 2014 at 6:24 am

By Surya
HI Dave,
Thats a great explanation. Here is some issue I am facing with my compiler (vcs):
package test_lib_pkg;
import uvm_pkg::*;
ìnclude uvm_macros.svh
import bus_agent_pkg::*;
import bus_seq_lib_pkg::*;
ìnclude bus_test_base.sv
endpackage
My compiler give me an error saying, le could not be found when this included le is not in the same dir
as my Makele is, or else if both are in the same dir it comiples without error. Now how do I tell my
compiler to look into the same dir where my pakage les are ?
Commented on January 21, 2014 at 8:17 am

By Dave Rich
This is a tool issue, not a language issue. Please contact your vendor for support.
Commented on April 24, 2014 at 10:18 am

By Soha Sayed
Thank you DAVE .. you are a life saver
.. CHAPEAU!
Commented on May 27, 2014 at 12:18 am

By mukesh
Hi Dave,
Thanx for ur wonderful explanation .
Commented on August 26, 2014 at 9:04 am

By Cadence stops support for importing packages in class ? | eecad
[] http://blogs.mentor.com/vericationhorizons/blog/2010/07/13/package-import-versus-include/ []
Commented on September 20, 2014 at 8:23 am

By Christopher
Thanks for nally talking about > SystemVerilog Coding

Guidelines: Package import versus ìnclude
Commented on March 10, 2015 at 7:46 pm

By SystemVerilog Coding Guidelines: Package import versus ìnclude Verication Horizons BLOG ASIC Craftsman (
)
[] SystemVerilog Coding Guidelines: Package import versus ìnclude Verication Horizons BLOG. []
Commented on March 13, 2015 at 12:59 am

By Yogaraj
Hi Dave,
Can you explain me the relationship between comparison scope and comparison unit with respect to
import package and include
Commented on March 16, 2015 at 9:55 am

By Dave Rich
Hi Yogaraj,
I assume you meant compilation not comparison. If so, please read http://go.mentor.com/unit-vs-root
and let me know if you have more questions. And remember, ìnclude is just a text processor that knows
nothing about the text it is including.
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VERIFICATION HORIZ ONS BLOG

SystemVerilog Coding Guidelines: Package import versus

Pos ted July 13th, 2010, by

IEEE 1800, S, Sys temVerilog,

This blog will provide an

After 37 years, we have

same situation two incompatible class denitions.

RT @Gizmodo: The world's

Stop by and say hi

"Yikes - #52DAC is Monday

#52DAC is in 2 weeks &U

MORE BLOG POSTS

The reports of OVMs death are greatly exaggerated (with

Redening Verication Performance (Part 1)

apologies to Mark Twain)

21 comments on this post | Add Your Own

Excellent illustration, Dave!

Commented on July 17, 2010 at 11:34 am

Excelent Article Dave

Commented on February 8, 2011 at 6:57 am

Commented on June 28, 2011 at 5:07 pm

Commented on July 7, 2011 at 1:40 am

good article, thanks or sharing, Dave.

Commented on September 9, 2011 at 12:00 pm

Commented on September 9, 2011 at 1:02 pm

Commented on April 16, 2012 at 3:42 pm

Commented on September 12, 2012 at 10:01 am

Commented on July 3, 2013 at 9:57 pm

Commented on July 8, 2013 at 7:15 am

Commented on September 16, 2013 at 2:40 pm

Very clear, thank you!

Commented on January 21, 2014 at 6:24 am

Commented on January 21, 2014 at 8:17 am

Commented on April 24, 2014 at 10:18 am

Thank you DAVE .. you are a life saver

Commented on May 27, 2014 at 12:18 am

Commented on August 26, 2014 at 9:04 am

Commented on September 20, 2014 at 8:23 am

Thanks for nally talking about > SystemVerilog Coding

Commented on March 10, 2015 at 7:46 pm

Commented on March 13, 2015 at 12:59 am

Commented on March 16, 2015 at 9:55 am

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