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VHDL Testbench Tutorial

Table Of Contents
VHDL Testbench Tutorial ................................................................................................................ 1
Introduction .................................................................................................................................. 1
Creating New Design ................................................................................................................... 1
Generating Test Bench ................................................................................................................ 3
Running TestBench Macro .......................................................................................................... 6
Timing Simulation ........................................................................................................................ 7
Adjusting Test Vector File ............................................................................................................ 8

VHDL Testbench Tutorial


Introduction
The purpose of this advanced testbench tutorial is to acquaint you with methods of automatic
generation of WAVES-based testbenches. The basic testbench tutorial, which you are assumed
to have already gone through, deals with the single process testbenches. A single process
testbench can only drive input ports of the UUT entity while the WAVES-based testbench
simultaneously drives the inputs and compares the output response with a previously saved
pattern. Test vectors used to stimulate the UUT entity are furnished in an external file (*.VEC)
based on a text format specified by the WAVES standard. Additional procedures compare output
signals of the UUT entity with the pattern vectors. Discrepancies are reported in a log file. The
Test Bench Wizard generates the test vector file (*.VEC) from a waveform file (*.AWF) created
with Waveform Editor. It also verifies if port names of the UUT entity agree with the signal names
saved in the waveform file.
Once the user has generated a testbench and prepared specification of test vectors, the
testbench can be used many times to perform automatic verification of successive revisions of a
VHDL design. Moreover, the same testbench can be used with different test vector files, provided
that they define timings of the same signals. The wizard is not the only tool that generates test
vector files in the WAVES format. Active-HDL provides the Export Waveform command that can
be used to convert waveform files (*.AWF) to WAVES format test vector files(*.VEC).

Creating New Design


In the tutorial, you will create a simple design. To save time, you will reuse VHDL code from the
Loadable_counter sample design, shipped with Active-HDL.
1. Start Active-HDL. If the Getting Started dialog opens, click Cancel.
2. Choose New | Design from the File menu. The New Design Wizard will open.
3. In the first wizard dialog, select the Add existing resource files option, and then click Next.
You will use an existing VHDL source file from the Loadable_counter sample design.

VHDL Testbench Tutorial


4. In the next wizard dialog, click the Add files button to open the Add Files to Design dialog
box.

5. In the Add Files to Design dialog box, select the counter.vhd source file from the src folder of
the Loadable_counter sample design folder.

6. Select the Make local copy check box, and then click Add to copy the counter.vhd file to your
design directory. Then click Next to display the last wizard dialog.
7. Specify desired synthesis and implementation tools for the current design (if there are any
installed). Choose the default family, block diagram configuration and default HDL language.
Click the Next button.
8. Enter L_counter as the design name, and then click Next.

VHDL Testbench Tutorial

9. The next wizard dialog shows a summarized design specification so that you can view it before
the design will be created.
Select the Compile source files after creation check box, and then click Finish.
The design will be created and the counter.vhd file will be compiled.
Choose the counter as a top-level.

After this operation, the Design Browser window should look as shown below:

Generating Test Bench


Usually, the user performs the functional simulation and defines test vectors required to verify
operation of the design before generating a testbench. To save time, in this tutorial you will use
the waveform file saved in the sample Loadable_counter design to generate the testbench, and
then perform the functional simulation using the testbench macro.

VHDL Testbench Tutorial


1. Select the Add files to design option from the Design menu.
2. In the Add Files to Design dialog box, select All files from the Files of type list box, then
select the Functional.awf waveform file from the src folder of the Loadable_counter design, and
then click Add.
3. In the Design Browser click the

icon to the left of the counter.vhd icon.

4. Click the counter(counter_behav) design entity with the right mouse button, and then choose
Generate Test Bench from the shortcut menu to start the Test Bench Wizard.

5. The first Test Bench Wizard dialog will appear in which you have to choose the desired
testbench type.

6. Select the WAVES Based option, and then click Next.


7. Select the Test vectors from file check box, to make the wizard use the previously saved
waveform file to generate the testbench stimuli. Next, click the Browse button to display available
waveform files. Select the Functional.awf waveform file in the Open dialog, and then click Open.

VHDL Testbench Tutorial

The Signals found in file box will display input ports found in the specified waveform file, and the
UUT ports box will display the input ports of the COUNTER entity. Note, that the COUNTER
entity is the UUT entity. Click Next.
8. The next wizard dialog allows you to specify the names of the testbench entity, architecture
and VHDL source file. The wizard automatically suggests default names. Click Next to accept
them and go to the next wizard dialog.

9. The last dialog displays the paths of the files that will be generated by the wizard.
They are:

the testbench source files


a simulation macro file which automatically compiles the testbench files, inserts the UUT
ports into the Waveform Editor window and runs simulation of the testbench

VHDL Testbench Tutorial

an additional source file containing a configuration declaration for timing simulation


(generated optionally)

10. Select the Generate check box to generate the optional configuration file, and then click
Finish.
11. The wizard will generate the testbench files and attach them to the design in a special file
folder, WAVES. Note, that Design Browser uses a special icon for testbench source files to
distinguish them from regular sources. The Counter_TB.vhd file will open in the HDL Editor
window. View the source code to see how the testbench has been constructed by the wizard.
12. In addition to the files created by the wizard, the WAVES folder also contains external
auxiliary files that have been attached to the design. The external files are represented in Design
icon.
Browser by the
13. Click the icon to the left of the WAVES folder on the Files tab of the Design Browser. The
WAVES folder contents is as shown in the figure below:

Running TestBench Macro


In the previous paragraph you have generated the WAVES-based testbench for your design.
Now, you can run the testbench macro to view the results of functional simulation of the design.
Note, that the generated waveform will contain not only the actual result timings of your design
but also the expected timings ( the output Q port is represented by the ACTUAL_Q signal, whose
value is compared with the expected Q port value, represented by the EXPECT_Q signal). The
waveform will also contain the ERR_STATUS additional signal, whose value of 'L' indicates that
no discrepancies have been detected between expected and actual timings.
The testbench macro will perform the following operations:

compiles the UUT design files


compiles the WAVES testbench necessary files
initializes simulation
adds ports of the design to the Waveform Editor window
runs simulation, comparing the actual results with the expected result values

All you have to do to run the test of the design is execute the macro and view the simulation
results. If the ERR_STATUS signal value equals 'L' then the results are the same as expected. If,
at any time value the discrepancy has been detected, then the ERR_STATUS signal value will
equal 'H'. The details of the detected discrepancies are logged to the counter_report.log file.
1. Select the Counter_TB_runtest.do macro on the Files tab of the Design Browser window.
2. Click the right mouse button and choose Execute from the shortcut menu.
3. Wait until the shown below message box appears, then click OK.

You should obtain waveforms as shown in the figure below.

VHDL Testbench Tutorial

4. End simulation by choosing End Simulation from the Simulation menu.

Timing Simulation
The final stage of the design development process is the verification of the design behavior after
its implementation. The Place & Route implementation tools produce structural VHDL code. Such
code is usually supplied with SDF file with timing information. So obtained source file can be
verified with the same testbench that has been used for functional simulation. In this tutorial, you
will not have to run implementation software by yourself. Instead, you will use implementation
files from the original sample design Loadable_counter, suitably modifying the testbench macro
for the needs of timing simulation.
1. Select Add Files to Design from the Design menu. In the Add Files to Design dialog select
the src folder located in the Loadable_counter folder, and then select the following two files:

counter_tim.vhd - the backannotated post place-and-route VHDL structural code


counter_tim.sdf - SDF (standard delay format) timing file

Make sure that the Make local copy check box is selected, then click Add.
2. Switch to the Files tab of Design Browser.
Now you will have to edit the counter_TB_tim_cfg.vhd configuration and the
counter_TB_runtest.do macro so that they can be used for timing simulation.
3. Double-click the counter_TB_tim_cfg.vhd file on the Files tab. The file will open in the HDL
Editor. Uncomment the line:
use entity work.ENTITY_NAME (ARCH_NAME);
Replace the ENTITY_NAME and ARCH_NAME with the entity and architecture names from the
backannotated VHDL file. The line should read as follows:
use entity work.COUNTER (STRUCTURE);
Save the timing configuration file by clicking the

toolbar button.

4. Double-click the counter_TB_runtest.do macro on the Files tab. The file will open in the HDL
Editor. Do the editing as follows:
a) In the #Compiling UUT entity design files section, replace the line
comp $DSN\src\counter.vhd
with the line:
comp "$DSN\src\counter_tim.vhd"
b) In the #Compiling timing configuration section, uncomment the line
acom -work L_counter "$DSN\src\WAVES\counter_TB_tim_cfg.vhd"
c) In the #Run simulation section replace the line
asim TESTBENCH_FOR_counter

VHDL Testbench Tutorial


with the line:
asim TIMING_FOR_counter -sdftyp /UUT=$DSN\SRC\counter_tim.sdf
5. Save the counter_TB_runtest.do file. Now, the macro is ready for execution. The macro will
compile the implementation source files, initialize simulation and run the testbench.
6. Select the macro label on the Files tab of the Design Browser window. Click the right mouse
button, and then choose Execute from the shortcut menu.
Wait until the shown below message box appears, then click OK.

7. View the results of timing simulation in the Waveform Editor window and compare them with
the results of the functional simulation.
As the frequency of 125 MHz has been chosen for the CLK input signal, which is too high for the
real synchronous counter implementation, the output ACTUAL_Q signal value does not change
as expected. Note, that the ERR_STATUS signal value is 1, indicating discrepancies between
EXPECT_Q and ACTUAL_Q signals. View the log file to see how discrepancies are represented
in it.

To do so, switch to the Resource tab of Design Browser, click the icon to the left of the Logs
folder, and then double-click the src\WAVES\counter_report.log label.

Adjusting Test Vector File


In this paragraph you will edit waveforms so that the timing simulation could be successfully
performed. The first thing you have to do is scaling the waveforms to obtain the 12.5 MHz
frequency of the input CLK signal, which should be acceptable by the design implementation. You
will use another Active-HDL feature, the Stretch command, that is available from the shortcut
menu after selecting the waveform area to be scaled.
1. Select End Simulation from the Simulation menu.
2. Open the original Functional.awf waveform file, that has been used for testbench generation.
3. Select the whole waveform area:
a) In Waveform Editor, switch to the Edit mode by clicking the

toolbar button.

b) Rest the mouse pointer over the origin of the waveform area to be selected. Press and hold the
mouse button. The mouse pointer will adopt a new shape:
. If the mouse pointer tends to
switch to the event-dragging mode, hold the Ctrl key.
c) Move the mouse so as to select the desired area. The selection should contain all waveforms.
The tooltip will show the time range of the current selection.

VHDL Testbench Tutorial


d) Release the mouse button.
4. Click the right mouse button, then select the Stretch command from the shortcut menu. This
will open the dialog shown below:

5. In the Scale box enter 1000%, and then click OK. This will change the CLK frequency to 12.5
MHz.
6. Save the waveform file, clicking the

button.

7. Choose Waveform from the File/Export menu. The following dialog will open:

8. Select the Waves vectors (*.VEC) from the Save as type box, select the Functional.vec file
from the \\src\WAVES folder, and then click Save. Click Yes when asked if you want to replace
an existing file.
Select the L_counter design library on the Files tab of the Design Browser, click the right mouse
button, and then choose Delete simulation data from the shortcut menu.
Note, that the asim TIMING_FOR_counter -sdftyp /UUT=$DSN\SRC\counter_tim.sdf command
instructs the simulator to apply the time delays from the counter_tim.sdf file. This will result in
certain delays of the output signal relative to the falling edge of the clock signal. The WAVESbased testbench declares the window frames, in which it will compare the actual signal values
with the expected signal values during simulation. For the purpose of the functional simulation the
default WND_BEGIN_DEFAULT and WND_END_DEFAULT window parameters have been
used. The appropriate declarations can be found in the counter_TB_declaration.vhd file:
constant WND_BEGIN_DEFAULT: EVENT_TIME := 1 ps;
constant WND_END_DEFAULT: EVENT_TIME := 0 ps;
Those values can not be used for the purpose of timing simulation. You will have to edit the
counter_TB_declaration.vhd file to supply the appropriate values of the window frames. As shown
in the figure below, the WND_BEGIN_DEFAULT parameter for the design operating with 12.5
MHz clock signal should be greater than 26 ns (which is the delay of the Q output relative to the
CLK falling edge). The figure shows timings for the WND_BEGIN_DEFAULT equal to 30 ns, and
the WND_END_DEFAULT equal to 40 ns.

VHDL Testbench Tutorial

9. Double-click the counter_TB_declaration.vhd file on the Files tab of Design Browser to open
the file for editing. In the editing window, enter WND_BEGIN_DEFAULT in the Find box located
. Next, click the Find Next button, and then
on the left of the Find Next toolbar button
replace the values in the constant declarations as shown below:
constant WND_BEGIN_DEFAULT: EVENT_TIME := 40 ns;
constant WND_END_DEFAULT: EVENT_TIME := 50 ns;
Click the

button.

10. Double-click the counter_tb_runtest.do macro on the Files tab of Design Browser to replace
the line:
run 400 ns with
run 4000 ns
This is required to simulate the whole stretched waveforms.
Save the macro, clicking the

button.

11. Select the counter_tb_runtest.do macro on the Files tab of the Design Browser window.
Click the right mouse button, and then choose Execute from the shortcut menu.
Wait until the shown below message box appears, then click OK.

The results should be as those shown in the picture below.

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VHDL Testbench Tutorial


The Console window still shows many VitalGlitch warnings. Choose End Simulation from the
Simulation menu. If you want to disable the VitalGlitch warnings edit the counter_tb_runtest.do
macro, adding the switch -noglitch to the asim command line.
Thank you for using Active-HDL

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