Abstract – This paper describes complete design and Digital controller design approaches are briefly reviewed
implementation of a digital controller for a highfrequency in Section III from the standpoint of the target converter
switching power supply. Guidelines for the minimum characteristics and operating modes. A digital controller
required resolution of the analogtodigital converter, the design example and implementation details are described
pulsewidth modulator, and the fixedpoint computational in Section IV. Experimental results obtained from the
unit are derived. A design example based on a buck converter
1MHz switching converter with the digital controller are
operating at the switching frequency of 1MHz is presented.
The controller design is based on direct digital design
presented in Section V.
approach and standard rootlocus techniques. Experimental
results are shown to validate the design approach and the II. RESOLUTION OF ANALOGTODIGITAL
allocation of resources (resolution) in the implementation. CONVERTER AND DIGITAL PULSE WIDTH
MODULATOR
I. INTRODUCTION
The system in Fig.1 has an analogtodigital (A/D)
It can be expected that digital controllers will be converter to sample the output voltage, a computational
increasingly used even in lowtomedium power, high unit to determine the value of the switch duty ratio, and a
frequency switching power supplies where conventional digital pulsewidth modulator (DPWM) that outputs a
analog controllers are currently preferred because of cost pulsating waveform that controls the switch(es) in the
and performance reasons [1,2]. converter at the computed duty ratio. The DPWM serves as
This paper addresses practical design and a D/A converter in the control loop. It is of interest to
implementation of a digital controller for a power supply examine the required resolution of A/D and DPWM
that operates at the switching frequency of 1MHz. blocks.
Attention is given to the digital implementation with
limited resources in terms of resolution of A/D and D/A A. Resolution of the A/D converter
(PWM) blocks and the time available to perform the
required computations. To satisfy specifications for the output voltage
Typical system under consideration is shown in Fig.1. regulation, resolution of the A/D converter has to enable
error lower than the allowed variation of the output voltage
∆V0:
+ Load
Switching ∆Vo Vmax V
Vin Vo ⋅ H ≥ n a / d , H = ref
converter Vo 2 a / d ⋅ Vo Vo
 (1)
where:
duty ratio  D Vref  is the reference voltage
Digital Pulse Width Vmax a/d  is the fullrange voltage of the analogtodigital
Modulator converter, assuming unipolar conversion in the range from
H
0 to Vmax a/d
npwm na/d  is the resolution, i.e. the number of output bits of the
A/D converter
na/d H  is the output voltage sensor gain
computational unit
A/D
Rearranging (1) gives the required A/D resolution:
Fig.1. Digital control system for a switching converter
V max a / d Vo
n a / d = int log 2 ⋅ (2)
The required resolution of A/D and PWM units is
V ref ∆Vo
addressed in Section II.
Fig. 2(b) shows the experimental waveforms under the IV. DESIGN EXAMPLE
same conditions as in Fig. 2(a), except that the DPWM
resolution is increased to 8 bits, which is, according to Design of a digital controller for a highfrequency buck
Table I the minimum required DPWM resolution. It can be converter is described in this section. The example
observed that the limit cycle oscillation is removed. converter is designed to generate the output voltage
Design of a highfrequency highresolution digital pulse regulated at 1.8V (with 2% allowed variation) at the output
width modulator can be a significant problem. Most of power of 5W, from an input voltage of 4V to 6V.
today’s designs found in DSP chips intended for motor The test bed used to validate various design approaches
drive applications or in generalpurpose microcontrollers is shown in Fig.3. The setup consists of an Analog Devices
are based on a simple counter approach that requires a high ADMC401 DSP development board, the 1MHz, 8bit
npwm
clock frequency of 2 fs, where fs is the switching DPWM chip [5], and the buck converter power stage.
frequency. A new DPWM design based on a combination M1 L Io [0.2  2.2 A]
of counter and delayline approaches has been described in 1.2uH +
[5]. This approach enables high resolution of 8bit or more +
at switching frequencies up to the MHz range. The use of Vin C 1.2uF Vo R
the DPWM chip in our experimental prototype is described M2

in Section IV.
d(t)
III. DIGITAL REGULATOR DESIGN APPROACHES Pulse Width Modulator 1MHz
clk
There are two basic approaches for digital controller d[n]
design based on the conventional control theory: digital
redesign and direct digital design. Based on comparisons Core processor
of load transient responses, as well as achievable phase ADSP2171
margin and bandwidth in power converter applications, A/D
direct digital design has advantages [6,7]. On the other
ADMC401 Development board
hand, digital redesign enables use of some of the well
known controller design methods previously developed for
continuoustime analog implementation. Fig.3. System used for implementation and experimental test of
various control approaches
For the conventional digital controller design, or for
applications of any of the methods offered by modern ADMC401 is a 26 MIPS, 16bit fixedpoint digital
control theory, it is necessary to develop a discretetime signal processor intended for motor control applications. It
model of the converter (i.e. the plant). One approach is to has a range of peripherals including eight A/D converters,
take into account the switching action in the converter and and enables experiments with change of resolution, and
treat the converter as a sampleddata system that leads with various control algorithms. It should be noted that the
naturally to a discretetime model. Another, simpler builtin PWM units on the ADMC401 would offer only 2
approach is to start with a wellknown continuoustime, bits of resolution at the switching frequency of 1MHz,
averaged model of the converter and transform the model which is why we had to use the external DPWM chip
to a discretetime equivalent using one of the well known described in [5].
transformation techniques [3]. The test bed of Fig.3 has been used to validate a design
Selections of the design and transformation method can targeted for a lowcost, standalone ASIC.
be based on the system dynamics and constrains caused by Based on the criteria presented in Section I, it was found
limited resources available for implementation. that sixbit resolution of the A/D converter, operating at
For the converter configurations where the low Vref equal to 90% of Vmax = 2V meets the 2% allowed
frequency dynamics can be described with a firstorder output voltage variation. From the expressions given in
model (such as for converters in discontinuous conduction Table I, using the worst case point (maximum value of the
mode, DCM), a method with good transformation of input voltage) it was found that the minimum number of
integral properties can be used (Bilinear transform, Euler bits for the DPWM is eight.
or Pole–Zero matching). These methods are also The controller was designed using the direct digital
convenient for the case when the digital redesign is used design approach. The system model is shown in Fig 4.
and when a simple PI controller is adequate. DIGITAL PID DIGITAL PULSE WIDTH DC/DC
REGULATOR MODULATOR
For systems described by secondorder dynamics and CONVERTER
Vref[n] 
D(Z) esTpwm Kpwm Gvd(s)
transformation of integral and derivative properties (such
as PoleZero Matching or Euler) give more accurate
discretetime equivalents of the continuoustime model. c[n]
esTa/d Ka/d
These methods also give a better transformation of
controller properties if a digital redesign method is applied
ANALOGTODIGITAL
to a PID controller. CONVERTER
Fig.4. Block diagram of the digital control system
0780371089/01/$10.00 (C)2001 IEEE 895
IECON'01: The 27th Annual Conference of the IEEE Industrial Electronics Society
The closedloop referencetooutput discretetime Using this method, the pole of H(s) caused by lowpass
transfer function C(z) of this system is: filter was mapped to 0.669, zero at s= ∞ was mapped to
z=1 while the delay was represented according to the rule
C ( z) =
{
D( z ) ⋅ Z K pwm ( s ) ⋅ Gvd ( s ) } 4. Poles of the converter and the gain are not constant
{
1 + D( z ) ⋅ Z K pwm ( s ) ⋅ Gvd ( s ) ⋅ K a / d ( s ) } (7)
values and their position in the zplane depends on the
operating point. For the two extreme operating points
where Gvd(s) is the controltooutput transfer function of (maximum input voltage/minimum load, and minimum
the buck converter operating in CCM: input voltage/maximum load), the plant transfer function is
given by (12) and (13), respectively:
G do
Gvd ( s ) = (8)
s2 11.76e −3
1+
s
+ H ( s) = ⋅ e − sTs (12)
Qω 0 ω 0 2 s s s 2
1 + 1+
3
+
358e 7.76e 6
150.5e9
For the selected converter components and the range of
operating points, it was found that: Gdo varies from 4V to 7.846e −3
6V, the corner frequency (f0) is 132.7kHz, while the load H ( s) = ⋅ e − sTs (13)
s s s 2
variation causes the Q factor to vary from 2 to 20. 1 + 1+
3
+
358e 7.76e
6
150.5e9
The transfer function of the DPWM is:
1
K pwm ( s) = K pwm ⋅ e − sTpwms , K pwm = (9) For the maximum input voltage and the minimum output
n pwm
2 −1 load current, the discretetime equivalent is:
In this case, Kpwm is 1/255 and Tpwm is the delay between
the time the DPWM input is updated and the time the 1.141 ⋅ 10−3 ⋅ (z + 1)
H (z ) =
switch duty ratio changes. (
z ⋅ (z − 0.669) z 2 − 1.331z + 0.9793 ) (14)
The transfer function of the A/D is:
When the load is the heaviest and the input voltage has the
K a / d − sTa / d 1− 2 − na / d minimum value, the discretetime equivalent becomes:
K a / d ( s) = e , Ka / d = (10)
s Vmax a / d
1+
ω lp 0.761 ⋅ 10−3 ⋅ (z + 1)
H (z ) =
(
z ⋅ ( z − 0.669) z 2 − 1.22 z + 0.8119 ) (15)
where Ta/d is the delay caused by the conversion time, and
the gain of the A/D converter (Ka/d) is 0.498. The pole at To achieve a controller suitable for implementation, it
fLP =57kHz in the converter characteristic is caused by a was decided to limit the control law to the second order
lowpass filter which is included on the ADMC401 board. equation. Controller coefficients are determined based on
The discretetime transfer function H(z) of the analog the poleszeros cancellation approach: the controller zeroes
plant is: are selected to (approximately) cancel the poles of the
discrete transfer function H(z). The coefficients obtained
{
H (z ) = Z K pwm ( s ) ⋅ Gvd ( s ) ⋅ K a / d ( s ) } (11) for the polezero cancellation at the two extreme operating
points are different. As a compromise, the final
In this case, the analog plant consists of the switching coefficients of the digital controller are set between the
converter model, the pulse width modulator, and the values that correspond to the two extreme cases. Finally,
analogtodigital converter. The polezero matched the gain of the controller is found using the root locus
transformation method was applied to obtain H(z). method (with the help of the MATLAB rltool [9]). The
The method is simple to apply and the discretetime objective was to place the closedloop system poles inside
model has been shown to reproduce the plant transient the cross section of constantdamping and decrement factor
responses with good accuracy. The second criterion for the areas inside the zplane, for all operating points [10]. The
selection of this method is its relatively low sensitivity to decrement factor area determines the minimum response
coefficient variations. For the plant in (11), the polezero speed, while the constant damping area limits the
matched transformation method is applied as follows [3]: maximum overshoot in the step transient response. The
maximum overshoot was set to 20%, while the minimum
1. If the continuous time plant H(s) has a continuous response speed was set to 50µs.
plant pole at s=ξp+jωP, then the discrete equivalent The obtained discretetime control law is given by:
H(z) has a pole at zP=e ξ ω , where Ts is the
( p+j p)Ts
Limited resolution of the fixedpoint computational unit d[n] = d[n1] + B[n] The new d[n] value
does not allow exact implementation of the control law. formed and available
The closest approximation of the designed controller is
given by:
d[n1] d[n]
d [n] = d [n − 1] + 49.2(e[n] − 1.3e[n − 1] + 0.81e[n − 2]) (17)
e[n2] e[n1]
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