STLD

QUESTION BANK
Unit I
1. A 12-bit Hamming code word containing 8-bits of data and 4 parity bits is read from memory. What was the
original 8-bit data word that was written in to memory if 12-bit words read out is as follows?
[4 4 = 16]
(a) 001111101010
(b) 101110010110
(c) 101110110100
(d) 110011010111
(RR,R05,Nov 08SET II,III)
2. Convert the following to Decimal and then to Hexadecimal.
(a) 7448
(b) 15528
(c) 110110012
(d) 111100112
(e) 55710
(f) 73910
[3+3+3+3+2+2]
(Nov 05,Mar 06,SET II,IV)
3. (a) Perform the following using BCD arithmetic.
[2 4 = 8]
i. 712910 + 771110
ii. 812410 + 812710
(b) Convert the following.
[4 2 = 8]
i. AB16 = ( )10
ii. 12348 = ( )10
iii. 101100112 = ( )10
iv. 77210 = ( )16
(RR,R07,Nov 09SET IiI,IV)
4. Convert the following to Decimal and then to Octal.
(a) 123416
(b) 12EF16
(c) 101100112
(d) 100011112
(e) 35210
(f) 99910
[3+3+3+3+2+2]
5. Convert the following to Decimal and then to Binary.
(a) 101116
(b) ABCD16
(c) 72348
(d) 77668
(e) 12810
(f) 72010.
[3+3+3+3+2+2]
6. Convert the following to Decimal and then to Binary
(a) 231116
(b) A44D16
(c) 74448
(d) 76678
(e) 15810
(f) 72910
[3+3+3+3+2+2]

R07(MAY 10)SET I, II

R07(MAY 10)SET III, IV

(Aug2008,S-1,4)

7. Convert the following to Decimal and then to Octal.

(a) 423416
(b) 125F16
(c) 100100112
(d) 101111112
(e) 39210
(f) 77910 [3+3+3+3+2+2].
Nov 06 SETI I

8. a) What are Hamming Codes? Explain.

b) Convert 100011101101 into 2s complement
c) What are signed bits explain with a example.

[4+8+4]
(RR,R07,MAY10SET IiI,IV)

9. a) What is meant by parity.

b) Explain the concept of Error Correcting & Detecting Codes.

[5+5]

10 a) find the 2s complement of the numbers:

(i) 01001110
(ii) 000110101
b) represent (-17)10 in

(i) sign magnitude

(ii) ones complement
(iii) twos complement
11 .Perform the following operation using 2s complement operation.
(i) 48 , (-23) (ii) 23, (-48) (iii) (-23), (-48).
12. a)Convert (6327.4051)8 into its equivalent decimal number.
b) Convert (3287.5100098)10 into octal
13.Convert the following binary numbers to octal numbers
a) 11001110001.000101111001
b) 1011011110.11001010011
c)111110001.10011001101
14 Add (23)8 and (67)8
15 a) what are the different types of codes.
b) write the various binary codes from 0 to 15 in decimal.
16 Given a = 10101110 and b = 1001 . Find
i) a+b ii) a-b iii) a.b iv)b+a v)b-a

17. a) What is gray code? What are the rules to construct Grey code? Develop the 4 bit gray code for the decimal 0
to 15.
b) What is the advantage of 1s and 2s complement in computers. Represent +45 and -45 in sign-magnitude, sign1s complement and sign-2s complement representation. [8+8]
18 .(a) Construct an even parity seven bit code to transmit the data 1101.
th

(b) Find the 10 element in the base 3 number system. [8+8]

(NR)Nov05
19. (a) Generate Hamming code for the given 11 bit message 10001110101 and rewrite
the entire message with Hamming code. [8]
(b) The binary numbers listed have a sign bit in the left most position and, if negative numbers are in 2s complement form. Perform the arithmetic operations
indicated and verify the answers. [4 2 = 8]
i. 101011 + 111000
ii. 001110 + 110010
iii. 111001 - 001010
iv. 101011 100110

20. (a) Write the following binary numbers in signed 1s complement form and signed
2s complement form using 16 bit registers.
i. +1001010
ii. -11110000

iii. -11001100.1
iv. +100000011.111
(b) Perform N1+N2,N1+(-N2) for the following 8 bit numbers expressed in a 2s
complement representation. Verify your answers by using decimal addition
and subtraction
i. N1=00110010, N2=11111101
ii. N1=10001110, N2=00001101
[10+6]

UNIT II
BOOLEAN ALGEBRA AND SWITCHING FUNCTIONS
(RR,NOV 05 SET I,III)

1. (a) Simplify the function using Karnaugh map method

F (A,B,C,D) =P(4,5,7,12,14,15)+Pd(3,8,10).
(b) Give three possible ways to express the function
F = A B D + A B C D +ABD + ABCD with eight or less literals.
(NR NOV 05 )
2. (a) Find the minimal expression for the function
f(w,x,y,z)=P(0,2,5,9,15) +Pd (6,7,8,10,12,13) using Karnaughs-map.
(b) i. Determine the Canonical sum-of-products form for T(x, y, z) = xy + z + xyz
ii. Minimize the function f(x, y, z,w) = x + xyz + wx + xy + wx + xyz.
[8+4+4]
(R05,NOV 07,SET I)
3. (a) Simplify the following Boolean expressions. [8]
i. AC + ABC + AC to three literals
ii. (xy + z) + z + xy + wz to three literals
iii. AB(D + CD) + B(A +ACD) to one literal
iv. (A + C)(A + C)(A + B + CD) to four literals
(b) Obtain the complement of the following Boolean expressions. [8]
i. BCD + (B + C + D) + B CDE
ii. AB + (AC) + (AB + C)
iii. ABC + A?BC + ABC + ABC
iv. AB + (AC) + ABC
(R05,R07,RR,NOV 07,SET I,II)
4. (a) Simplify the function using Karnaugh map method
F (A,B,C,D) = P(4,5,7,12,14,15)+ Pd(3,8,10).
(b) Give three possible ways to express the function
F = A B D + A B C D + ABD + ABCD with eight or less literals. [8+8]
5. (a) Reduce the following Boolean Expressions [8]
i. AB + A(B + C) + B(B + D)
ii. A +B + ABC
iii. AB + ABC + ABCD + ABCDE
iv. ABEF + AB(EF) + (AB)EF
(b) Obtain the Dual of the following Boolean expressions. [8]
i. xyz + xyz + xyz + xyz
ii. xyz + xyz + xyz + xyz
iii. xz + xy + xyz + yz
iv. xyz + xyz + xyz + xyz + xyz

(R05,NOV 06)

R05(NOV 06,SET I,IV)

6. (a) i. Simplify the Boolean Expression X[Y+Z[(XY + XZ)] .
ii. Obtain the simplified expression in SOP form of x z + y z + yz + xyz.
(b) Obtain the simplified expression in product of sums
F(A, B, C,D) =P (5, 6, 7, 8, 9, 12, 13, 14,).[4+4+8]

(R 05,Nov 07,set I)

7. (a) For the given function find the min term designation and max term designation
F = A'BC + ABC' + ABC + A'B'C
(b) Write the Min terms and Max terms for the following functions
F1= (1,4,6,7,9)
F2 = (3,5,7,11,14)
[8+8]
(R 05,Nov 07,set I)
8. Map the following function and simplify using K-Map
(a) F = (A+B+C) (A+B'+C) (A+B'+C') (A'+B+C)
(b) F = (A'BC'D' + A'BC'D + AB'CD + AB'CD' + ABCD + A'B'C'D')

[16]

(R05,Nov 08,set I)
9. (a) Simplify the following Boolean expressions. [8]
i. AC + ABC + AC to three literals
ii. (xy + z) + z + xy + wz to three literals
iii. AB(D + CD) + B(A +ACD) to one literal
iv. (A + C)(A + C)(A + B + CD) to four literals
(b) Obtain the complement of the following Boolean expressions. [8]
i. BCD + (B + C + D) + B CDE
ii. AB + (AC) + (AB + C)
iii. ABC + A?BC + ABC + ABC
iv. AB + (AC) + ABC

(R07,Nov10,set III)
10. (a) Find the complement of the following and show that F.F?=0 and F+F=1. [8]
i. F=xy+xy
ii. F=(x+y+z)(x+z)(x+y)
(b) Obtain the Dual of the following Boolean expressions. [8]
i. BCD+(B+C+D)+BCDE
ii. AB+(AC)+(AB+C)
iii. ABC+ABC+ABC+ABC
iv. AB+(AC)+ABC
(RR,Nov 06,SET I)
11. (a) i. Simplify the Boolean Expression X[Y+Z[(XY + XZ)] .
ii. Obtain the simplified expression in SOP form of x z + y z + yz + xyz.
(b) Obtain the simplified expression in product of sums
F(A, B, C,D) =P (5, 6, 7, 8, 9, 12, 13, 14,).

[4+4+8]

(R05,Nov08,set III)
12. (a) Reduce the following Boolean Expressions [8]
i. AB + A(B + C) + B(B + D)
ii. A +B + ABC
iii. AB + ABC + ABCD + ABCDE
iv. ABEF + AB(EF) + (AB)EF
(b) Obtain the Dual of the following Boolean expressions. [8]
i. xyz + xyz + xyz + xyz
ii. xyz + xyz + xyz + xyz
iii. xz + xy + xyz + yz
iv. xyz + xyz + xyz + xyz + xyz

13. a) Simplify the following Boolean functions to minimum number of literals.

i) XYXYZ++ ii) ABAB
b) State Duality theorem. List Boolean laws and their duals. [8+8]
14 Obtain the simplified expression in product of sums
F(A, B, C,D) =P (5, 6, 7, 8, 9, 12, 13, 14,).

[16]

15. Obtain the simplified expression in SOP form of x z + y z + yz + xy

Unit III
NOV 09 R05
1. Map the following function and simplify using K-Map
(a) F = (A+B+C) (A+B'+C) (A+B'+C') (A'+B+C)
(b) F = (A'BC'D' + A'BC'D + AB'CD + AB'CD' + ABCD + A'B'C'D')
[16]
NOV 09 R05
2. (a) Implement the following function using only NOR gates F=a .(b+ c.d) + (b. c).
(b) Implement the following function using only NAND gates G=(a + b). (c. d+ e )
(c) Give the minimum two-level SOP realization of the following switching function using only NAND gates.
F(x,y,z) = P m (0,3,4,5,7)
NOV 10 RR
[4+4+8]
4. Determine the canonical Product of sum form for the function and simplify using k-map
(a) Y(x,y,z) = x(y'+z)
(b) Y(a,b,c) = ab' + bc
(c) Y(w,x,y,z) = wxy' + x(y'+z)
(d) Y(a,b,c) = (ab + c')(ac + b')
[16]
MAY 07 R05
5.(a) Design a logic circuit to provide an output when any two or three or four switches are closed.
(b) Minimize the following Boolean function using K-map F = (2, 7, 8, 9, 10, 12).
[8+8]
NOV07 R07
6. Design a combinational logic circuit with 4 inputs A, B, C, D. The output Y goes HIGH if and only if B and
C inputs go HIGH. Draw the Truth table. Minimize the Boolean function using K-map. Draw the circuit
diagram.
[16]
JAN 03 OR
7. (a) Implement the following function using only NOR gates F=a .(b+ c.d) + (b. c).
(b) Implement the following function using only NAND gates G=(a + b). (c. d+ e )
(c) Give the minimum two-level SOP realization of the following switching function using only NAND gates.
F(x,y,z) = P m (0,3,4,5,7)
[4+4+8]
APR 08 R07
8. Explain the type of Hazard if any in the EXCLUSIVE - OR circuit made by five
NAND gates and the EXCLUSIVE ?OR circuit made by four NAND gates as shown
in figure BELOW .
[16]

NOV 09, MECH R09, III/I SEM.

9.a) State Duality theorem. List Boolean laws and their Duals.
b) Simplify the following Boolean functions to minimum number of literals:
a) xy + xy
b) (x + y)(x+y).
c) Realize XOR gate using minimum number of NAND gates. [8+4+4]
NOV 07 R07
a) State the purpose of reducing the switching functions to minimal form.
b) Write the Dual of
i) (A+BC +AB)
ii) (AB+BC+CD)
c) Give the truth table for the Boolean expression (X+Y)
[4+8+4]
JAN 10 RR
11. (a) Derive Boolean expression for a 2 input Ex-NOR gate realized with two input
NOR gates, without using complemented variables and draw the circuit.
(b) Redraw the given circuit (_gure5b) after simpli_cation.
[8+8]

10.

APR 08 ,R05
12.(a) For the given function find the min term designation and max term
designation F = A'BC + ABC' + ABC + A'B'C
(b) Write the Min terms and Max terms for the following functions
F1= (1,4,6,7,9)
F2 = (3,5,7,11,14)

[8+8]

NOV R09 MECH

13. Apply Branching method to simplify the following function
[16]
F (A, B, C, D) =QM(0, 1, 4, 5, 9, 11, 13, 15, 16, 17, 25, 27, 28, 29, 31)d(20, 21, 22, 30).
MAY 10 R07
14. Minimize the the following multiple output functions.
f1 = Pm(0, 2, 6, 10, 11, 12, 13) + d(3, 4, 5, 14, 15)
f2 = Pm(1, 2, 6, 7, 8, 13, 14, 15) + d(3, 5, 12).
[16]
NOV 09 RR
(15) Give three possible ways to express the function
[16]
F = A B D + A B C D + ABD + ABCD with eight or less literals.
MAY 03 RR ECE, EIE
16 a) Determine the minimal sum of product form of
[8+8]
i) f(w, x, y, z) = m(4, 5, 7, 12, 14, 15) + (3, 8, 10).
ii) f(A, B, C, D) = M(0, 3, 5, 6, 8, 12, 15).
JAN 03 OR
17 a) Simplify the following Boolean functions to minimum number of literals.
(i)
X+Y+XYZ (ii) (A+B)(A+B)
b) State Duality theorem. List Boolean laws and their duals.
[8+8]
18.a) Draw a logic diagram using only two-input NAND gates to implement the following expression: (AB +
A'B') (CD' + C'D)
[8+8]
b)
Derive the circuits for a three-bit parity generator and four-bit parity checker using odd parity bit.
19 Simplify the following Boolean expressions and implement by using only NAND gates.
(i)
[8+8]
Y = A( A + B ) ( AB + B )
20

(i)
Z = ( A + B) ( A + C ) ( B + C )
State the basic laws of Boolean algebra and explain.

Apr/May 2008
R05 SET 1
(1) Expand A + B C + ABD + ABCD to minterms and maxterms.
Apr/May 2008
R05 SET 4

[16]

[16]

2 (a) What is a cell of a K-map? What is meant by pair, a quad, and an octet of a
map and how many variables are eliminated?
[8]
(b) Reduce the following function using K- map and implement it using NAND
logic. F= Pm(0, 2, 3, 4, 5, 6, )
[8]
JUN 10
R05 SET 1
3.a) What are the advantages of Tabulation method over K-map?
b) Simplify the following Boolean function using Tabulation method.
Y(A,B,C,D) = (1,3,5,8,9,11,15)
[2+14]
JUN 10
R05 SET 4
4.a) What are the advantages of Tabulation method over K-map?
b) Simplify the following Boolean function using Tabulation method.
Y(A,B,C,D) = (1,3,5,8,9,11,15)
[8+8]

JUN 10
R07 SET 1
5.a) Define the following terms with respect to K-Map with an example.
i) Prime implicant
ii) Redundant terms
iii) Essential Prime implicants
iv) Octet
b) Determine Prime implicants and essential prime implicants for the following function.
F(w,x,y,z) = m(8,12,13,18,19,21,22,24,25,28,30,31) + d(1,2,4,6,7,11,26)
[8+8]
JUN 10
R07 SET 3
6. Design a logic circuit with BCD input and the output of the circuit should produce a gray code for corresponding
input. Use K-map for reduction.
[16]
JUN 10
RR SET 1
7. (a) Simplify the function using Karnaugh map method
[8]
F (A,B,C,D) = P(4,5,7,12,14,15)+ Pd(3,8,10).
NOV 07
R05 SET 1
8. (a) Convert the following expressions in to sum of products and product of sums[8]
i. (AB + C) ( B + CD)
ii. x + x(x + y)(y + z)
(b) Obtain the Dual of the following Boolean expressions.
[8]
i. (AB + AC)(BC + BC)(ABC)
ii. ABC + ABC + ABC
iii. (ABC)(A + B + C)
iv. A + BC (A + B + C)
NOV 07
R05 SET 4
9. Minimize the following function using tabular minimization and verify the same
with K-map minimization
F = Pm(0, 1, 6, 7, 8, 9, 13, 14, 15)
[8+8]
NOV 07

R05 SET 3

10. (a) What are the advantages and disadvantages of the tabular method vis--vis the
K-map?
[6]
(b) Reduce the following function using K-map
F = QM(1, 4, 5, 6, 7, 8, 9, 14, 15, 22, 23, 24, 25, 28, 29, 30, 31)
[10]
MAY 03
OR
11. a) Simplify the following Boolean function using Tabular method
f= (0,1,2,3,4,,6,8,9,10,11)

MAY 02
OR
12.a) Simplify the following Boolean function using K map
F (w,x,y,z) = ( 0,1,2,4,5,6,8,9,12,13,14).
13. (NOVEMBER, 2009, R07, Set-4)

14. (NOVEMBER, 2009, R07, Set-1)

15. (NOVEMBER, 2009, R07, Set-2)

Unit IV
( R07,R05 JUN2010, Set-2),RR SET II,IV
1.
a) Differentiate synchronous and asynchronous circuits.
b) Design a 2 to 4 decoder using NAND gates.
[8+8]
( R05 JUN2010, Set-2)
2 .a) What is Encoder? Design decimal to BCD Encoder.
b) Explain how a decoder can be converted in to a demultiplexer with relevant block diagrams and truth
tables.
[10+6]
RR JUN10 SET 4
3. a) What is decoder? Construct 3*8 decoder using logic gates and truth table.
b) Implement full adder using decoder and OR gates.
[8+8]
RR,R05,R07 JUN 07 ,MAY 05
4.a) Design a converter circuit which converts 8,4,2,-1 code to 8,4,2,1 code
b) Implement a Full adder using decoder and logic gates
[8+8]
RR,R05 JUN,05,10 SET 1 ,4
5 List the applications of Multiplexer and Demultiplexer. [8]
RR,R05 NOV,05,06, SET 1 ,4
6.
Write short notes on any Three:
a) SOP and POS forms.
b) PLA and PAL.
c) RAM, ROM, EPROM and E2PROM.
d) Multiplexer and decoder.
Nov 09 R05 MECH,EIE
7.a) Design a modulo 6-counter which counts in the way given below. Use T-flip flop.
Decimal Gray
0
000
1
001
2
011
3
010
4
110
5
111
b)

Explain the principle of 4-bit adder.

Nov 10 RR ,

8 .a) List the advantages of synchronous counters over ripple counters.

b) Using a shift register and a combinational logic circuit, design a sequence generator which will
generate the binary sequence: 01001011101
RO7 MAY 10 OR APR 04
9.a) Draw the block diagram of BCD Adder and explain its operation.
b) Explain the construction of a Johnson counter.
R05 APR 08,OR,NR MAY 02,03
10 Implement Full adder circuit using ROM and Verify the working.

Unit V
1.

(R07 JUN2010, Set-2)

2.

(R07 JUN2010, Set-4)

3.
( R07 JUN2010, Set-4)
a) Write in detail about types of Read only memories.
b) Write in detail to program a ROM to implement Boolean functions. [8+8]
( R07 JUN2010, Set-2)
4 . Write about Programmable Array Logic. Mention the advantages of Programmable Array logic. Represent the
conventional symbol and array logic symbol of PAL. Give the internal connections of PAL.
[16]
( R07 JUN2010, Set-4)
5. Implement the following functions using PAL and PLA
F1 = m (2,3,4,7,8,11)
F2 = m (1,3,5,7,9,11,13,15)
MAY 03 , (ECE & EIE)
6. a)Generate a PLA program table to design a BCD to excess 3 code converter.
b) Write brief note o n multi gate synthesis of threshold logic.
RR JUN 10,R05 JUN 10,RR NOV 09,R05 NOV 07
7 a) Write a note on PROM, PAL and PLA architecture.
b) Implement a full sub tractor using ROM.
RR JUN 10,R05 JUN 10,RR ,R05 NOV 07

[16]

[8+8]
[8+8]

8 Derive the PLA programming table for the combinational circuit that squaresa 3 bit number.
[16]
Unit VI
1.
(JUN2010, Set-2)

2.

(JUN2010, Set-2)

3.

(JUN2010, Set-2)

4.

(JUN2010, Set-4)

5.

(JUN2010, Set-4)

(R 07 JUN2010, Set-1)
6. a) Differentiate Latch and flip-flop. Explain the construction of S-R Latch.
b) Construct a D-Latch and explain its operation.
[8+8]
(R 07 JUN2010, Set-2)
7. a) Differentiate edge triggering , Level triggering and Pulse triggering.
b) Design a clocked JK flip flop. Explain its operation with the help of characteristic table and characteristic
equation. Give the symbol of edge triggered JK flipflop.
[8+8]
(RRJUN05 , Set-2)
8. a) Design a 4-bit Bidirectional Shift Register.
b) Convert D flip op to T flip flop. [8+8]
(RR JUN 10)
9.a) Explain the operation of a master-slave JK flip flop in each clock cycle over a period of six consecutive clocks.
b) Explain the operation of a Johnson counter with neat diagram.
[16]

(R 05 JUN10)
10. a) Draw the logic, diagram of a JK flip flop and using excitation table, explain its operation.
b) Explain the operations of a 4-bit synchronous binary counter with neat diagram. [8+8]
(R 07 JUN10, Set-4)
11 a) Give the excitation tables of all flip flops and explain.
b) Convert D flip flop in to T, JK and SR flip flop.

[8+8]

(R 07 JUN10, Set-2)
12 a) What is the basic difference between a pulse mode and level mode circuits.
b) Draw a neat circuit diagram of positive edge trigged JK flip flop and explain. [8+8]
(R05 NOV 07)
13 . (a) Compare synchronous & Asynchronous circuits
(b) Design a Mod-6 synchronous counter using J-K flip flops.

[6+10]

(R 07 JUN2010, Set-2)
14 .a) Define state diagram. Explain the procedure to reduce the state diagram.
b) For the state diagram shown, obtain the state table and design the circuit using minimum number of JK
Flip Flops.

(R 05 APR 08)
15.a) Design a BCD counter with JK flip flops.
b) Draw the diagram of a 4-bit Binary ripple counter using flip flops that trigger on the positive edge.
[16]
Unit VII
(R 07 JUN2010, Set-1)
1. a) Write short notes on :
i) State transition function.
ii) Finite State model.
iii) Terminal state
iv) Strongly connected machine
b) Discuss on the capabilities and limitations of finite state machines.
[8+8]
R07 MAY 10 SET I1
2. Minimize the following incompletely specified machine using Merger Graph method. [16]

R07 MAY 10 SET IV

3. For the machine shown, find the equivalent partition and a corresponding reduced machine in standard form.
[16]
PS
A
B
C
D
E
F
G

X=0
F,0
G,0
B,0
C,0
D,0
E,1
E,1

NS,Z
X=1
B,1
A,1
C,1
B,1
A,1
F,1
G,1

R07 MAY 10 SET III

4. The state table of a sequential machine is shown below. Obtain the compatibility graph using.
(a) Merger graph
(b) Merger Table
[16]
PS
X=0
F,0
G,0
B,0
C,0
D,0
E,1
E,1

A
B
C
D
E
F
G

NS,Z
X=1
B,1
A,1
C,1
B,1
A,1
F,1
G,1

R05 NOV 07 SET I.II, IV

5. A clocked sequential circuit is provided with a single input x and single output Z.
Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the
sequence it produce an output Z = 1 and overlapping is also allowed.
(a) Obtain State - Diagram.
(b) Also obtain state - Table.
(c) Find equivalence classes using partition method & design the circuit using D FF
[4+4+8]
(JUN2010, Set-1), (R05 JUN2008, Set-3) (JUN2010, Set-1&2)
6. a) Write the differences between Mealey and Moore type machines,
b) What are the basic building blocks of an ASM chart? Explain with neat diagram. [8+8]

Unit VIII
1.

(JUN2010, Set-2)

2.

(JUN2010, Set-4)

(R05 JUN2008, Set-2)

3.

(JUN2010, Set-1), (R05 JUN2008, Set-3) (JUN2010, Set-1&2)

4. Design the ASM chart, Data path circuit & Control circuit to implement traditional
division of two four bit binary numbers.
[16]

(R05 JUN2008, Set-4)

5.

(R05 NOV 07,R05 APR 08)

6.

(R07 JUN2008, Set-4)

7. Draw an ASM chart to design a binary multiplier control. Design the control using D flip flops and Decode logic.
[16]
8 Write a brief notes on.
a) Building blocks of ASM charts.
b) Binary multiplier operation.

9(a) For the given ASM chart obtain its equivalent state diagram below .
(b) Design the circuit using mulitiplexes.

11

[8+8]

[8+8]

12 Show the exit paths in an ASM block for all binary combinations of control
variables x, y and z, starting from an initial state.
[16]

13 Draw the ASM chart of binary multiplier and design the control circuit using each
methods:(a)
JK flip flop & gates
(b)
D flip flop & decoder.

Write short notes on :

a)
ASM chart
b)
Finite state machines
c)
Asynchronous Vs Synchronous circuits.
15(a) Draw the state diagram and the state table of the control unit conditions given
below. Draw the equivalent ASM chart leaving the state box empty.
i. from 00 state, if x = 1 , it goes to 01 state and if x = 0, it remains in the
same state 00.
ii. from 01 state, if y = 1, it goes to 11 state and if y = 0, it goes to 10 state.
iii. from 10 stae, if x = 1 and y = 0, it remains in the same state 10 and if x
= 1 and y = 1, it goes to 11 state, and if x = 0, it goes to 00 state.
iv. from 11 state, if x = 1, y = 0, it goes to 10 state and if x = 1, and y =
1, it remains in the same state, and if x = 0, it goes to 00 state.
(b) Design the control using PLA and registers for the above problem. [8+8]

14

16. (a) Explain in detail the block diagram of ASM chart. [16]

of

the

following