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Data Sheet
FN6398.3
Features
Ordering Information
ISL6266HRZ
ISL6266 HRZ
ISL6266HRZ-T*
ISL6266 HRZ
ISL6266AHRZ
Thermal Monitor
User Programmable Switching Frequency
Differential Remote CPU Die Voltage Sensing
Static and Dynamic Current Sharing
Support All Ceramic Output with Coupled Inductor
(ISL6266)
Overvoltage, Undervoltage and Overcurrent Protection
Pb-Free (RoHS Compliant)
PART NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(C)
PACKAGE
(Pb-free)
PKG.
DWG. #
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007-2010 All Rights Reserved. R3 Technology is a trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
ISL6266, ISL6266A
Pinout
3V3
CLK_EN#
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
ISL6266, ISL6266A
(48 LD 7x7 QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
PGOOD
36 BOOT1
PSI#
35 UGATE1
PMON
34 PHASE1
RBIAS
33 PGND1
VR_TT#
32 LGATE1
NTC
SOFT
OCSET
29 PGND2
VW
28 PHASE2
COMP 10
27 UGATE2
31 PVCC
GND PAD
(BOTTOM)
30 LGATE2
FB 11
26 BOOT2
FB2 12
13
14
15
16
17
18
19
20
21
22
23
24
VDIFF
VSEN
RTN
DROOP
DFB
VO
VSUM
VIN
GND
VDD
ISEN2
ISEN1
25 NC
FN6398.3
June 14, 2010
ISL6266, ISL6266A
Absolute Maximum Ratings
Thermal Information
JAC/W
JCC/W
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See
Tech Brief TB379.
2. For JC, the case temp location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 4)
TYP
MAX
(Note 4) UNITS
IVDD
VR_ON = 3.3V
5.1
5.7
mA
VR_ON = 0V
I3V3
No load on CLK_EN#
IVIN
PORr
VDD Rising
4.5
PORf
VDD Falling
4.0
-0.5
0.5
-8
mV
-15
15
mV
-0.8
0.8
-10
10
mV
-18
18
mV
RRBIAS = 147k
1.45
1.47
1.49
1.188
1.2
1.212
4.35
4.15
%Error
(VCC_CORE)
%Error
(Vcc_core)
RBIAS Voltage
RRBIAS
Boot Voltage
VBOOT
VCC_CORE
(max)
VID = [0000000]
1.5
VCC_CORE
(min)
VID = [1100000]
0.3
VID = [1111111]
FN6398.3
June 14, 2010
ISL6266, ISL6266A
Electrical Specifications
PARAMETER
MIN
(Note 4)
TYP
410
440
470
kHz
280
300
320
kHz
100
600
kHz
-0.25
0.25
mV
SYMBOL
TEST CONDITIONS
MAX
(Note 4) UNITS
CHANNEL FREQUENCY
Nominal Channel Frequency
fSW
Adjustment Range
AMPLIFIERS
Droop Amplifier Offset
Error Amp DC Gain
AV0
(Note 3)
90
dB
GBW
CL = 20pF (Note 3)
18
MHz
SR
CL = 20pF (Note 3)
V/s
10
IIN(FB)
150
nA
mV
ISEN
Imbalance Voltage
Input Bias Current
20
nA
SOFT-START CURRENT
Soft-Start Current
ISS
IGV
IC4
-47
-42
-37
180
205
230
DPRSLPVR = 3.3V
-47
-42
-37
IC4EA
DPRSLPVR = 3.3V
37
42
47
IC4EB
DPRSLPVR = 0V
180
205
230
1.5
RSRC(UGATE)
ISRC(UGATE)
RSNK(UGATE)
ISNK(UGATE)
RSRC(LGATE)
ISRC(LGATE)
RSNK(LGATE)
ISNK(LGATE)
0.5
Rp(UGATE)
A
1.5
1.5
0.9
GATE DRIVER SWITCHING TIMING (refer to ISL6266, ISL6266A Gate Driver Timing Diagram on page 6)
UGATE Rise Time
tRU
8.0
ns
tRL
8.0
ns
tFU
8.0
ns
tFL
4.0
ns
tPDHU
ISL6266AHRZ
TA = -10C to +100C
PVCC = 5V, Outputs Unloaded
20
30
44
ns
tPDHU
ISL6266AIRZ
18
30
44
ns
FN6398.3
June 14, 2010
ISL6266, ISL6266A
Electrical Specifications
PARAMETER
SYMBOL
tPDHL
ISL6266AHRZ
tPDHL
ISL6266AIRZ
MIN
(Note 4)
TYP
TA = -10C to +100C
PVCC = 5V, Outputs Unloaded
15
30
ns
15
30
ns
0.43
0.58
0.72
0.4
TEST CONDITIONS
MAX
(Note 4) UNITS
BOOTSTRAP DIODE
Forward Voltage
Leakage
VR = 16V
VOL
IPGOOD = 4mA
IOH
PGOOD = 3.3V
-1
PGOOD Delay
tpgd
6.3
7.6
8.9
ms
Overvoltage Threshold
OVH
155
195
235
mV
OVHS
1.675
1.7
1.725
10
10.2
3.5
mV
0.26
I(RBIAS) = 10A
9.8
OC Threshold Offset
-3.5
Undervoltage Threshold
(VDIFF-SOFT)
UVf
9
-360
-300
mV
-240
mV
LOGIC INPUTS
VR_ON, DPRSLPVR Input Low
VIL(3.3V)
VIH(3.3V)
IIL(3.3V)
IIH(3.3V)
2.3
-1
VIL(1V)
VIH(1V)
IIL(1V)
IIH(1V)
0
0
-1
V
A
1
0
0.45
A
1
0.3
0.7
-1
V
0
0.45
53
60
67
1.18
1.2
1.22
6.5
THERMAL MONITOR
NTC Source Current
NTC = 1.3V
Over-Temperature Threshold
V(NTC) falling
RTT
I = 20mA
POWER MONITOR
PMON Output Voltage Range
Vpmon
Vpmonmax
1.638
1.680
1.722
0.308
0.350
0.392
2.8
3.0
FN6398.3
June 14, 2010
ISL6266, ISL6266A
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 4)
TYP
MAX
(Note 4) UNITS
Isc_pmon
mA
Isk_pmon
mA
Refer to Figure 29
PMON/
250
PMON Impedance
PMON/
180
PMON/
100
3.1
VOH
VOL
ICLK_EN# = 4mA
2.9
0.26
0.4
NOTES:
3. Limits established by characterization and are not production tested.
4. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
tPDHU
tFU
tRU
1V
UGATE
1V
LGATE
tRL
tFL
tPDHL
FN6398.3
June 14, 2010
ISL6266, ISL6266A
3V3
CLK_EN#
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
48
47
46
45
44
43
42
41
40
39
38
37
PGOOD
36 BOOT1
PSI#
35 UGATE1
PMON
34 PHASE1
RBIAS
33 PGND1
VR_TT#
32 LGATE1
NTC
SOFT
OCSET
29 PGND2
VW
28 PHASE2
COMP 10
27 UGATE2
31 PVCC
GND PAD
(BOTTOM)
30 LGATE2
FB 11
26 BOOT2
FB2 12
13
14
15
16
17
18
19
20
21
22
23
24
VDIFF
VSEN
RTN
DROOP
DFB
VO
VSUM
VIN
GND
VDD
ISEN2
ISEN1
25 NC
FN6398.3
June 14, 2010
ISL6266, ISL6266A
PGOOD - Power good open-drain output. Connect
externally with 680 to VCCP or 1.9k to 3.3V.
BOOT2 - This pin is the upper gate driver supply voltage for
Phase 2. An internal boot strap diode is connected to the
PVCC pin.
FN6398.3
June 14, 2010
ISL6266, ISL6266A
PGND2
LGATE2
PHASE2
UGATE2
BOOT2
PGND1
LGATE1
PHASE1
UGATE1
BOOT1
VR_TT#
NTC
6A
54A
PVCC
PVCC
PVCC
PVCC
VDD
PVCC
1.2V
VIN
PVCC
1.24V
DRIVER
LOGIC
VIN
DRIVER
LOGIC
ULTRASONIC
TIMER
FLT
FLT
ISEN2
CURRENT
BALANCE
ISEN1
VSOFT
I_BALF
VIN
GND
VSOFT
VIN
MODULATOR
MODULATOR
OC
OC
CH1
CH2
VW
3V3
CH1
CH2
COMP
Vw
FAULT AND
PGOOD
LOGIC
SINGLE
PHASE
VO
E/A
VIN
FB
SINGLE
PHASE
PMON
OC
VDIFF
MODE CHANGE
REQUEST
0.5
RTN
VO
DROOP
VSEN
VO
DROOP
DFB
VSUM
OCSET
10A
DPRSTP#
DPRSLPVR
PSI#
VR_ON
VID6
VID5
VID4
VID3
VID2
MODE
CONTROL
DAC
VID1
SINGLE
PHASE
MULTIPLIER
VO
DACOUT
VID0
SOFT
VSOFT
SOFT
RBIAS
FB2
PHASE
CONTROL
LOGIC
PGOOD
FLT
PHASE
SEQUENCER
CLK_EN#
Vw
PGOOD
MONITOR
AND LOGIC
PGOOD
FN6398.3
June 14, 2010
ISL6266, ISL6266A
Typical Performance Curves
1.16
100
90
1.14
70
VIN = 8.0V
60
VIN = 12.6V
VIN = 8.0V
1.12
VIN = 19.0V
VOUT (V)
EFFICIENCY (%)
80
50
40
VIN = 12.6V
1.10
VIN = 19.0V
1.08
30
20
1.06
10
0
10
15
20
25
30
35
40
45
1.04
50
10
20
IOUT (A)
40
50
100
1.01
VIN = 8.0V
90
VIN = 12.6V
1.00
80
70
0.99
VIN = 8.0V
60
VIN = 12.6V
50
VOUT (V)
EFFICIENCY (%)
30
IOUT (A)
VIN = 19.0V
40
30
0.98
0.97
VIN = 19.0V
0.96
20
0.95
10
0
10
15
20
0.94
25
10
IOUT (A)
20
25
0.765
100
90
0.764
80
0.763
VIN = 12.6V
70
0.762
VIN = 8.0V
60
VOUT (V)
EFFICIENCY (%)
15
IOUT (A)
50
40
VIN = 12.6V
VIN = 19.0V
30
0.761
0.760
0.759
VIN = 19.0V
20
0.758
10
VIN = 8.0V
0.757
0
0.1
1.0
IOUT (A)
10
10.0
IOUT (A)
FN6398.3
June 14, 2010
ISL6266, ISL6266A
Typical Performance Curves
(Continued)
VR_ON
VOUT
VOUT
VSOFT
VR_ON
VSOFT
CSOFT = 15nF
CSOFT = 15nF
CLK_EN#
VIN
IMVP-6_PWRGD
IIN
VOUT @ 1.15V
VOUT
VR_ON
DPRSTP#
VOUT
VID6
DPRSLPVR
IIN
VOUT
11
FN6398.3
June 14, 2010
ISL6266, ISL6266A
Typical Performance Curves
(Continued)
VOUT
VOUT
VID3
VID3
VOUT
VOUT
PHASE1
PHASE1
PHASE2
PHASE2
PSI#
PSI#
VOUT
VOUT
PHASE1
PHASE1
PHASE2
PHASE2
12
FN6398.3
June 14, 2010
ISL6266, ISL6266A
Typical Performance Curves
(Continued)
DPRSLPVR
DPRSLPVR/PSI
VOUT
VOUT
PHASE1
PHASE1
PHASE2
PHASE2
VOUT
DPRSLPVR
VOUT
IMVP-6_PWRGD
PHASE1
PHASE2
IOUT
VID3
IMVP-6_PWRGD
VOUT
VOUT
PMON UNFILTERED
PHASE1
13
PMON FILTERED
FN6398.3
June 14, 2010
ISL6266, ISL6266A
Typical Performance Curves
(Continued)
VOUT
VOUT
PMON UNFILTERED
PMON UNFILTERED
PMON FILTERED
PMON FILTERED
VOUT
PMON UNFILTERED
PMON FILTERED
FIGURE 28. VID = 1.15V, LOAD RELEASE FROM 36A TO 0A WITH INTEL VTT TOOL, 1kHz RATE, 50% DUTY CYCLE, TR = 35
1.8
0.8
1.6
19V, 1.15V, 40A
0.6
1.2
1.0
PMON (V)
PMON (V)
1.4
0.8
19V, 1.15V, 10A
0.6
19V, 1.15V, 5A
0.5
0.2
0.1
1
2
3
4
5
CURRENT SOURCING (mA)
14
180
0.3
0.2
0.4
0.4
0.0
0.7
0.0
0.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
FN6398.3
June 14, 2010
ISL6266, ISL6266A
Simplified Coupled Inductor Application Circuit for DCR Current Sensing
+5V
R12
+3.3V
VIN
3V3
RBIAS
NTC
ISL6266
C7
R13
VR_TT#
VR_TT#
C8
VID<0:6>
UGATE1
BOOT1
SOFT
C6
VIDs
PHASE1
R8
DPRSTP#
DPRSTP#
VSUM
LGATE1
DPRSLPVR
DPRSLPVR
PGND1
PSI#
PSI#
ISEN1
ISEN1
PMON
CLK_ENABLE#
CLK_EN#
VR_ON
VR_ON
IMVP-6_PWRGD
PGOOD
RL
VIN
CL VO'
C8
R10
VSEN
REMOTE
SENSE
VO
UGATE2
RTN
PHASE2
C3
R7
R11
RL
LGATE2
FB2
FB
C1
CO
C5
VDIFF
R3
LO
BOOT2
R2
VO'
R9
PGND2
R1
CL
VSUM
COMP
ISEN2
C2
RFSET
ISEN2
VSUM
VSUM
VW
OCSET
C9
GND
DFB
DROOP VO
R5
R6
R4
C4
RN
NTC
NETWORK
CCS
VO'
FIGURE 31. ISL6266 BASED TWO-PHASE COUPLED INDUCTOR DESIGN WITH DCR SENSING
15
FN6398.3
June 14, 2010
ISL6266, ISL6266A
Simplified Application Circuit for DCR Current Sensing
+5V
VIN
+3.3V
R12
3V3
RBIAS
NTC
ISL6266A
C7
R13
VR_TT#
VR_TT#
C8
VID<0:6>
UGATE1
BOOT1
SOFT
LO
C6
VIDs
PHASE1
R10
DPRSTP#
DPRSTP#
CL
RL
LGATE1
DPRSLPVR
ISEN1
DPRSLPVR
PSI#
VO'
R8
PGND2
PSI#
VO
VSUM
ISEN1
PMON
CO
CLK_ENABLE#
CLK_EN#
VR_ON
VR_ON
IMVP-6_PWRGD
PGOOD
VIN
C8
VSEN
REMOTE
SENSE
UGATE2
RTN
R2
C5
VDIFF
R3
PHASE2
C3
R7
R11
RL
LGATE2
FB2
FB
C1
LO
BOOT2
R9
PGND2
R1
ISEN2
CL
VO'
VSUM
COMP
ISEN2
C2
RFSET
VSUM
VSUM
VW
OCSET
C9
GND
DFB
DROOP VO
R5
R6
R4
C4
RN
NTC
NETWORK
CCS
VO'
FIGURE 32. ISL6266A BASED TWO-PHASE BUCK CONVERTER WITH INDUCTOR DCR CURRENT SENSING
16
FN6398.3
June 14, 2010
ISL6266, ISL6266A
Simplified Application Circuit for Resistive Current Sensing
+5V
VIN
+3.3V
R11
3V3
RBIAS
ISL6266A
NTC
C7
R12
VR_TT#
VR_TT#
C9
VID<0:6>
UGATE1
BOOT1
SOFT
RS
C6
VIDs
PHASE1
R10
DPRSTP#
DPRSTP#
CL
RL
LGATE1
DPRSLPVR
ISEN2
DPRSLPVR
PSI#
VO'
R8
PGND2
PSI#
VO
VSUM
ISEN1
PMON
CO
CLK_ENABLE#
CLK_EN#
VR_ON
VR_ON
IMVP-6_PWRGD
PGOOD
VIN
C8
VSEN
REMOTE
SENSE
UGATE2
RTN
PHASE2
C3
R11
R7
RL
LGATE2
FB2
FB
C1
RS
C5
VDIFF
R3
BOOT2
R2
R9
PGND2
R1
ISEN2
CL
VO'
VSUM
COMP
ISEN2
C2
RFSET
VSUM
VSUM
VW
OCSET
C9
GND
DFB
DROOP VO
R5
R6
R4
CHF
C4
VO'
FIGURE 33. ISL6266A BASED TWO-PHASE BUCK CONVERTER WITH RESISTIVE CURRENT SENSING
17
FN6398.3
June 14, 2010
ISL6266, ISL6266A
Theory of Operation
VDD
10mV/s
VR_ON
2.8mV/s
100s
VBOOT
SOFT AND VO
VID COMMANDED
VOLTAGE
90%
13 SWITCHING CYCLES
CLK_EN#
~7ms
IMVP-6 PGOOD
Static Operation
After the start sequence, the output voltage will be regulated
to the value set by the VID inputs shown in Table 1. The
entire VID table is presented in the intel IMVP-6
specification. The ISL6266A will control the no-load output
voltage to an accuracy of 0.5% over the range of 0.75V to
1.5V.
TABLE 1. TRUNCATED VID TABLE FOR INTEL IMVP-6+
SPECIFICATION
VOUT
(V)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1.5000
1.4875
1.4375
1.2875
Start-Up Timing
1.15
0.8375
0.7625
0.3000
0.0000
18
ISL6266, ISL6266A
minus the output voltage, VO, is a high-bandwidth analog of
the total inductor current. This voltage is used as an input to
a differential amplifier to achieve the IMVP-6+ load line, and
also as the input to the overcurrent protection circuit.
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding thus maintaining the
load-line accuracy.
In addition to monitoring the total current (used for DROOP
and overcurrent protection), the individual channel average
currents are also monitored and used for balancing the load
between channels. The IBAL circuit will adjust the channel
pulse-widths up or down relative to the other channel to
cause the voltages presented at the ISEN pins to be equal.
The ISL6266A controller can be configured for two-channel
operation, with the channels operating 180 apart. The
channel PWM frequency is determined by the value of
RFSET connected to pin VW as shown in Figures 32 and 33.
Input and output ripple frequencies will be the channel PWM
frequency multiplied by the number of active channels.
TABLE 2. CONTROL SIGNAL TRUTH TABLES FOR OPERATION MODES OF ISL6266 AND ISL6266A
DPRSLPVR
DPRSTP#
PSI#
ISL6266
ISL6266A
CPU MODE
1-phase CCM
fast
awake
2-phase CCM
2-phase CCM
fast
awake
1-phase CCM
fast
awake
2-phase CCM
2-phase CCM
fast
awake
slow (Note 5)
sleep
slow (Note 5)
sleep
1-phase CCM
slow
awake
2-phase CCM
2-phase CCM
slow
awake
NOTE:
5. The negative VID slew rate when DPRSTP# = 0 and DPRSLPVR = 1 is limited to no faster than the slow slew rate. However, slower slew rates
can be seen. To conserve power, the ISL6266A will tri-state UGATE and LGATE and let the load gradually pull the core voltage back into
regulation.
19
FN6398.3
June 14, 2010
ISL6266, ISL6266A
While transitioning to single-phase operation, the controller
smoothly transitions current from the idling-phase to the activephase, and detects the idling-phase zero-current condition.
During transitions into automatic-DCM or forced-CCM mode,
the timing is carefully adjusted to eliminate output voltage
excursions. When a phase is added, the current balance
between phases is quickly restored.
When commanded into 1-phase CCM operation according
to Table 2, both MOSFETs of Phase 2 will be off. The
controller will thus eliminate switching losses associated with
the unneeded channel.
VOUT AND VSOFT
Dynamic Operation
Figure 35 shows that the ISL6266A responds to changes in
VID command voltage by slewing to new voltages with a
dV/dt set by the SOFT capacitor and by the state of
DPRSLPVR. With CSOFT = 15nF and DPRSLPVR HIGH,
the output voltage will move at 2.8mV/s for large changes
in voltage. For DPRSLPVR LOW, the large signal dV/dt will
be 10mV/s. As the output voltage approaches the VID
command value, the dV/dt moderates to prevent overshoot.
10mV/s
-2.5mV/s
2.5mV/s
DPRSLPVR
VID#
Protection
The ISL6266A provides overcurrent, overvoltage,
undervoltage protection and over-temperature protection, as
shown in Table 3.
PROTECTION ACTIONS
FAULT RESET
Overcurrent fault
120s
Way-Overcurrent fault
<2s
Immediately
1ms
Undervoltage fault
(-300mV)
1ms
1ms
Over-temperature fault
(NTC <1.18V)
Immediately
N/A
20
FN6398.3
June 14, 2010
ISL6266, ISL6266A
The ISL6266A has a thermal throttling feature. If the voltage
on the NTC pin goes below the 1.2V over-temperature
threshold, the VR_TT# pin is pulled low indicating the need
for thermal throttling to the system oversight processor. No
other action is taken within the ISL6266A in response to
NTC pin voltage.
Power Monitor
For over-loads exceeding 2.5 times the set level, the PWM
outputs will immediately shut off and PGOOD goes low to
maximize protection due to hard shorts.
21
(EQ. 2)
(EQ. 3)
ISL6266 Features
The ISL6266 incorporates all the features previously listed
for the ISL6266A. However, the sleep state logic is slightly
altered (see Table 2). In addition to those differences, the
ISL6266 has been optimized to work with coupled-inductor
solutions. Due to mutual magnetic fields between the
individual phase windings of the coupled-inductor, the
effective per-phase inductance equals the leakage
inductance of the transformer. This can be very low (e.g.
90nH), which allows for faster channel current slew rates
and, consequently, an all-ceramic output capacitor bank can
be utilized. Additionally, the current ripple is lower than would
be produced with two discrete inductors of equivalent value
to the coupled-inductor leakage. This improves
coupled-inductor efficiency over discrete inductor solutions
for the same transient response.
In single phase operation, the active channel inductor will
continue to build a mutual field in the inactive channel inductor.
This field must be dissipated every cycle to maintain inductor
FN6398.3
June 14, 2010
ISL6266, ISL6266A
volt-second balance. The ISL6266 continues to turn on the
lower MOSFET for the inactive channel to deplete the induced
field with minimum power loss.
ISL6266, ISL6266A
ISS
I2
ERROR
AMPLIFIER
+
SOFT
+
CSOFT
VREF
22
(EQ. 4)
(EQ. 6)
Selecting RBIAS
To properly bias the ISL6266A, a reference current is
established by placing a 147k, 1% tolerance resistor from
the RBIAS pin to ground. This will provide a highly accurate
10A current source from which the OCSET reference
current can be derived.
Care should be taken in layout that the resistor is placed
very close to the RBIAS pin and that a good quality signal
ground is connected to the opposite side of the RBIAS
resistor. Do not connect any other components to this pin as
this would negatively impact performance. Capacitance on
this pin would create instabilities and should be avoided.
FN6398.3
June 14, 2010
ISL6266, ISL6266A
ISEN1
ISEN2
ISEN2
ISEN1
10A
OCSET
ROCSET
VO'
IPHASE1
OC
VSUM
+
DROOP
INTERNAL TO
ISL6266
+
+
VSUM
DFB
Rdrp2
DCR
RL1
Cn
IPHASE2
RPAR
ISEN1
L2
RS
VSUM
VSEN
C L1
RO1
RL2
VO'
DCR
+
Vdcr2
VOUT
RO2
RNTC
VO'
VDIFF
Vdcr1
-
RSERIES
+
1 RTN
RS
VSUM
DROOP
+
1 -
L1
ISEN2
Rdrp1
VO'
CBULK
CL2
VO'
82nF
10
Ropn1
0.018F
0.018F
VCC_SENSE
VSS_SENSE
ROPN2
ESR
TO VOUT
TO PROCESSOR
SOCKET KELVIN
CONNECTIONS
FIGURE 37. SIMPLIFIED SCHEMATIC FOR DROOP AND DIE SENSING WITH INDUCTOR DCR CURRENT SENSING
23
(EQ. 7)
FN6398.3
June 14, 2010
ISL6266, ISL6266A
For 300kHz operation, RFSET is suggested to be 9.53k. In
discontinuous conduction mode (DCM), the ISL6266A runs
in period stretching mode. The switching frequency is
dependent on the load current level. In general, lighter loads
will produce lower switching frequencies. Therefore,
switching loss is greatly reduced for light load operation,
which conserves battery power in portable applications.
6A
VR_TT#
SW1
NTC
+
VNTC
-
Rs
1.24V
LOGIC_0
T2
SW2
T1
T (C)
1
1
b -------------------- -----------------------
T + 273 To + 273
(EQ. 8)
RNTC
VR_TT#
LOGIC_1
54A
1.24V
R NTC ( T 2 ) + R S = ---------------- = 22.96k
54A
(EQ. 9)
(EQ. 10)
1.20V
INTERNAL TO
ISL6266
(EQ. 11)
2.96k e
R NTCTo = -----------------------------------------------------------------------------e
1
b -----------------------
T 2 + 273
1
b -----------------------
T 1 + 273
(EQ. 12)
(EQ. 13)
FN6398.3
June 14, 2010
ISL6266, ISL6266A
(EQ. 14)
= 2.96k + R NTC_T
(EQ. 15)
1
T 2_actual = ----------------------------------------------------------------------------------- 273
R NTC_T
1
--- ln -------------------------2 + 1 ( 273 + To )
b R NTCTo
(EQ. 18)
(EQ. 16)
DESIGN EXAMPLE
The process of compensation for DCR resistance variation
to achieve the desired load line droop has several steps and
may be iterative.
10A
OCSET
OC
RS
RS EQV = -------2
VSUM
+
DROOP
-
INTERNAL TO
ISL6266
VDIFF
DCR
Vdcr EQV = I OUT ------------2
DROOP
+
1 -
+
1 -
RTN VSEN
VO'
Cn
Rdrp1
DFB
Rdrp2
VSUM
+
-
VN
-
VO'
RO
RO EQV = --------2
FIGURE 40. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DCR SENSING
25
FN6398.3
June 14, 2010
ISL6266, ISL6266A
RO is typically 1 to 10. This resistor is used to tie the
outputs of all channels together and thus create a summed
average of the local CORE voltage output. RS is determined
through an understanding of both the DC and transient load
currents. This value will be covered in the next section.
However, it is important to keep in mind that the outputs of
each of these RS resistors are tied together to create the
VSUM voltage node. With both the outputs of RO and RS
tied together, the simplified model for the droop circuit can
be derived. This is presented in Figure 40.
Figure 40 shows the simplified model of the droop circuitry.
Essentially, one resistor can replace the RO resistors of each
phase and one RS resistor can replace the RS resistors of
each phase. The total DCR drop due to load current can be
replaced by a DC source, the value of which is given by
Equation 19:
I OUT DCR
V DCR_EQU = --------------------------------2
(EQ. 19)
(EQ. 20)
(EQ. 25)
(EQ. 26)
(EQ. 27)
(EQ. 28)
Rn ( T )
G 1 ( T ) = ------------------------------------------R n ( T ) + RS EQV
(EQ. 21)
2 R droop
R drp2 = --------------------------------------- 1 1k 5.82k
0.0008 0.769
(EQ. 22)
26
(EQ. 24)
(EQ. 29)
FN6398.3
June 14, 2010
ISL6266, ISL6266A
To see whether the NTC has compensated the temperature
change of the DCR, the user can apply full load current and
wait for the thermal steady state and see how much the
output voltage will deviate from the initial voltage reading. A
good compensation can limit the drift to 2mV. If the output
voltage is decreasing with temperature increase, the ratio
between the NTC thermistor value and the rest of the
resistor divider network has to be increased. The user is
strongly encouraged to use the evaluation board values and
layout to minimize engineering time.
The 2.1mV/A load line should be adjusted by Rdrp2 based
on maximum current. The droop gain might vary slightly
between small steps (e.g. 10A). For example, if the max
current is 40A and the load line 2.1m, the user load the
converter to 40A and look for 84mV of droop. If the droop
voltage is less than 84mV (e.g. 80mV) the new value will be
calculated by Equation 30:
84mV
R drp2 new = ---------------- ( R drp1 + R drp2 ) R drp1
80mV
(EQ. 30)
2.25
2.20
2.15
2.10
2.05
0
20
40
60
80
100
(EQ. 31)
(EQ. 32)
(EQ. 33)
FN6398.3
June 14, 2010
ISL6266, ISL6266A
a mathematical calculation file available to the user. The
power stage parameters such as L and Cs are needed as
the input to calculate the compensation component values.
Attention must be paid to the input resistor to the FB pin. Too
high of a resistor will cause an error to the output voltage
regulation because of bias current flowing in the FB pin. It is
better to keep this resistor below 3k when using this file.
28
(EQ. 34)
(EQ. 35)
(EQ. 36)
FN6398.3
June 14, 2010
ISL6266, ISL6266A
10A
OCSET
+Voc -Roc
OC
RS
VSUM
+
DROOP
-
INTERNAL TO
ISL6266A
VDIFF
DFB
+
DROOP
+
1 -
Rsense
Vrsense EQV = I OUT ----------------------2
+
-
RTN VSEN
VO'
VN
Cn
Rdrp1
RS
= -------2
VSUM
Rdrp2
EQV
RO
VO'
EQV
RO
= --------2
FIGURE 42. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DISCRETE RESISTOR SENSING
VOC. Once the droop voltage is greater than VOC, the PWM
drives will turn off and PGOOD will go low.
The selection of ROC is given in Equation 37. Assuming an
overcurrent trip level, IOC, of 55A, and knowing from the Intel
specification of the load line slope, Rdroop = 0.0021 (V/A),
ROC is calculated by Equation 37.
I OC R droop
55 0.0021
R OC = ----------------------------------- = ------------------------------ = 11.5k
6
10A
10 10
(EQ. 37)
Note, if the droop load line slope is not -0.0021 (V/A) in the
application, the overcurrent setpoint will differ from
predicted. In addition, due to the saturation limitations of the
DROOP amplifier, there is a maximum way-overcurrent
(WOC) set point for each VID code. The maximum OC set
point that will ensure WOC can be reached is expressed in
Equation 38:
1.75 VID
I OC = -------------------------------------2.5 R DROOP
(EQ. 38)
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Intersil Corporations quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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29
FN6398.3
June 14, 2010
ISL6266, ISL6266A
44X 0.50
37
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
1
7.00
36
4. 30 0 . 15
12
25
(4X)
0.15
13
24
0.10 M C A B
48X 0 . 40 0 . 1
TOP VIEW
( 6 . 80 TYP )
(
0.10 C
BASE PLANE
0 . 90 0 . 1
4 . 30 )
SEATING PLANE
0.08 C
SIDE VIEW
( 44X 0 . 5 )
0 . 2 REF
( 48X 0 . 23 )
( 48X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
30
FN6398.3
June 14, 2010