Latches & Flip-Flops

F4 : Latches, Flip-Flops, Data buses &

Resolved functions

SR-Latch

Gated SR-Latch

Q+ Qn+

SR =
Q Qn

00

01

11

10

00

11 01

00

10

01

01 01

00

00

11

00 00

00

00

10

10 00

00

10

C
Q
S

D-latch

Master-Slave Flipflop

Clk

C
Q

D
Clk

D
Clk

Edge-triggered Flipflop

Latches
Mux:

process(a,b,sel)

begin

if (sel=1) then

Clk

q<=a;

else
q<=b;

Sel

end if;
end process;

Latches
Latch:

process(D,clk)

Flip-flop
D

(a)

begin
if (clk=1) then

q<=D;
end if;

Clk

end process;

Clk

Clk

(Sel)

Flip-flop
process(clk)

-- synthesis might complain that d is not listed

Signal Attributes
signal s:bit;
s

begin
if (clk=1) and clkevent then
q<=d;
end if;
end process;

sevent

sactive

sstable(5 ns) =
squiet(5 ns) =
stransaction =

now

Signal Attributes

D-latch with asynchronous reset

Latch:

signal s:bit;

process(D,reset,clk)
sdelayed(5 ns)

slast_event

slast_active

slast_value

begin

if (reset=0) then
0

q<=0;
elsif (clk=1) then

Reset

q<=D;
Clk

end if;
end process;

D-latch with synchronous reset

D-flipflop with asynchronous reset

Latch:
process(D,reset,clk)

D
Reset

begin
if (clk=1) then

if (reset=0) then

q<=0;

else

Reset

q<=D;
end if;

Clk

Clk

end if;

Clk

end process;

D-flipflop with synchronous reset

Synchronous reset
process(clk)

D
Reset

begin
q

Clk

-- synthesis might complain that neither d nor

-- reset is listed

Clk

if (clk=1) and clkevent then

if (reset=1) then
q<=0;
else
q<= D;
end if;
end if;
end process;

Asynchronous reset
process(clk,reset)

-- synthesis might complain that d is not

-- listed

begin

Registers
D(0 to N-1)

Q(0 to N-1)

Clk
if (reset=1) then
q<=0;
elsif (clk=1) and clkevent then
q<= D;
end if;

end process;

Structural description
USE work.all;
ENTITY d_register IS
generic( N:integer
);
port(
D:IN bit_vector(N-1 DOWNTO 0);
clk:IN bit;
Q:OUT bit_vector(N-1 DOWNTO 0));
END d_register;
ARCHITECTURE structure OF d_register IS
COMPONENT dflipflop -- IS is allowed in VHDL93
Not very efficient!!!
port(
D:IN bit;
clk:IN bit;
Q:OUT bit);
END COMPONENT; -- COMPONENT keyword may be skipped in VHDL93
BEGIN
U0:FOR i IN 0 TO N-1 GENERATE
R0:dflipflop PORT MAP (D(i),clk,Q(i));
END GENERATE ;
END d_register;

Sequential description (RTL-style)

ARCHITECTURE behave OF d_register IS
BEGIN

VERY efficient!!!
PROCESS(clk)
BEGIN
IF clkEVENT AND (clk=1) THEN
q<=D;
END IF;
END PROCESS;

The datatype decides the size

END behave;

Data buses
En(0 to N-1)

Databuses & Resolution

Functions

D(0 to N-1)

Clk

How do we model buswires?

Bus Resolution in VHDL

Bus Resolution in VHDL (ctd.)

VHDL does not allow multiple concurrent signal assignments to the

same signal
Multiple sequential signal assignments are allowed

If a signal has a bus resolution function associated with it, then the
signal may have multiple drivers
USE WORK.my_bus_resolution.ALL;

-- this code will generate an error

ENTITY bus IS
PORT (a, b, c : IN bit; z : OUT bit);
END bus;

ENTITY bus IS
PORT (a, b, c : IN bit; z : OUT bit);
END bus;

ARCHITECTURE smoke_generator OF bus IS

SIGNAL circuit_node : bit;
BEGIN
circuit_node <= a;
circuit_node <= b;
circuit_node <= c;
z <= circuit_node;
END smoke_generator;

ARCHITECTURE fixed OF bus IS

SIGNAL circuit_node : wired_and bit;
BEGIN
circuit_node <= a;
circuit_node <= b;
circuit_node <= c;
z <= circuit_node;
END fixed;

Signal Resolution and Buses

Execution phase

Bus Resolution Functions

Signal update phase

VHDL uses bus resolution functions to resolve the final value of

multiple signal assignments

Transaction queue

OR

Bus Resolution Function

Resolved
signal

AND

Bus resolution effects on Port Modes

The port mode of the interface describes the direction of the data
flow with respect to the component
The five types of data flow are
In - data flows in this port and can only be read
Out - data flows out of this port and can only be written to
Buffer - data flow can be in either direction but only one source is
allowed at any one time
Inout - data flow can be in either direction with any number of sources
allowed (implies a bus)
Linkage - data flow direction is unknown

FUNCTION wired_and (drivers : bit_vector) RETURN bit IS

VARIABLE accumulate : bit := '1';
BEGIN
FOR i IN drivers'RANGE LOOP
accumulate := accumulate AND drivers(i);
END LOOP;
RETURN accumulate;
END wired_and;

Bus resolution functions may be user defined or

called from a package

IEEE standard 1164

type std_ulogic is (U, X, 0, 1, Z, W, L, H, -);
U - Uninitialized
X - Forcing Unknown
0 - Forcing Zero
1 - Forcing One
Z - High Impedance
W - Weak Unknown
L - Weak Zero
H - Weak One
- - Dont Care

std_logic

std_logic Resolved function

Function resolved(input:std_logic_vector) return std_logic is
constant resolve_table:std_logic_LUT:=();

type std_logic is resolved std_ulogic;

variable res:std_logic:=Z;
begin

type std_logic_vector is array(integer range <>) of std_logic;

for i in inputrange loop

res:=resolve_table(res,input(i));

type std_logic_LUT is array(std_logic,std_logic) of std_logic;

end loop;
return res;
end resolved;

std_logic Resolved function

How accurate is the Resolution

model?

Function resolved(input:std_logic_vector) return std_logic is

constant resolve_table:std_logic_LUT:=(
-- U,X, 0, 1, Z,W,L,H, -
VDD

( U,U,U,U,U,U,U,U,U), -- U
( U,X,X,X,X,X, X,X,-), -- X

VL

( U,X,X, 1, 1,1, 1, 1, -), -- 1

N connected Units

VOH

( U,X, 0,X, 0,0, 0, 0, -), -- 0

VL

VSS

( U,X, 0, 1, Z,W,L,H,-), -- Z
( U,X, 0, 1,W,W,W,W,-), -- W
( U,X, 0, 1,L, W,L,W,-), -- L
( U,X, 0, 1,H,W,W,H,-), -- H
( U, -, -, -, -, -, -, -, -)); -- -

Voltage levels

Representation of 1s and 0s
VOH = 3.3V
VIH = 2.4V

VOH

VH

VOL

VL

H, 1
W, X

VIL = 0.8V

Noise Margin

TTL

VH>2.4 V, VL<0.8 V,

CMOS

VH>90% of VDD -VSS,

VOL = 0.4V

Ri

VOH=3.3 V, VOL=0.4V
VL<10% of VDD -VSS

L, 0

~10 Mohms => Z

Vi

Ri =

~10 kOhms => L, H, W

~10 Ohms => 0, 1, X

Physical representation of std_ulogic

Vres
Rres

<0.8V
<10%

>0.8V,<2.4V
>10%, <90%

>2.4V
>90%

Equivalent Two-pole of output stage

- TTL
- CMOS (% of VDD-VSS)

VDD
VL

<1kOhm

VOH

V=VOH
R=ROH

VL
>1kOhm, <1MOhm

>1 MOhm (TTL)

>1 GOhm (CMOS)

VSS

Equivalent Two-pole of output stage

0 - Forcing Zero
R
VDD

VH
VH

VDD

VOL

VH

VL
VOL

V=VOL
R=ROL

VH

VH
VSS

VSS
V<VL
R~10 Ohms

H - Weak High (Open Drain)

Z - High Impedance
R

VH

VDD

VOH
VL

R
VDD

VH

V=?

VL

VH

VL

V=?
VL

VSS
VDD

0
VH<V
R~10 kOhms

VSS

0
V=?
R~10 MOhms (TTL)
10 GOhms (CMOS)

Two-pole equivalent

Example: X - Forcing Unknown

Vres

R
VH

R1

R2

VL

V1

V2

Rres = R1||R2

VL<V<VH
R~10 Ohms

Vres = V1*R2/(R1+R2)+V2*R1/(R1+R2)

X - Forcing Unknown

X - Forcing Unknown
Vres
VDD

VDD

VL

VDD

VH
VOH

VSS

VSS

VH

R2

V1

V=?

VL
VOL

R1

V2

VH
VSS

VL

V1 = VDD = 5 (V), V2 = VSS = 0 (V), R1 = R2 = RON = 10 (Ohm)

V = (VDD-VSS)*RON/(RON+RON) = VDD/2 = 2.5 (V)
R = RON//RON = RON/2 = 5 (Ohm)

A Real Resolution Algorithm...

Final Result table

Vres = 0 (V), Rres = 1 (GOhm)

Vres := Vi *Rres/(Ri+Rres)+Vres*Ri/(Ri+Rres)

Vres

<0.8V
<10%

>0.8V,<2.4V
>10%, <90%

>2.4V
>90%

<1kOhm

>1kOhm, <1MOhm

>1 MOhm (TTL)

>1 GOhm (CMOS)

Rres

Rres := Ri*Rres/(Ri+Rres)
Final check:
if Rres> 1 (MOhm) then return Z;
elsif Vres> 0.9*VDD then
if Rres> 1 (kOhm) then return H; else return 1; end if;
elsif Vres> 0.1*VDD then
if Rres> 1 (kOhm) then return W; else return X; end if;
else
if Rres> 1 (kOhm) then return L; else return 0; end if;
end if;

- TTL
- CMOS (% of VDD-VSS)

Example - Resolution functions

How many Open Drains (H) can be connected to
a Forcing Zero (0) before the Forcing Zero goes
into the unknown region?

Example: D-Flipflop with Tri-state

enable
En
Q

How many Open Source (L) can be connected to

a Forcing One (1) before the Forcing One goes
into the unknown region?
Clk

Example: I2C (CAN)-bus protocol

Appendix

Single wire used

both for arbitration
and communication
in any direction!!!

Dataflow modeling

Concurrent statements:

Dataflow Modeling of Tri-state

functionality

U0: q0 <= a and b ;

U1: q1 <= f(a,b);
U2: and_gate port map(q0,q1,q2);

Concurrent If-statements

Concurrent Case-statement

q <= 1 when sel=00

with sel select

else d(0) when sel=01

q<=1 when 00,

else d(2) when sel=10

d(0) when 01,

else 0;

d(2) when 10,

0 when others;

Data flow Modeling of Latches &

Flipflops

Tristate Modeling - Null Transaction

-- D-latch
q<=D when clk=1 else q;

How can a driver be disconnected (i.e., not influencing the output at

all)?

-- D-flipflop

Example

Use the null waveform element

q <= D when clkevent and (clk=1) else q;

bus_out <= null after 17 ns;

q <= D when (NOT(clkSTABLE) AND (clk=1) AND

(clkLAST_VALUE=0)) else q;

Bus & Register construct

What happens if all drivers of a resolved signal are disconnected?
Use register kind in signal declaration to keep most recently determined
value
Use bus kind in signal declaration if resolution function must determine
the value

Example
signal t : wired_bus bus;
signal u : bit register;

Blocks and Guards

Blocks partition the concurrent statements in an architecture such
that conditional activities unique to each block can occur
A guarded signal assignment statement generates a value only if the
block guard expression is true. If false, the assignment is
disconnected
Example
ARCHITECTURE guarded_assignments OF n_1_mux IS
BEGIN
bi: FOR j IN irange GENERATE
bj: BLOCK (s(j)=1 or s(j)=Z)
BEGIN
x <= guarded i(j);
END BLOCK;
END GENERATE;
END guarded_assignments

The Implicit Guard-signal

Modeling Latches using Guarded

Dataflow Style

The Guard can also be used as an implicit signal

Example

ARCHITECTURE guarded_assignments OF n_1_regs IS

BEGIN
bi: FOR j IN regsrange GENERATE
bj: BLOCK (enable=1 and read=1)
BEGIN
x <= regs(j) when guard else ZZZZZZZZ;
END BLOCK;
END GENERATE;
END guarded_assignments;

-- Latch, dataflow style with synchronous reset

U0 : BLOCK(clk=1)
signal q_temp:bit;
BEGIN
q_temp<=guarded 0 when (reset=1) else d;
q<=q_temp;
qbar<=not(q_temp);
END BLOCK;

Modeling Flipflops using Guarded

Dataflow Style

Disconnect statement
entity tristate is

-- Flipflop, dataflow style with asynchronous reset

U0:BLOCK((NOT(clkSTABLE) AND (clk=1) AND (clkLAST_VALUE=0))
OR reset=1)
signal q_temp:bit;
BEGIN
q_temp<=guarded 0 when (reset=1) else d;
q<=q_temp;
qbar<=not(q_temp);
END BLOCK;

port(a0,a1,a2,a3,en:IN bit;
q0,q1,q2,q3:OUT bit);
end tristate;
architecture data_flow of tristate is
disconnect q0:bit after 1 ns;
disconnect others:bit after 2 ns;
-- disconnect all:bit after 2 ns;
begin
U0:block(en=1)
begin
q0 <= guarded a;
...
end block;
end data_flow;

Block syntax

block_label: block [ (Guard_expression)] [ is ]

[ generic ( generic_interface_list );
[ generic map ( generic_association_list ); ] ]
[ port ( port_interface_list );
[ port map ( port_association_list ); ] ]
{ block_declarative_item }
begin
{ concurrent_statements }
end block [ block_label ] ;

Electrical Equivalents to
std_logic

X - Forcing Unknown

0 - Forcing Zero
R

VDD

VH

R
VDD

VH

VL
V
VL

VH
V=?

VOL
V

VL

VH
VSS

VL<V<VH
R~10 Ohms

VH
VSS

V<VL
R~10 Ohms

1 - Forcing One

Z - High Impedance
R

VH

VDD
V

VOH
VL

R
VDD

VH

VH

VL
V=?

V=?
VL

VL

VL
VSS

VSS

0
VH<V
R~10 Ohms

V=?

R~10 MOhms (TTL)

10 GOhms (CMOS)

W - Weak Unknown

L - Weak Zero (Open Source)

R

VDD

VH

R
VDD

VH
VH

V=?

VL

VOL
VL

VSS

R~10 kOhms

VSS
VDD

0
VL<V<VH

0
V<VL
R~10 kOhms

VSS

L
VSS

H - Weak High (Open Drain)

R
VH

VDD
V
VOH

VL

VL
VSS
VDD

0
VH<V
R~10 kOhms