Introduction

CurrentIssueswith Test
Fault Models
Introduction Behavioral Level / Gate Level (RTL) / Component Level
Types of Fault Models examples detailed
(DC) Stuck-at
Opens
Bridging
Functional
Toggle
Parametric
(AC) Transition Delay
Path Delay
Automatic Test Pattern Generation
What is ATPG?
Structural Test
Overview of the ATPG process
Targets Cone of Logic
Injecting Faults
Generating Vectors examples using various Fault Models
D and Dbar Notation
Sensitive Paths
Reconvergent Fanouts
Reconvergent Inputs
Student Exercise determine pathways and conditions
ATPG vector validation
Fault Coverage / Fault Grading
Benefits of ATPG
Design For Test (DFT) Introduction
Functional vs. Structural Test
Phases of Test
Vectors Functional / Application / Parallel / Broadside
Vectors Structural / Scan
Ad-Hoc vs. Structured DFT
DFT methods
Full Scan vs. Partial Scan
DFT benefits
DC Scan

Implementing Logic Scan

Flops Mux-D, LSSD, Two Clock Scan Flops
ATPG and Scan Logic
Single, Multiple Chains (example data)
Scan Terminology
Scan Timing Diagrams detailed waveforms, timing values, timing sequences
Shared Scan interface functions
Shifting Scan Data whats important, ways shifting can fail
Testing Scan Logic Scan integrity tests
Data Alignment Issues examples, keeping it correct
Why DC Scan Tests Fail
Scan Design / Test Data/ Test Application/ Device
AC Scan
Why perform AC Scan?
High Frequency AC Scan
Delay Fault Models and AC Scan
Delay Path Distribution
Path Delay Example Ideal Case
Transition Delay Example
Dynamic Hazards
Robust Delay Rules, Tests examples of good/bad
AC Scan Terminology Controlling/Non-controlling/Enabling/On-Path/Off-Path
Delay Test Examples
Strategies for Delay Tests
How AC Scan works
Launch On Shift (L-O-S)
LOS detailed timing
LOS test generation and associated issues
Functional Launch (Launch on Capture LOC)
Functional Launch detailed timing
Functional Launch test generation and associated issues
AC Scan Debug
Using AC Scan to make Timing Measurements
Low Voltage Stress Effects
Clocks and Phase Lock Loops (PLL)
PLL basics
Chop Clocks
Using Chop Clocks to generate Shift/Launch/Capture sequences
Boundary Scan 1149.1 IEEE Standard JTAG
Introduction to Boundary Scan and the JTAG team
Why it was needed (PCB test requirements)
The IEEE 1149.1 Standard whats defined
The Boundary Scan Register functions

TAP Controller and dedicated pins

TAP 16 State Machine
TAP Operations
Boundary Scan Instructions
Instruction Behavior
Boundary Scan Register hardware
Bypass Register
Identification Register
BS Timing Instruction Load
BS Timing Data Scan
Using BS for parametric tests VOH/VOL/VIL/VIH/IOZL/IOZH
Another look at In-Circuit Test (PCB test addressed)

Built-In Self Test (BIST)

BIST defined
BIST applications
Memory BIST Architecture, Algorithms
Logic BIST Architecture
Pseudo-Random-Pattern-Generation (PRPG)
Linear Feedback Shift Register (LFSR)
LFSR designs: Type 1 & 2, Pattern Sequences
Seed Codes, Polynomials
Correlated Data Issues
Phase Shifters, Spreaders, Broadcasters
Output Compression Multiple Input Shift Registers (MISR)
Output Signature
Logic BIST Test Sequence
BIST Clocking
IO BIST Reduced Pin Count Testing (RPCT)
Why IO BIST
Reduced Pin Count Testing, whats involved
IO BIST pin circuitry
No Contact Shorts Test
Basic IO Functional Test (VOL/VOH/VIL/VIH) no contact
IIL/IIH No Contact Leakage Tests
IO Loop Back Test
DFT and ATE systems
ATE system overview types of test systems
Uses for each type of system
Introduction to DFT ATE
What DFT ATE is designed for (capabilities/limitations)

Faults

Scan
Debug

IDDQ
MBIST

IEEE

compression techniques, Serdes,LNC,Shadow

S@,transition
Clocking,LOC,LOS,LO pipelineS
CG gating,latch
Low power
Coverage improvement
Pattern count reduction
broken chain
Simulation
ATE fails

JTAG
Boundary Scan
IEE1500 WBR TAM

clock grouping