polling and interrupts

Interrupts and Polling

Consider a computer that is playing back an mpeg file in say media player. You click some icon
on the desktop and the computer responds immediately. How does this happen? The computer
had no way of knowing when this event would occur, but yet it dealt with it.
A computer receives input from a number of different sources. Characters keyed in on the
keyboard, the click of a mouse, data from a scanner. The arrival of this type of input is not
necessarily expected at any particular time and the computer has to have a way of detecting it.
There are two ways that this can happen, known as polling and interrupts. Both of these
techniques allow the processor to deal with events that can happen at any time and that are not
related to the process it is currently running.

Polling
The first method is polling. Here the processor continuously polls or tests every device in turn as
to whether it requires attention (e.g. has data to be transferred). The polling is carried out by a
polling program that shares processing time with the currently running task. A device indicates it
requires attention by setting a bit in its device status register.
Most of the time, devices will not require attention and when one does it will have to wait until it
is next interrogated by the polling program. This is an inefficient method and much of the
processors time is wasted on unnecessary polls.
Compare this method to a teacher continually asking every student in a class, one after another,
if they need help. Obviously the more efficient method would be for a student to inform the
teacher whenever they require assistance.

Interrupts
An interrupt is a signal to the microprocessor from a device that requires attention. The
microprocessor will respond by setting aside execution of its current task and deal with the
interrupting device. When the interrupting device has been dealt with, the microprocessor
continues with its original task as if it had never been interrupted.
A simple enough idea it happens to people all the time, such as receiving a phone call when
you are doing some work. You deal with the interruption and then resume with your work from

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where you left off. The concept is identical with computers however; implementation is not quite
so straightforward.
In order to be able to continue from where it was before the interrupt, the current state of the
microprocessor must be saved. This is achieved by saving the contents of all of its internal
registers, both general purpose and special registers, to an area of memory called the stack.
The registers will then be reinstated from the stack on completion of the interrupt call, allowing
the microprocessor to resume its original task.
Any device that generates an interrupt signal must also be accompanied by code that will be run
by the microprocessor instructing it how to tend to the device's needs. Such code is referred to
as an interrupt handler or interrupt service routine (isr) and is a small piece of software
executed in response to a particular interrupt
Every device that is capable of generating an interrupt signal will have its own particular isr.
These interrupt service routines are essential for the operation of a computer system and are
loaded into memory at boot-up along with the kernel.
To summarise so far, whenever an interrupt signal is received, the microprocessor will respond
by
completing its current instruction,
transferring the contents of important registers to the stack,
deal with the interrupting device, by executing its interrupt service routine
restore registers from the stack and resume execution of the task which was interrupted.
Although up to this point we have considered interrupts that are generated by hardware devices,
they can also be generated by software.
Software driven interrupts are generated from within a program that is currently running, and
are triggered by the int opcode. Software interrupts are simply subroutine calls that allow a
program to access certain low level services that are provided by the operating system. For
example the int 21h interrupt (where 21 is a hex value that identifies the particular interrupt)
allows access to certain ms-dos services.
Hardware driven interrupts are signalled from a device to the microprocessor by setting high
(a 1 signal) an interrupt line in the control bus. Microprocessors are normally equipped with two
hardware interrupt inputs: non maskable interrupt (NMI) and interrupt request (INTR).
A non maskable interrupt is generated by an event which must be dealt with immediately. The
microprocessor cannot ignore an NMI. The NMI line is exclusively used for events that will have
tragic consequences for the computer operation. Typically an NMI is due to an interruption of

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the power supply, a memory fault or pressing the reset button. By taking immediate action the
microprocessor may be able to save some user data.
An interrupt request may be generated by a number of different devices all of which are
connected to the single INTR control line. As the name suggests this interrupt is a request for
attention which may or may not be granted. The microprocessor will ignore all interrupt requests
if it is already dealing with an interrupt. No further interrupts (other than a NMI) will be accepted
until the current interrupt has been serviced.
A third line INTA (or ACK) is for output and is used by the microprocessor to acknowledge its
reception of an interrupt signal to a device.

Identifying the Source of an Interrupt

The microprocessor only has one interrupt request (INTR) line which is triggered by a 1 signal.
All hardware devices use this line to generate an interrupt request. When the INTR line goes
high the microprocessor does not have enough information to determine which of the possible
interrupting devices is requesting attention. The device must be identified in order for the
microprocessor to run the appropriate service routine.
Two methods are available to determine the interrupting device.
Polled interrupts On receiving an interrupt request the microprocessor will execute a routine
causing it to poll each of the devices in turn. Devices have a status register containing one or
more interrupt request bits. If a device caused the interrupt, its interrupt flag bit will be set. The
appropriate service routine will then be selected and the device serviced. Polling can be very
inefficient if there are many devices capable of causing an interrupt. This method uses only
software methods to identify an interrupting device.
Vectored interrupts This is the method used in modern computers. It is sometimes referred to
as hardware identification since additional hardware is required.

Vectored Interrupts
The interrupt vector table is used to point to the addresses of interrupt service routines for
both hardware and software interrupts. It is located in the first 1024 bytes of memory, and
contains 256 different interrupt vectors, each of which is the address of an interrupt service
routine. That is, each vector is 4 bytes in length and is the start address of an interrupt service
routine. See table 1.

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Each vector is identified by an interrupt number from 0 to 255 and provides the processor with
the means of addressing the appropriate interrupt handler. For example, if an interrupt is
identified as having interrupt number 4 then addresses 10H to 17H contain the start address of
its interrupt service routine. A vector address is determined by multiplying its vector number by
4 (e.g. 4 * 4 = 16 or 10H). This gives the beginning location of its 4 byte interrupt vector.

Vector

Address (hex)

Function

Number
0

0000 -

0003

divide error

0004 -

0007

single step

0008 -

000B

NMI

000C -

000F

breakpoint

0010 -

0013

overflow

5 - 31

0014 -

00FF

(reserved)

32

0100 -

0103

IRQ0

33

0104 -

0107

IRQ1

34

0108 -

010B

IRQ2

Table 1. Interrupt vector table (showing first 35 interrupt vectors) as used for the Intel
x86 range of microprocessors. The first 32 vectors are reserved for processor
generated interrupts (or exceptions) and the remainder are available for the user.

This is precisely how a software generated interrupt is handled: its operand is the interrupt
number and this provides access to the corresponding interrupt vector in the table. For example,
the software interrupt int 13H has interrupt number 13H (19 in decimal) and its entry in the
vector table are the 4 bytes starting at location 4CH (13H * 4). So, no problem here. However
hardware interrupts are a bit more awkward.
The number of interrupt lines available to devices are extended by the use of external dedicated
chips known as programmable interrupt controllers. A PIC has 8 INTR input lines, labelled as

PIC

microprocessor

ACK

ACK in

IRQ

IRQ out

interrupt
request
lines
from
devices

Data bus

Figure 1
The connection of a single programmable
interrupt controller to the microprocessor and devices.

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IRQ 0 to IRQ 7, each of which is connected to the interrupt request line of a device. When the
PIC receives an interrupt signal on an input line, it will, in turn, send the request to the
microprocessor INTR input. On receiving an acknowledgement from the microprocessor the PIC
will identify the device which requested an interrupt by depositing its interrupt number on the
data bus. The microprocessor will use the interrupt number to access the appropriate isr from
the vector table.
In the PC, two PICs are used to increase the number of available interrupt lines from 8 to 15.
This is achieved by connecting the INTR out pin of the second PIC to the IRQ 2 input of the first
PIC.
Prioritised interrupts With the large number of devices in a system capable of generating
interrupts, it is possible that two interrupts may be received simultaneously (this is unlikely), or
an interrupt is received while another interrupt service routine is currently being executed by the
microprocessor. The interrupt request will only be granted if it is of a higher priority level than
the interrupt currently being serviced. Otherwise the microprocessor will ignore it.
The PIC interrupt request lines are prioritised, that is, they are divided into levels and to each
level there is assigned a priority number (0 is the highest). This is implemented via various
programmable registers within the PIC. The various priority levels for the PC are summarised in
table 5.2. When an interrupt request is received the PIC will interrupt the microprocessor only if
the current interrupt is of higher priority than any other interrupts currently being serviced. This
will cause the processor to service the current interrupt request. A PIC relieves the
microprocessor of the responsibility of receiving and accepting interrupt requests. Any request
from the PIC to the microprocessor via its IRQ line will be serviced.

interrupt

priority

number

level

description

division by 0

overflow

software

software INT

NMI

hardware

(IRQ)

debugging

Table 2. Priority levels for interrupts in the PC.

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