CDX-4180

SERVICE MANUAL

US Model
Canadian Model
E Model

SPECIFICATIONS
AUDIO POWER SPECIFICATIONS (US Model)
POWER OUTPUT AND TOTAL HARMONIC DISTORTION
17 watts per channel minimum continuous average power into
4 ohms, 4 channels driven from 20 Hz to 20 kHz with no more than
1% total harmonic distortion.

Model Name Using Similar Mechanism

NEW

CD Drive Mechanism Type

MG-363X-121

Optical Pick-up Name

KSS-521A

Other Specifications
CD player section
System

Compact disc digital audio

system
90 dB
10 - 20,000 Hz
Below measurable limit

AM
Tuning range

US, Canadian model:

530 - 1,710 kHz
E model:
AM tuning interval:
9 kHz/10 kHz switchable
531 - 1,602 kHz
(at 9 kHz step)
530 - 1,710 kHz
(at 10 kHz step)
External antenna connector
10.71 MHz/450 kHz
30 V

Signal-to-noise ratio
Frequency response
Wow and flutter
Laser Diode Properties
Material
GaAlAs
Wavelength
780 nm
Emission Duration
Continuous
Laser output power
Less than 44.6 W*
* This output is the value measured at a distance
of 200 mm from the objective lens surface on
the Optical Pick- up Block.

Antenna terminal
Intermediate frequency
Sensitivity

Tuner section

Power amplifier section

FM
Tuning range

Antenna terminal
Intermediate frequency
Usable sensitivity
Selectivity
Signal-to-noise ratio

Outputs
US, Canadian model:
87.5 - 107.9 MHz
E model:
FM tuning interval:
50 kHz/200 kHz switchable
87.5 - 108.0 MHz
(at 50 kHz step)
87.5 - 107.9 MHz
(at 200 kHz step)
External antenna connector
10.7 MHz
8 dBf
75 dB at 400 kHz
65 dB (stereo),
68 dB (mono)

Speaker impedance
Maximum power output

Speaker outputs
(sure seal connectors)
4 - 8 ohms
40 W 4 (at 4 ohms)

Continued on next page

Harmonic distortion at 1 kHz

Separation
Frequency response
Capture ratio

0.5% (stereo),
0.3% (mono)
35 dB at 1 kHz
30 - 15,000 Hz
2 dB

FM/AM COMPACT DISC PLAYER

MICROFILM

SECTION 4
DIAGRAMS
4-1. IC PIN DESCRIPTION
IC801 PD17705GC-526-3B9 (SYSTEM CONTROL)
Pin No.
Pin Name
I/O
1
SIRCS
I
SIRCS input (A/D)

Pin Description

2
3

IN-SW
D-SW

I
I

CD mechanism position detection

CD mechanism position detection

4
5

SELF-SW
L-SW

I
I

CD mechanism position detection

LIMIT switch

6
7

LM-EJ
LM-LOD

O
O

Loading motor control (Eject direction)

Loading motor control (Loading direction)

8
9

ANT-ON
MONO

O
O

Power control for amplifier.

Force MONO output

10
11

SD
BAND-SW

I
I

SD signal input
Band plan setting of general area.

12
13

AREA1-SW
AREA2-SW

I
I

Destination select 1
Destination select 2

14, 15
16

RE1, 2
SEEK

I
O

Rotary encoder input 1, 2

SEEK output

17 20
21

NC
GND3

Not used.
GND

22 24
25

KEYIN3 1
ROT-IN

I
I

A/D key input 3 1

Rotary commander input

26
27

S-METER
TEST-SW

I
I

FM and AM common signal meter A/D conversion input

TEST mode select input

28
29
30

AM-IFC
FM-IFC
VDD2

I
I

31
32

VCOH-FM
VCOL-AM

I
I

33
34

GND2
NC

GND
Not used.

35
36

EO1-PDOUT
TESTO

Error out output

Fixed at L.

37
38

AM-ON(TU-ON)
FM-ON(FM/AM)

O
O

AM power output (AM select)

FM power output (FM select)

39
40

LCL/DX
BEEP

O
O

LOCAL/DX select (H : LOCAL, L : DX)

BEEP output

41
42

ACC-IN
SCOR

I
I

Accessory input
SUBQ data read request

43
44

MUTE
AMP-MUTE

O
O

System mute output

Power amplifier mute output

45
46

TEL-MUTE
NC

Telephone mute output

Not used.

47
48

VOL-CE
VOL-CLK

O
O

Electric volume chip select

Electric volume serial clock

49
50

VOL-DATA
EMPHO

O
O

Electric volume serial data

De-emphasis control output

51
52

PW-ON
MD-ON

O
O

System power control

Loading motor power

53
54

CD-ON
ILL-ON

O
O

Servo drive power

Illumination output

55, 56
57

MOD1, 2
NC

Bus boost control 1, 2

Not used.

58

LCD-CE

LCD drive chip select output

AM center frequency input

FM center frequency input
Power supply (+5 V)
Local oscillation frequency input (FM)
Local oscillation frequency input (AM)

19

Pin No.
59

Pin Name
EZ-SEL

I/O
I

Pin Description

60
61

SENS
FOK

I
I

62
63

LD-ON
NC

Laser diode control

Not used. (Connect to GND.)

64
65

ST/MONO
LCD-CKO

I/O
O

Used for both STEREO indicator display input and force MONO output. (FM)
LCD driver serial clock output

66
67

LCD-SO
C.ALARM

O
O

LCD driver serial data output

Caution alarm output

68
69

SQ-CKO
CD-RST

O
O

Q data read serial clock output

Servo IC/DAC reset output

70
71

SQ-SI
CD-SO

I
O

Q data input
Serial data output to servo IC.

72
73

CD-LAT
CD-CKO

O
O

Data latch output to servo IC.

Serial clock output to servo IC.

74
75

VREF
GND1

Not used.
GND

76
77

X-OUT
X-IN

Crystal oscillator connection (4.5 MHz)

Crystal oscillator connection (4.5 MHz)

78
79

BU-IN
VDD1

Back-up detection
Power supply (+5 V)

80

RESET

SHIFT + input
Information input from servo IC.
Focus OK input

RESET input

20

CDX-4180

4-4. SCHEMATIC DIAGRAM CD MECHANISM SECTION Refer to page 22 for Waveforms and Note and page 37 for IC Block Diagrams.

(1/2)

(Page 33)

25

26

CDX-4180

4-6. SCHEMATIC DIAGRAM DISPLAY SECTION

DISPLAY

(2/2)

(Page 36)

Note:
All capacitors are in F unless otherwise noted. pF: F
50 WV or less are not indicated except for electrolytics
and tantalums.
All resistors are in and 1/4 W or less unless otherwise
specified.
U : B+ Line.
Power voltage is dc 14.4V and fed with regulated dc power
supply from ACC and BATT cords.

29

C : panel designation.
Voltage is dc with respect to ground under no-signal
(detuned) condition.
no mark : FM
Voltages are taken with a VOM (Input impedance 10 M).
Voltage variations may be noted due to normal production
tolerances.

30

CDX-4180
4-8. SCHEMATIC DIAGRAM MAIN SECTION (1/2) Refer to page 37 for IC Block Diagrams.

(Page 26)

TU01

Note:
All capacitors are in F unless otherwise noted. pF: F
50 WV or less are not indicated except for electrolytics
and tantalums.
All resistors are in and 1/4 W or less unless otherwise
specified.

: internal component.
C : panel designation.
U : B+ Line.
Power voltage is dc 14.4V and fed with regulated dc power
supply from ACC and BATT cords.
Voltage is dc with respect to ground under no-signal
(detuned) condition.
no mark : FM
(
) : AM
<
> : CD PLAY
: Impossible to measure

Voltages are taken with a VOM (Input impedance 10 M).

Voltage variations may be noted due to normal production
tolerances.
Signal path.
F : FM
f : AM
J : CD

R601
3.3k

33

34

CDX-4180
4-9. SCHEMATIC DIAGRAM MAIN SECTION (2/2) Refer to page 34 for Note and page 37 for IC Block Diagrams.

DISPLAY

(Page 29)

35

36

 IC Block Diagrams

SEIN
CLOK
XLAT

VDD
XLTO
DATO
CNIN

XLON
SPOD
SPOC
SPOB
SPOA
CLKO

IC1 CXD2507AQ

64 63 62 61 60 59 58 57 56 55 54 53 52

MON
MDP
MDS
LOCK
TEST

2
3
4
5
6

FILO

FILI
PCO
VSS
AVSS
CLTV
AVDD

8
9
10
11
12
13

RF
BIAS
ASYI
ASYO
ASYE

14
15
16
17
18

SERVO AUTO
SEQUENCER

SUB CODE
PROCESSOR

CPU
INTERFACE

14

51
50
49
48
47
46
45
44
43
42
41
40

DIGITAL
CLV

EFM
DEMODULATOR

DIGITAL
PLL

DATA
XRST
SENS
MUTE
SQCK
SQSO
EXCK
SBSO
SCOR
VSS
WFCK
EMPH

3
ASYMMETRY
CORRECTOR
D/A
INTERFACE

ERROR
CORRECTOR

16K
RAM

DIGITAL
OUT

39 DOUT
38
37
36
35
34

CLOCK
GENERATOR

FOK

C4M
FSTT
XTSL
XTAO
XTAI

33 MNTO

WDCK 19

GTOP
XUGF
XPCK
VDD
GFS
RFCK
C2PO
XROF
MNT3
MNT1

LRCK
PCMD
BCLK

20 21 22 23 24 25 26 27 28 29 30 31 32

OP IN

OP IN +

VREF

CH3

CH3-IN

CH2

CH2-IN

VCC

CH1

CH1-IN

CH1 +

CH1

CH2 +

CH2

IC3 BA6796FP

28

27

26

25

24

23

22

21

20

19

18

17

16

15

LEVEL
SHIFT

VCC
LEVEL
SHIFT

DRIVE
BUFFER

DRIVE
BUFFER

DRIVE
BUFFER

DRIVE
BUFFER

LEVEL
SHIFT

THERMAL
SHUT
DOWN

DRIVE
BUFFER

DRIVE
BUFFER

DRIVE
BUFFER

DRIVE
BUFFER

DRIVE
BUFFER

10

11

12

13

14

CH5

COM

CH4 +

CH3 +

CH3

LOGIC

GND

LEVEL
SHIFT

V/I

CTL1

CTL2

FWD

REV

TRAY

REV

CH4

FWD

CH4-IN

CTL2

OPOUT

CTL1

37

PHD 1

PHD

LD

RF M

RF O

RF I

CP

CB

CC1

36

35

34

33

32

31

30

29

28

27 26 25

FOK

CC2

PHD 2

IC2 CXA1782BQ

LEVEL S

FOK

APC

MIRR
RF IV AMP1

IIL

24

SENS

TTL

23

C.OUT

22

XRST

21

DATA

20

XLT

19

CLK

18

VCC

17

ISET

16

SL O

15

SL M

14

SL P

13

TA O

DFCT

TTL
RF IV AMP2

TTL

FE BIAS 37

IIL DATA REGISTER

INPUT SHIFT REGISTER

FE AMP

ADDRESS DECODER

IIL
IIL

OUTPUT DECODER

38
TOG1-3
BAL1-3

F IV AMP
E

39

EI

40

FS1-4

TG1-2

TM1-7

PS1-4

FZC COMP

E IV AMP

BAL 3

BAL2

BAL1

TE AMP

HPF COMP
VEE

TRACKING
PHASE
COMPENSATION

LPF COMP

ISET

41
TM6

TED 42

TOG3

TOG2

TOG1

TG1
TM5
TM4

TEI

TZC

TM3

44

ATSC 45
46

FCS PHASE
COMPENSATION

TZC COMP

LPFI 43

TM2

DFCT

WINDOW COMP

FS1

TM1

TM7
FS2

ATSC

TDFCT 47

F SET

8 9

10

11

12

TG2

FSET

TA M

38

TGU

FDFCT

SRCH

FEI

FE O

FE M

FLB

FGD

FS4

48

FEO

VC

TG2

DFCT

LVRIN

LCOM

LT1
LT2

LT3

LTOUT
LSIN
NC

NC
LSB1

LSB2

IC401 LC75374E

33

32

31 30

29

28 27 26 25 24

23
22 LFIN

34
35
36
37
38

21 LFOUT

20 LROUT

LSELO
L4
L3
L2
L1

19 VREF
VDD 39

R1
R2
R3
R4
RSELO

18 CE
17 DI
16 CL
15
VSS
14 RROUT

13 RFOUT

CONTROL

40
41
42
43
44

DECODER

LATCH

SHIFT
REGISTER

3 4

6 7 8 9 10

11

RVRIN

RCOM

RT1
RT2

RT3

RTOUT
RSIN
NC
NC
RSB1

RSB2

12 RFIN
1

IC701 SM5852FS

DIGITAL
SIGNAL
PROCESSOR

SYSTEM
CLOCK

16
15
14
13

DB/DS
MOD2
MOD1
OPT

12 VDD

MUTE

ATTENUATION COUNTER

DEEN

FILTER & ATTENUATION

OPERATION BLOCK

RSTN 6

SEQUENTIAL
CONTROL

TESTN 7
MUTEN 8

OUTPUT
INTERFACE

11 LRCO
10 BCKO
9 DOUT

VSS 5

TIMING
CONTROL

NOISE SHAPER
OPERATION BLOCK

MUTE
CONTROL
MODE
CONTROL

24 ATCK
23 MODE

CLK 4

INPUT
INTERFACE

LRCI 1
BCKI 2
DI 3

IC702 SM5878AM

CKO
DVSS
BCKI
DI

3
4
5
6

22 RSTN
21 DS
20 XVSS

CLOCK
GENERATOR

INPUT INTERFACE

DVDD 7
LRCI 8

19 XTO
18 XTI
17 XVDD
16 MUTE

TSTN 9
TO1 10

AVDDL 11

LO 12

39

11 LEVEL
DEM DAC

11 LEVEL
DEM DAC

11 LEVEL
DEM DAC

11 LEVEL
DEM DAC

LPF

LPF

AMP

AMP

15

AVDDR

14 RO
13 AVSS