Code No: 34040 R05 Set No.

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II B.Tech II Semester Supplimentary Examinations,February 2010
COMPUTER ORGANISATION
Common to Instrumentation And Control Engineering, Electronics And
Computer Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. What are the different modes of data transfer? Explain each mode in detail. [16]

2. (a) Design a 4-bit odd parity generator and checker. Can parity bit be used for
error deltection. If so how.
(b) Distinguish between high level and low level languages? What are the require-
ments for a good programming language? [16]

3. What are the different types of Mapping Techniques used in the usage of Cache
Memory? Explain. [16]

4. Explain with a block diagram the general structure of a CPU along with registers
and ALU. Also, explain what is a control word and relate it with the functioning
of the CPU. [16]

5. (a) Explain arithmetic overflow and divide overflow with some examples for 2’s
complement numbers.
(b) Explain restoring method of division with two 4 bit numbers. [8+8]

6. (a) Explain nanoinstructions and nanometry. Why do we need the same?

(b) Support or oppose the statement “If we want to add a new machine language
instruction to a processors instruction set simply write a C program and com-
pile and store the resultant code in control memory”. [8+8]

7. (a) What are the different physical forms available to establish an inter-connection
network? Give the summary of those.
(b) Explain time-shared common bus Organization.
(c) Explain system bus structure for multiprocessors [6+5+5]

8. Explain three segment instruction pipeline. Show the timing diagram and show the
timing diagram with data conflict. [16]

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Code No: 34040 R05 Set No. 4
II B.Tech II Semester Supplimentary Examinations,February 2010
COMPUTER ORGANISATION
Common to Instrumentation And Control Engineering, Electronics And
Computer Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) What is pipelining? Explain.

(b) Explain four segment pipelining. [8+8]

2. (a) Explain programmed I/O in detail.

(b) Explain interrupt initiated I/O in detail. [8+8]

3. Explain the following with applications for each:

(a) ROM
(b) PROM
(c) EPROM
(d) EEPROM. [4+4+4+4]

4. (a) What are register windows? Where do we use them? Explain with an example
how they are used.
(b) Distinguish between CISC and RISC.Processors [8+8]

5. (a) Give means to identify on whether or not has overflow has occurred in 2s
complement addition or subtraction operations. Take one example for each
possible situation and explain. Assume 4 bit registers. Let If overflow register
E is also considered, check whether the result is corrector not
(b) Represent -32.75 and 18.125 in single precision IEEE 754 representation. [6+10]

6. (a) Differentiate tightly coupled and loosely coupled multiprocessors according to

hardware.
(b) Differentiate tightly coupled and loosely coupled multiprocessors according to
programming techniques [8+8]

7. (a) How do we reduce number of microinstructions. What are micro-subroutines?

(b) Explain nanoinstructions and nanometry. Why do we need them. [8+8]

8. (a) What is the use of fast multiplication circuits. Write about array multipliers.
(b) Explain booths algorithm with its theoretical basis. [8+8]

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Code No: 34040 R05 Set No. 1
II B.Tech II Semester Supplimentary Examinations,February 2010
COMPUTER ORGANISATION
Common to Instrumentation And Control Engineering, Electronics And
Computer Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) Explain about sign magnitude and 2’s complement approaches for representing
the fixed point numbers. Why 2’s complement is preferable.
(b) Give means to identify whether or not an overflow has occurred in 2’s comple-
ment addition or subtraction operations. Take one example for each possible
situation and explain. Assume 4 bit registers. [8+8]

2. (a) How many bits are needed to store the result addition, subtraction, multipli-
cation and division of two n-bit unsigned numbers. Prove.
(b) What is overflow and underflow. What is the reason? If the computer is
considered as infinite system do we still have these problems? [8+8]

3. (a) Design a circuit transferring data from a 4bit register which uses D flip-flops
to another register which employs RS flip-flops.
(b) What are register transfer logic languages. Explain few RTL statement for
branching with their actual functioning. [8+8]

4. (a) Explain the functioning of omega switching network with a neat sketch.
(b) In 8 × 8 omega switching network how many stages are there and in each
stage how many Switches are there.
(c) How many stages and how many Switches in each stage are needed in a n ×
n omega sitching network. [8+4+4]

5. (a) Explain bit oriented and character oriented protocols in serial communication
(b) What are the different issues behind serial communication? Explain. [8+8]

6. (a) What are the design goals for a designer while deciding a hardwired or micro-
programmed CU for a CPU.
(b) Explain nanoinstructions and nanometry. Why do we need them. [8+8]

7. (a) How to implement 2K × 32 memory module using 512K x 8 static memory

chips? Show a neat sketch.
(b) How many 128 × 8 RAM chips are needed to provide a memory capacity of
2048 bytes?
(c) How many lines of address bus must be used to access 2048 bytes of memory?
[8+4+4]

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Code No: 34040 R05 Set No. 1
8. Explain the following in related with Vector Processing

(a) Super Computers

(b) Vector operations
(c) Matrix multiplication
(d) Memory interleaving [4+4+4+4]

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Code No: 34040 R05 Set No. 3
II B.Tech II Semester Supplimentary Examinations,February 2010
COMPUTER ORGANISATION
Common to Instrumentation And Control Engineering, Electronics And
Computer Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) Explain the working of 8 × 8 Omega Switching network.

(b) Explain the functioning of Binary Tree network with 2 × 2 Switches. Show a
neat sketch [8+8]

2. (a) What is a virtual memory technique? Explain different virtual memory tech-
niques.
(b) Explain how the technique of paging can be implemented. [8+8]

3. (a) What is daisy chaining? Explain with neat sketch.

(b) What is parallel priority interrupt method? Explain with neat sketch. [8+8]

4. (a) What are the different interconnection structures used in multiprocessors. Ex-
plain about multistage crossbar switch.
(b) Support or oppose the statement “Every efficient serial program is efficient
parallel program”. [8+8]

5. (a) Explain single precision and double precision calculations. In general how
many bytes are used for both and what is the precision we get. Give some
examples where double precision calculations are needed.
(b) Explain how we can identify arithmetic overflow has occurred or not while
adding/subtracting two signed numbers. Draw the circuit for performing ad-
dition/substraction of two 4 bit numbers that checks the overflow. [8+8]

6. (a) Explain nanoinstructions and nanometry. Why do we need them?

(b) Describe advantages and disadvantages of horizontal and vertical microcoded
systems. [8+8]

7. (a) Explain about stack organization used in processors. What do you understand
by register stack and memory stack?
(b) Explain how X=(A+B)/(A-B) is evaluated in a stack based computer.[10+6]

8. Explain the following with related to the Instruction Pipeline

(a) Pipeline conflicts

(b) Data dependency
(c) Hardware interlocks

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Code No: 34040 R05 Set No. 3
(d) Operand forwarding
(e) Delayed load
(f) Pre-fetch target instruction
(g) Branch target buffer
(h) Delayed branch [8×2=16]

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