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15MVD0001
EXPERIMENT-2
i)
15MVD0001
NMOS Length:-100nm
PMOS Length:-100nm
EXPERIMENT-2
NMOS Length:-100nm
15MVD0001
EXPERIMENT-2
15MVD0001
i)
Go to Outputs save allenable all pubRun transient
ii)
Go to Browseropen resultspsf files click on power
The characteristics of the transistors remain same as the above but this circuit has an extra capacitive load
EXPERIMENT-2
i)
ii)
15MVD0001
The characteristics of the transistors remain same as the above but this circuit has an extra capacitive load
of 50fF.
RESULTS:
EXPERIMENT-2
15MVD0001
From the above graph we note that the threshold point for the given specification of the
transistor is 735.392mV
VOH : 1.5V
VOL :1mV
EXPERIMENT-2
15MVD0001
For PMOS widths of 270nm, 315nm, 350nm we have observed the shift in threshold voltage of
CMOS inverter.
EXPERIMENT-2
15MVD0001
The derivative of the Voltage transfer curve is taken and points where the gain is -1 is noted
down for VIH and VIL values.
VIH :944.882mV
VIL : 578.868mV
Noise margin = min(NMH , NML)
NMH = VOH VIH = 0.555118
NML = VIL VOL = 0.578868
Hence noise margin is 0.555118V
EXPERIMENT-2
15MVD0001
The spikes obtained in the graph are as a result of the rise time delay in input and fall time delay in the
output. The delays can be seen in the below graph.
The delays observed from transient analysis of a CMOS inverter without any load capacitance
are:
EXPERIMENT-2
15MVD0001
tphl = 4.427 ps
tplh = 3.475ps
t PHL+ t PLH
tp =
2
= 3.951ps
The average power consumed by the cmos when no load is connected is 187.6 nW
EXPERIMENT-2
15MVD0001
The average power consumed by the cmos inverter when 20pF load is connected is 2.479 uW.
Power calculation Graph for the capacitive load of 50fF
The average power consumed by the cmos inverter when 50pF load is connected is 5.911 uW.
CONCLUSION:
1. If the width of the PMOS is increased the transfer characteristics would shift towards right.
2. The threshold point obtained is 735.392mV for PMOS width of 290nm.
EXPERIMENT-2
15MVD0001
3. The propagation delay obtained is 3.951ps and we can observe that tplh< tphl.
4. The average power dissipated by a CMOS inverter increases as we increase the load capacitance.
5. Average power consumed by a CMOS inverter
a) Without load capacitance:187.6 nW
b) With 20fF load capacitance:
2.479 uW
c) With 50fF load capacitance:
5.911 uW
REFERENCES:
1. Design of analog CMOS integrated circuits- Behzad Razavi.
2. Digital integrated circuits(A design perspective)- Jan M. Rabaey