ECE344

Theory and Fabrication of

Integrated Circuits

Fall 2003

Copyright ©2002
University of Illinois Department of Electrical and Computer Engineering

This manual should not be reproduced without permission from the University of Illinois Department of Electrical and Computer
Engineering
ECE344 Laboratory Manual
The most current version of the manual is the web - there are always manipulations mid-
semester - and announcements will be made in the uiuc.class.ece344 newsgroup.

ICS Tutorial 3
ICS Prelab 4
Integrated Circuit Fabrication Recipe 13
Oxidation Prelab 16
PR Prelab 20
Data Sheets 43
Graphs and Tables
Concentration v. Resistivity GT1
Four Point Probe Correction Factors GT2-3
Oxidation GT4-6
SiO2 Color Chart GT7
SiO2 Properties GT8
Trumbore Curves -Silicon GT9
Diffusion GT10
BN Rs v. t GT11
erfc Properties GT13-14
Ion Implantation Effective Range Data GT15
Kennedy and O’Brien BV Curves GT16
Physical Constants GT19
Vapor Pressure Curves GT20
Herman Mask Set GT21
Appendices
ICS A
Evaporator B
Wafer Cleaning C
Photoresist Processing D
Hot Point Probe E
Four Point Probe F
Furnace G
UltraTech 1000WF Stepper H
Mask Set I
Test Stations/Probers J

NOTE: Items to be handed in as assignments are in dark blue text.

There are also questions located throughout the manual in red text. The
answers to these questions are not turned in, but it is a good idea to know the
answers (great quiz questions).
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ECE344 Fall 2003 Lab Manual

ICS Tutorial
1. Prelab
2. Commercial Device Measurements
3. Schottky Diode Fabrication
4. Schottky Diode Measurement
5. Schottky Diode Calculations
6. Write-up

The purpose of this tutorial is to give you some experience with Metrics ICS, as well as an
evaporator and a prober. Later in the semester you will be using these again without the 3:1
student teacher ratio you will have for this tutorial. You will, in fact, be graded on your
preparedness when you use these items later with your IC wafer, so please make the most of
this exercise and the lab instructor.

Three basic electronic devices will be tested:

• a commercial Bipolar Junction Transistor (BJT)

• a commercial P-channel Metal-Oxide-Semiconductor Field Effect Transistor (P-
MOSFET)
• Schottky diodes

The lab will be broken into three parts:

• 1st hour: become familiar with ICS by testing the commercial devices in the test
fixtures
• 2nd hour: fabricate Schottky diodes using the evaporator
• 3rd hour: test the Schottky diodes using the probe stations and ICS

Note: It will not matter if you finish the modeling and measurements since the write-up is not
due for several weeks and they can serve as "filler" activities until then. "Filler" activities are
needed when you are waiting for equipment, waiting for a diffusion to finish, or when it's too
late in the period to start a photoresist operation.

The Schottky diode fabrication must be completed during the lab period reserved for this
tutorial.

Note that the diode fabrication may be skipped depending on the time left and the availability
of the evaporator.
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ECE344 Fall 2003 Lab Manual

ICS PRELAB
After reading through this ICS Tutorial up to the Commercial Device Measurements, the
Appendices for the equipment, and the web links, answer the following questions.

1. Evaporation Questions:

a) Define what is meant by the term "cracking the oil" in a diffusion pump? (See Appendix B
in the printed version).

b) What steps should you take if the foreline pressure exceeds 100 microns in a hot
diffusion pump?

c) What is the procedure to bring the cryo-pump on-line after a power failure or shutdown?
At what cold head temperature can the pump be used efficiently? See
http://www.helixtechnology.com/literature/cti/8040613.pdf

d) A diffusion pump requires a foreline pump to keep the bottom of the diff pump at a low
pressure. The foreline pump then exhausts to the toxic exhaust ductwork. Where do the
pumped gasses from a cryocondensation pump go? What implications does this have on
the use of a cryo-pump?

e) What types of pressure transducers are used on the Cooke CVE301? What types are
used on the Varian 3120? Classify them according to pressure range. See the
Appendices and web pages (Main→Lab→Equipment).

f) Draw the plumbing schematic for a diffusion pumped vacuum system. Draw the
schematic for a cry-pumped vacuum system. Include all necessary valves, pumps, and
pressure transducers.

2. Testing Questions

a) In the context of a test instrument, "compliance" tells the instrument how far to go in order
to comply with a measurement request. For example, if the instrument is told to sweep
the voltage from 0 to 5 V, and the compliance is set at 100 mA, then the instrument will
try to sweep the voltage up to 5V, but will limit the current to 100 mA (the instrument then
acts as a constant current source set to 100mA).

Suppose you tell an instrument to measure the I-V characteristic of a 1 KΩ resistor. You
set the voltage sweep to go from 0 to 10 volts, and you set the compliance at 5 mA.
Create a current vs. voltage curve that would result using Microsoft Excel or other
spreadsheet program. What is the significance of the 5 mA compliance on your plot?

b) What electrical parameters can the Agilent 4155C measure? The Agilent/HP 4284?
Refer to the manufacturers web pages (they are located in the Test and Measurement
section).
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ECE344 Fall 2003 Lab Manual
c) Find the following entries in the ICS_Prelab_Data.DAT file in your network (W:) drive. To
view, open Excel and drag the ICS_Prelab_Data.DAT file (located in your network drive)
into the Excel window.

• The range of collector voltage (start to stop) applied to the BJT in the Ic_vs_Vce
setup.
• The highest voltage difference applied between the device pins by the MTP2955
model. Is this safe for the device even if you connect the device wrong? (See
Motorola’s data sheets following the Tutorial in the paper version.)

d) Open the worksheet BVcbo in the ICS_Prelab_Data.DAT file using Excel. You will note
that a graph has been created labeled Ic vs Vce. Graphical representations of data
usually explain the data better than raw data. Create a family of curves for the data in the
Ic_v_Vce worksheet. (Refer to Microsoft Excel’s help section or the graphing tutorial on
the web.)

The graph should represent Ic vs Vce for different base currents. Label the graph
completely – include a title describing what the graph is about, axis labels (including
units), a series legend or Y2 axis label (to be able to determine base currents), and any
other relevant information needed to convey what the graph represents. Save the data as
an Excel spreadsheet (.xls), renaming it to username.ICS_Prelab_Data.xls where
username is your netid.
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ECE344 Fall 2003 Lab Manual

ICS - Commercial Device Measurements

You will make some simple measurements on a 2N2222 general purpose BJT and a MTP2955
P-channel power FET. Some of the information here is the same as under Exploring ICS above,
but here you will actually be making measurements. Be sure that you don't accidentally skip over
a measurement.

Initial startup
1. Plug in the devices if they aren't already. The 2N2222 should be in the left socket and the
MTP2955 on the right.
2. Check that the Agilent 4155C cables labeled SMU1, SMU2 and SMU3 are connected to
the test fixture's connectors of the same names.
3. Turn on the Agilent 4155C and HP4284A.
4. Log into the PC workstations
5. Start ICS.
6. Open the 2N2222 BJT setup first.

BJT Measurements
1. Make sure the switch on the test fixture is in the left position to select the 2N2222.
2. Open the BJT2N2222 setup.
3. Open the IC_V_VCE Data and Graph windows.
4. Click on the Measure button (if the Measure window is not already open). Do a Single
measurement.
5. When the measurement is finished, the plot will update with the new test data.
6. If the plot doesn't look familiar to you, ask your lab instructor for help interpreting it or
review the BJT plot screens on the web. After ECE 342 (not a prerequisite) you will
recognize this as what is commonly called the "family of curves" for a BJT. Instruments
called curvetracers specialize in displaying such curves. The Agilent 4155C is far more
flexible, especially under computer control.
7. Minimize the Ic_vs_Vce setup window.
8. For each of the BV (Breakdown Voltage) setups (i.e., BVcbo, BVebo, BVceo), display the
plot and make the measurement.

Note that you may not see a breakdown of the Collector-Base junction, even up to 100 V,
so you will need to edit the BVcbo Test Setup to apply a higher voltage. The 4155C can
only source from -100 to +100V. Hmmmmm..., how will you apply > 100V reverse voltage
to the CB junction?
9. Continue testing for the rest of the setups.
10. That's it for making BJT measurements. Store the data*. Whenever you complete new
measurements, it's a good idea to save the information.

*Select Save under the File pull-down menu and follow the prompts.

11. It's always wise to occasionally store the data to a secondary filename. Select Save As
under File. Add “backup” as Attribute #5 and click on OK.
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ECE344 Fall 2003 Lab Manual

MTP2955 P-Channel MOSFET Measurements

1. Make sure the switch in the test fixture is flipped to the right to select the MOSFET.
2. Open the IDVG data and graph windows.
3. Perform a Single measurement.
4. The plot should vaguely resemble the curvetracer plot of the BJT2N2222, but note that
the spacing between curves is not uniform. Review FET operation if this is a surprise to
you.
5. Collect the data for the other (IDVD) setup in the same manner.
6. Explore and understand the setups and MOSFET ICS plots. Try modifying the plots to
get as much data as possible from the setups displayed.
7. Save your data to multiple places as before.

Schottky Diode Fabrication

Your instructor will demonstrate how to fabricate schottky diodes about an hour into the lab
section.

Be sure to record the wafer manufacturer's specs in your lab notebook along with any
observations you make during the process. Employers appreciate good record keeping by
their engineers.
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ECE344 Fall 2003 Lab Manual

Schottky Diode Measurements

1. Area calculation:
• Measure the diameters of three round aluminum dots using the metallurgical
microscope with the reticle. When the microscope is on the 8x magnification,
each major division of the reticle is 0.11440mm.
• Calculate the average diameter, and use it to obtain an average dot area.
2. Start ICS and open the Schottky Setup.
3. Connect the instruments as follows:
• The 4155C’s SMU1 to the triax connector for probe 1.
• The 4155C's SMU4 to the triax connector for probe 4/chuck.
• The HP4284A's L (cur and pot) connectors to the coax connector for probe
4/chuck.
• The HP4284A's H (cur and pot) connectors to the coax connector for probe
1.
4. Make sure a jumper is in place of probe 4 so the wafer chuck is connected to an
instrument instead.
5. Turn on the instruments - the 4155C and the HP4284A.
6. Place the wafer onto the wafer chuck and turn on the chuck vacuum.
7. Using the probing instructions, probe the device with probe 1. (Be sure to note the
Dos and DON’Ts).
8. Make sure the switches on the side of the prober are in the UP position, so that the
probe station will be connected to the 4155C for I-V measurements.
9. Measure the device as you did with the commercial devices, but this time you may
find you will need to adjust some of the setup table inputs in order to maximize the
meaningful data in the plots about the diodes (hint-hint).
10. Flip the switches on the side of the prober to the DOWN position, so that the probe
station will be connected to the HP4284A for C-V measurements.
11. Perform the C_vs_V measurement. Note that the first time the capacitance meter is
used, a calibration must be performed:
• Check to make sure the cables are connected to the correct probes and the
corresponding switches on the probe station are down.
• Lift all the probes off of the wafer.
• On the LCR meter press MEAS SETUP
• A menu on the LCD display will give you four options. Press CORRECTION
• Scroll down using the cursor arrows until Freq 1 is highlighted (this should be
set for 1 MHz)
• A new menu will appear. Press MEAS OPEN
• This completes the calibration. Note: this will need to be done for every new
probe configuration (i.e. if CMH or CML are changed).
12. When the data looks like what you would expect from the knowledge you gained in
ECE 340, save the model.
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ECE344 Fall 2003 Lab Manual
13. Save the model adding your name to Attribute #3 and Data1 to Attribute #4.
14. Open the original Schottky setup.
15. Probe another round diode and use the original Schottky model to gather new data.
(Remember that you saved the previous data in the Data1 setup.)
16. When finished, save the model as Data 2 as in step #13. Now you have saved data
from one diode in the Data1 setup, and data from another in the Data2 setup
17. Repeat for a third device, Data3.
18. In addition to saving the setups to a file, save them to an alternate filename as well –
just in case something goes wrong.
19. Don't forget to make sure you know the average diameter for your Schottky diodes.
(You do not need to measure the diameters on the same dots that you tested using
ICS.)

Schottky Diode Calculations

If you finish testing early, you are advised to begin the calculations during class. There are
items which require ICS to complete. If you are working on this outside of class, then you
can Remote Desktop into the lab computers. If you do not have a Remote Desktop client, it
is available on Microsoft’s website.
The addresses for the lab computers are el50q-01 to el50q-06.ece.uiuc.edu.
For each of the Schottky models:

1. Create a plot of log10(C) vs. log10(Vo-V) in each of the Schottky setups (Data1 to Data3).
To do that:
• Open the C_VS_V data window.
• Click the Transform Editor button.
• Create and save two transforms:
• LOGC=LOG(C)
• LOGV=LOG(0.1-BIAS) (V0 is set for 0.1 for now)
• Close the Transform Editor.
• Click the Create Plot button.
• For the X-axis select LOGV for the Data Group.
• For the Y-axis select LOGC for the Data Group.
• Click on Done when finished.
• In general, you will want to add a header and footer using the Opts menu on the left
of the plot menu.
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ECE344 Fall 2003 Lab Manual

2. Fit a line to the data and note the slope. To use the line fitting functions in ICS:
• Open the Cursors menu on the left. Click the OFF button for the square and diamond
cursors. They will toggle to Y1 and place appropriately shaped cursors on the graph.
• Move the cursors with your mouse to define the two points the line will intersect.
• Open the Fits menu on the left and select Fit #1. Click the square and diamond
buttons to select the cursors to be used. Then click the blue diagonal line with yellow
boxes on either end to draw a line connecting the two cursors. Close the Fits menu.
• A green line will connect the two cursors with the slope, y-intercept, and x-intercept
displayed below the graph.
3. Create a new transform as follows: CINVSLP= POW(C,1/(m)) where m is the slope from the
logC vs logV plot. Then create a new plot with y-axis set to CINVSLP and x-axis set to BIAS.
4. Again fit a line to the data.
5. Substitute the absolute value of the X intercept from this latest plot (PowerLaw) into the
LOGV transform as Vo (which was initially set to 0.1).
6. Fit a line to the logC_vs_logV data again and, if necessary, plug its slope back into the
CINVSLP transform.
7. Iterate as many times as necessary until the slope and intercept values differ by less than 5%
between iterations.
8. Now, you should have a pretty good measurement of Vo, and the slope should be close to -
0.5 .
9. Next, add three new transforms:
• DERIV=DIFF(POW((C/area),-2),BIAS) where area is the area of the diode
• XN=(11.9*8.85E-14*area)/C where area is the area of the diode
• N=(-2)/(11.9*8.85E-14*1.6E-19)*POW(DERIV,-1)
10. Create a new plot with the x-axis set to XN and the y-axis set to N. You have created a plot of
doping concentration vs. distance into the wafer. Title it accordingly.
11. Save often…
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ECE344 Fall 2003 Lab Manual

Schottky Diode Report

This report is typically due two weeks after the end of the prelabs. Your TA will let you know
the exact date.

1. Check the ECE344 newsgroup for additions, deletions, or changes for this write-up.
2. Do the Schottky Diode Calculations as described above.
• What is the average area of your Schottky diodes? Show your calculations.
• What values did you find for the slope of the log(C) vs log(V0-V) plots?
• What are the corresponding values of V0 from the PowerLaw plots?
3. Compile all your data (commercial devices and Schottky diodes) into an Excel
spreadsheet. To do this:
• Open the setup
• Under File in the pull down menu, select Export. Select the directory to save to,
name the file (example: Schottky.data1.dat), select ASCII (all setups), then click
on OK.
• Continue the process for the remaining setups (make sure you use a consistent
naming convention).
• Start Excel. Open the file (name.dat ) by dragging it into Excel (easiest method)
or by using Open under the File menu. If you use the Open method, you will be
asked a series of formatting options for the DAT file:
• Select Delimited
• Start import at row 1
• Click Next
• On the next page select Tab as the delimiter
• Click Finish
• Rename the worksheet if desired.
• Continue opening the files in Excel as described above.
• Create a new workbook and copy the data from the individual files into separate
worksheets. Save the compiled data into a file named Tutorial.login_name.xls
(where login_name is your netid).
• Email the Excel file to your TA.
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ECE344 Fall 2003 Lab Manual

4. Show where the equations used in the Schottky Diode Calculations section for the
determination of the doping concentration and built-in voltage of the Schottky diodes
come from (refer to your ECE 340 text.) Term by term discussion would be useful here.
In other words, suppose that we did not tell you what equations to use in making the
plots.

Derive the following using

(do not derive this equation, use it to derive the following)
• equations for Nd vs. w
• equations used to determine Vo, the built-in voltage.
5. Find a value for β (Ic/Ib) for the transistor. Is it a constant (i.e. independent of bias)? Hint:
You can add a plot of Ic/Ib vs Ic in the Ic_vs_Vce setup. You can also look at the
fgummel plots.
6. Find values of the threshold voltage (Vt) and the slope of the transconductance (gm) vs vg
(in saturation) of your measured PMOSFET.
To do that:
• In the MTP2955 idvg model, add a transform to calculate the transconductance,
gm = DIFF(ID,VG).
• Create a new plot with gm/id vs vg (insert gm as the Y-2 Axis).
• Choose two points on the gm curve in the saturation region (gm is linear there)
and fit a line as before.
The slope and intercept of the line are displayed on the plot. Your 340 textbook (or
other reference) will help you to find Vt from this line.
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ECE344 Fall 2003 Lab Manual

IC FABRICATION EXPERIMENT
1. Introduction 14
2. Oxidation Pre-lab Report 16
3. Degrease tweezers and wafers 17
4. Remove native oxide 17
5. RCA Cleaning 17
6. Oxidation 18
7. Starting Material Information 19
8. Photoresist 1 Pre-lab Report 20
9. Degrease IC wafer and tweezers 22
10. PR1 - Open windows for first diffusion 22
11. Boron Predeposition 24
12. Remove borosilicate glass 25
13. Boron Drive 25
14. PR2 - Open windows for Phosphorus Predeposition 26
15. Phosphorus predeposition diffusion 27
16. Remove phosphosilicate glass 28
17. PR3 - Open windows for gate oxidation 29
18. Gate oxidation 29
19. Measurement of oxide thickness using ellipsometer 29
20. PR4 - Open contact windows 30
21. Processing Report 31
22. PR5 - Define metal contact areas 34
23. Aluminum evaporation for contacts 34
24. Aluminum Lift-off 34
25. Anneal contacts 35
26. Electrical testing 35
27. Final Report 36
28. References 41
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ECE344 Fall 2003 Lab Manual
Introduction
The student will produce a
variety of electronic devices
and circuits in this
experiment. A special mask
set was designed for the
fabrication of more structures
than he or she could possibly
test and analyze during the
semester. Each mask
contains 45 complete copies
of the appropriate layer of the
device cell. Three cells are
combined into what is known
as a field. A test area has
been included in each field to
monitor and map intermediate
processing parameters. You
should look at Appendix I to
see which parts of the test
area to use for measurements
at different stages of the
process.
The class will be split into
three groups which will start
at different stages of the
fabrication and testing. On
the fifth meeting of the
semester, everyone could be
at the same step and
requiring the same piece of
equipment. Fortunately,
people work at different paces
and will probably be
staggered enough to minimize
such "collisions". It will be in
your best interest to come
prepared to proceed as far as
possible in the process each
period.
-Cleanliness is of utmost
importance in the
fabrication process.
Contaminants introduced
during the process can
degrade or destroy device
performance. Therefore, it is
important that processing
equipment or chemicals are
never touched with the bare
hands, (i.e., diffusion
furnaces, push rods, boats,
etc.). Not only do the bare
hands contain dirt and oils,
but also sodium, which can
easily destroy FETs (why?).
Always handle the wafer with
clean tweezers. A good rule
to remember is to never touch
anything with your bare hands
that will come in contact with
the wafer.
-Always consult the
instructor if any mistakes
are made in processing.
Always consult your instructor
at the beginning of the period
for any special processing
instructions. Often the
instructor will call a short
meeting at the beginning to
make such announcements to
everyone at once.
-Photoresist should not be
left on wafers overnight. Do
not begin a photoresist
operation unless you are
confident you can finish it. At
the beginning of the semester
a PR patterning process will
take a little over an hour.
Later, it will go quicker.
Processing
Overview
In addition to reading the
description below, you can
also look at schematic cross-
sections of a FET and BJT at
various stages in the ECE344
process. The cross-sections
should be useful in
understanding the purpose for
the various processing steps.
The first step will be to clean
and oxidize a batch of wafers
in a group of three students.
The wafers will be referred to
as the "IC wafers" in this
recipe. A pattern will be
etched through the oxide
using Mask 1 and the
Photoresist (PR) process
outlined in the manual. The
wafer will then be subjected to
a boron ambient at high
temperature so that the boron
will diffuse into the N-type
silicon through the ‘holes’ in
the oxide, forming P-regions
on the wafer in those areas
delineated by Mask 1. This
diffusion is known as the
predeposition or predep
diffusion.
After the wafer has been
suitably cleaned and excess
boron removed, it will be
subjected to another diffusion,
called the redistribution or
drive diffusion, this time
without the boron source. The
idea here is to move the
dopant farther into the wafer.
This diffusion will be made in
an oxygen atmosphere so
that another layer of oxide is
grown simultaneously on the
wafer to mask the P-regions
from subsequent doping
processes.
After suitable cleaning, a
second PR process using
Mask 2 will be used to
delineate areas which will be
changed back to N-type by a
phosphorus predeposition
diffusion. The third mask will
be used to remove oxide from
the gate regions of the FETs
so that a thin high quality gate
oxide may be grown there.
Mask 4 will be used to etch
holes down to the various
regions through which metal
contacts to the silicon surface
can be effected. Mask 5 will
be used to define the
aluminum contact areas, and

then aluminum will be vacuum
evaporated over the entire
wafer. The photoresist will be
removed, lifting off the metal
in the unwanted areas. Scale
drawings of these masks are
available for study in
Appendix I of this manual.
The ECE344 homepage on
the World Wide Web
(http://fabweb.ece.uiuc.edu)
contains an interactive image
of the mask set, which can be
very useful in exploring the
various regions of the mask
set.
Finally, you will form ohmic
Al-Si contacts by annealing.
This is a process in which the
ECE344 Fall 2003 Lab Manual
components of a system are
heated to a temperature
below the system's eutectic
point. (The melting point of a
given alloy of one substance
in another depends upon the
percentages of the materials
present. That point on a
phase diagram of temperature
vs. percent of each parent
material present where a
temperature minimum occurs
in the liquidus line is known
as the eutectic point. The
eutectic point for the Al-Si
system is 576°C.) You will
use a temperature of 475°C,
which permits the aluminum
atoms to move around and
spread more uniformly over
15
the silicon surface. In
addition, during annealing, the
aluminum can diffuse into the
silicon itself. Annealing is
used instead of alloying (i.e.,
heating of the system to
temperatures above the
eutectic point) because
experience in our lab has
shown that alloying often has
a detrimental effect on the
resulting p-n junction diode
characteristics (find out about
Al spiking on your own).
The devices will then be
tested, and operational chips
noted for further testing.

Cleanroom etiquette
• Leave most of your stuff outside the cleanroom.

• Bring only your lab manual, notebook, and a pen into the lab.

• Wait outside if there are already three persons in the gownroom.

• Don your tyvek coveralls and cap while on the "dirty" side of the bench.

• If you do not wear glasses, put on a pair of safety glasses or goggles.

• Contact lenses are unnecessarily risky because they can hold

chemicals against your eye. Please do not use them when you come to
lab.

• Put on the booties as you step onto the "clean" side of the bench.

• Never step on the dirty side of the gownroom with booties on.

• As you enter the cleanroom, take a couple of steps on the tacky mat to
remove lint from the booties.

• Never enter the wet lab without gloves and a face shield.
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ECE344 Fall 2003 Lab Manual

OXIDATION PRE-LAB REPORT

Turn in the answers to the following questions before carrying out the procedures in the rest
of this section.

1. What are the purposes of the SC-1 and SC-2 solutions in the RCA standard cleaning
procedure? Refer to the article by Kern in Appendix C of the paper version.

2. As an alternative to the RCA clean, a clean which uses a sulfuric acid-hydrogen peroxide
solution followed by an HF step has been proposed. List 5 advantages of this
substitution. (See Pieter Burggraaf's article "Keeping the 'RCA' in Wet Chemistry
Cleaning" in the appendix C of the paper version.) (The ECE 344 recipe uses Sulfuric
acid rather than Hydrochloric acid in the SC-2 solution.)

3. Refer to the oxidation step below. What gases are flowing during
• dry oxidation?
• steam oxidation?

4. In steam oxidation, how is the steam produced?

5. Explain in general terms why different thicknesses of oxide give different colors. Why is it
important to view samples vertically? (see Anner section 5.10)
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ECE344 Fall 2003 Lab Manual

Degrease Tweezers and Wafers

The Clean Air Act reduced the production of trichloroethane (TCA), which is a major
constituent of the degreasing procedure. There are alternatives, namely trichloroethylene
(TCE) and methylene chloride, both of which are or possibly are carcinogenic. Your lab
instructor will update you on the method of degreasing.
Your instructor will have a Teflon holder loaded with an appropriate number of wafers. The
degreasing procedure is posted on the degreaser hood and can be found in appendix C of
the paper version of the lab manual.

Remove Native Oxide

The instructor will have some extra words of caution just before your first experience with the
strong acids in the ECE 344 lab. Heed them and be careful!

1. Perform a 30-second oxide etch in the 50DI: 1HF acid under the acid Etch Hood to
remove any oxide which may have been built up due to exposure to air.
2. DI rinse in the HF Rinse tub under the Acid Etch Hood.
3. Spray rinse. Be sure to spray off any HF that may have gotten on the handle.

What is native oxide? Why must it be removed?

RCA Cleaning

Clean the wafers using the RCA standard clean in Appendix C of the paper version.
The procedures are posted on the wet lab's acid hoods, so please do not take your lab
manual or notebook into the wet lab. All you have to remember are the general steps, which
in this case are to degrease, remove native oxide, and RCA clean.

Why is it important to remove ionic impurities? What devices does this type of contamination
affect? What affect will they have on the performance of the devices?
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ECE344 Fall 2003 Lab Manual

Oxidation

The oxidation consists of a dry oxidation step, a steam oxidation step, and a final dry
oxidation step. The dry oxide is higher quality, but the steam oxide grows more quickly. You
will be doing the oxidation as a group. The lab instructor will demonstrate the loading and
unloading procedure first.
1. After a careful review of the instructions regarding the furnaces given in appendix G of
the paper version, a student should insert the wafers into the steam oxidation furnace (T=
1100°C) with nitrogen flowing.
2. One group member should be assigned to time keeping and switching gases. Once the
wafers have reached the center of the furnace:
• Turn on the O2 and turn off the N2 (the lower gas panel in the gas cabinet). By only
flowing O2, the wafers will undergo dry oxidation. Let the wafers soak for 15 minutes
with only O2 flowing.
• Turn on the H2 so that both O2 and H2 are flowing. This combination will produce
steam from the combustion of the gases, and the wafers will undergo steam
oxidation. Let the wafers soak with steam for 30 minutes.
• Turn off the H2 to revert back to a dry oxidation. Let the wafers soak for 10 minutes
with only O2 flowing.
• Switch back to N2 only.
3. A different student should remove the wafer boat.
4. Each student should remove one wafer and hold it in the air for 10 - 20 seconds before
placing it into their wafer carrier. (The cool down time is essential to avoid melting of the
wafer carrier!)
5. The timekeeper should place the boat back into the furnace. Everyone should get some
experience handling the quartzware. Further practice is also encouraged. Later on, you'll
be doing things on your own without the 1:3 teacher student ratio - take advantage of the
instructor now.

What is the purpose of starting and stopping with a dry oxidation?

What are the mechanical and electrical differences between dry and wet thermally grown
oxide?
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ECE344 Fall 2003 Lab Manual

Starting Material Information

The following is the wafer spec sheet submitted to them for our wafers. Be sure to record the
parameters for the starting material (substrate and epitaxial layer).
An epitaxial layer is a thin layer of single crystal Si grown on the much thicker single crystal
Si substrate. The doping of the "epi-layer" is generally different in type and/or concentration
from that of the substrate. –Note: the wafers used in lab do not have an epi layer.
Supplier: Silicon Quest, International
1230 Memorex Drive
Santa Clara, CA 95050
408.496.1000
http://www.siliconquest.com

Manufacturer: MEMC

substrate units
resistivity 1-10 Ω-cm
doping material Phosphorus
thickness 475-550 µm
orientation (100)

Determine the background doping of the substrate using the ρ vs. N graph in the GT section
(GT-1). Enter the background doping for the substrate in your electronic logsheet file at the
first opportunity.

NC = ____________ cm-3 (from GT-1 and starting material information)

What are the advantages of using (100) orientated wafers? When would (111) orientation be
preferred?

What are epitaxial layers used for?

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ECE344 Fall 2003 Lab Manual

PHOTORESIST 1 PRE-LAB REPORT

These questions are to be turned in before beginning the first photoresist patterning of the IC
wafer.

1. Draw a flow chart of the basic positive PR process used for opening windows in
unpatterned oxide for ECE 344. This includes etching the oxide and removing the PR.
Use concise descriptions or names for each significant step. Refer to Appendices C and
G, and note that for the standard PR process you do not use step C.2.12, which is for
image reversal. You will be using Acetone for PR removal. For those who do not know
what is meant by a flow chart, an example is shown. Just enough detail should be
included to allow you or some other ECE 344 graduate to reproduce the process a year
from now without the benefit of the lab manual excerpts we post in the lab. For the
amount of detail we are looking for, your flowchart should fit on one page. It should also
contain three conditional loops. (For example, see the one below for PR residue.)
 21
ECE344 Fall 2003 Lab Manual

2. Determine the field oxide thickness of the wafer after each PR step. Use the oxidation
charts. Tabulate the results in an Excel spreadsheet.

Determine the oxide thickness for each test window after the wafer is finished
processing. Use the oxidation charts. Tabulate the results in an Excel spreadsheet.

Add another column to the spreadsheet and add the color of the oxide in that area. Use
GT-7 as a reference.

The surface plane of your silicon wafer is (100), so use the (100) curves.
Note: If, for example, a dry oxidation step is off the chart you may assume its contribution
is negligible. Such assumptions should always be clearly stated, however!

You may not have covered oxidation in lecture yet, so here is some help: The graphs
show thickness as a function of time, given as (t+τ). If there is already oxide present
on your wafer before a certain oxidation step, "τ" is the equivalent time required
under the current oxidation conditions (temperature, steam or dry...) to give that
oxide thickness. The oxidation step is of duration "t". To find the thickness after the
oxidation step, you need to use t+τ, and read the corresponding thickness off the
appropriate curve.

Here's an example: Suppose that you are to do a 12 minute steam oxidation at

1100° C, and there is already 0.19 µm oxide present. From the (100) curve on GT.6,
0.19 µm corresponds to T = 8 min. (In other words, it is as if you have already done 8
minutes in steam at 1100° C to give you the 0.19 microns already present.) Then add
t = 12 min to T = 8 min to get t+T=20 min. At t+T = 20 min, read the 1100° C curve to
get a final thickness of 0.34 µm. (Note that the value of T would be different for a
different temperature, or for dry oxidation.)

3. The test instruments in the lab are limited to 200V. Will the breakdown voltage of the field
oxide (the oxide which is never etched) exceed this figure when you complete the
processing of your devices? Assume that the oxide will breakdown in an electric field of
107 V/cm (a conservative figure). Show your work.

4. Outline the alignment procedure used by the UltraTech 1000WF stepper. Categorize the
steps as either mechanical or optical.
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ECE344 Fall 2003 Lab Manual

Degrease the IC Wafer and Tweezers.

Cleanliness is extremely important. Tweezers and wafers should always be degreased at the
beginning of a processing session. Appendix C of the paper version describes the
degreasing procedure and is posted in the wet lab. Do not take paper into the wetlab, please.

PR 1 - Open Windows for First Diffusion

1. Follow the procedure for putting a patterned layer of photoresist on the wafer given in
appendix D of the paper version. (For the basic positive PR process, the image reversal
step C.2.12 is not used.)

2. Etch the oxide using 6NH4F:1HF (BOE) for 5.5 minutes. Slowly agitate the wafer carrier
back and forth during the etch. Do NOT splash! Rinse in DI water thoroughly, and N2 dry.
Wet etching requires the diffusion of the etchant to the surface and the diffusion of the
reaction products away from the surface. The smallest windows on the wafer will etch at
a rate closer to that of the large test areas with a little rotational agitation.

When coming out of the etch it is important to let the wafer carrier drip for a few seconds
while no more than a few centimeters above the acid. Tilting the carrier in two opposing
directions also helps return more acid to its container. This not only keeps the DI rinses
cleaner, but also minimizes the depletion of the acid container.

Is wet etching of SiO2 isotropic or anisotropic? What consequences will this have on
linewidths? How will this affect the different devices?
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ECE344 Fall 2003 Lab Manual

3. Use the hot point probe (see Appendix E) in the upper right window of the test areas to
check for complete oxide removal. You may want to check in 5 areas such as this:

X X X

This will ensure uniformity in etching by mapping over the entire wafer.
If no definitive reading (a few nanoamps or more) is obtained, etch in 30 second
intervals until oxide is removed. Do not etch for more than 6 minutes without consulting
your instructor.

What sign should the ammeter reading be?

4. Always follow up with a microscope inspection to insure that all the windows to be
opened through the oxide are indeed etched to bare silicon. The test area should be
uniform in color (metallic grey) and all the windows should match it.
5. Record the wafer type (p or n) determined using the hot point probe.

Type = ________.

6. Initial PR Removal: Hold your wafer level over the waste acetone/IPA container (with the
lid off) and squirt acetone on the wafer until it begins to flow off the edges. Let it dissolve
the PR for 10-15 seconds before draining the acetone into the waste container. Repeat
until most of the PR is gone (~3 times).
7. Strip off any remaining PR residue by following the standard degreasing procedure
(Acetone, IPA, DI, IPA, N2 dry.) Make sure you remove residue where your tweezers
were.
8. Inspect the wafer under a microscope for PR residue. Go back and degrease if
necessary. Incomplete photoresist removal is the most common cause of furnace tube
contamination. Please inspect wafers thoroughly.
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ECE344 Fall 2003 Lab Manual

Boron Predeposition

1. Degrease the wafer.

2. Perform a 10-15 second etch in 50:1 DI:HF if it has been more than an hour since
opening the diffusion windows, DI rinse, and N2 dry.
3. Check the boron predep furnace and support equipment (i.e., gas flows and
temperature). The boron predep furnace should be at 950°C.
4. Follow the procedure for furnace loading in appendix G of the paper version. Use the
Boron predep furnace and load the wafer so that the patterned side is facing the nearest
BN wafer. Be sure to record which position your wafer is in (see Appendix G.4). Don’t
forget the stainless steel endcaps!
5. After a 15-minute predeposition at 950°C, unload your wafer.
6. Use the Veeco four-point probe to get a rough idea of the sheet resistance. Consult the
instructor if it's outside the range 70-120 ohms/square, you may have to return the wafer
to the furnace. Note: The correction factor was determined for the smaller of the four
point probe windows (second large window from left). Be sure "auto-penetrate" is on. If
the Veeco reads that the conduction type is still N, then verify it with the hot point probe.
Trust the hot point probe more.

Rs=__________ ohms/square.

How is boron deposited on the wafer during the predep? What is the boron solid source
composed of?

Note: The BN source transfers boron to the wafer via B2O3. The B2O3 reacts with the silicon
to form a heavily doped SiO2 layer (borosilicate glass), with a B:Si alloy layer at the BSG – Si
interface. The BSG is easily removed with BOE, but the B:Si layer must be oxidized
chemically before it can be removed with the BOE.
This transfer of boron using B2O3 is the ideal case for the ECE344 lab, but can be greatly
accelerated by the presence of H2 or H2O. The hydrogen reacts with B2O3 to form HBO2
(meta-boric acid), which has a vapor pressure ~2X that of B2O3. The higher vapor pressure
of the metaboric acid accelerates the growth rate of BSG, therefore requiring a longer BSG
etch.
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ECE344 Fall 2003 Lab Manual

Remove Borosilicate Glass

1. Clean the wafer for the drive diffusion and testing using the following procedure. (The
idea here is to remove the borosilicate glass and any elemental boron formed on the
wafer surface during predep.) The original thermally grown oxide is not removed, but it is
etched slightly. Check with your TA to see if there are additional instructions.
• Remove the borosilicate glass by placing the wafer in the 50:1 DI:HF oxide etch for
15 seconds. Follow with a thorough DI rinse.
• Immerse the wafer in 1 H2SO4 : 1 HNO3 for 10 minutes to oxidize the Si:B layer.
• Rinse thoroughly with DI water and return to the 50 DI:1 HF oxide etch for 30
seconds to remove the oxidized boron. If HNO3 is transferred to the HF, it becomes
a silicon etch.
• Wash very thoroughly in DI water and dry carefully with N2.
2. Perform a hot-point probe measurement on any open region in the test area of the wafer.
You may want to map the wafer again for a more thorough test. Record whether it is P or
N type. (Refer to Appendix E in the paper version.) Also, make sheet resistance
measurements on the wafer with the four point probe as before. Consult Appendix F in
the paper version if necessary.
• Boron predep. Type ____________ Rs1 = ____________ ohms/sq.
• Enter your Rs value and furnace boat position into your logsheet ASAP.
• The sheet resistance after the boron predep should be between 70 and 120
ohms/square. If the measured value is out of this range consult your instructor. He or
she may have you return your wafer to the boron predep furnace for an additional 10
minutes depending on the how far it's off. If this is required, the subsequent
borosilicate glass removal times may be reduced proportionately.
• Did the Borosilicate glass affect the four-point probe measurement?

What is borosilicate glass?

Boron Drive

1. Have your instructor check the boron drive furnace and support equipment (i.e., gas
flows). The furnace should be at 1100°C.
2. Degrease your wafer using the instructions in Appendix C of the paper version.
3. Insert wafer into boron drive furnace using Appendix G of the paper version as a guide.
4. Perform the following drive recipe at T = 1100°C. (20 minutes total drive time).
• Dry oxygen drive for 10 minutes.
• Steam drive for 30 minutes.
• Back to a dry drive for 5 minutes.

There are multiple processes occurring during the boron drive. What are they?
26
ECE344 Fall 2003 Lab Manual

PR2 - Open Windows for Phosphorus Predeposition

Dark field masks are mostly dark when held up to a light. Since we want the holes in the
chrome layer on the mask to be transferred as holes in the PR, a positive photoresist is
needed. AZ5214 PR is inherently a positive resist so processing is relatively simple and
robust. The drawback of a dark field is that, since its mostly dark, you can't see much of the
underlying wafer with which you are to align - for contact aligning, this is important. However,
since we are using the steppers, this is of no consequence to the process.
Light field masks, being mostly clear, are easily aligned with the underlying wafer, but for
masks 1 through 4 a negative PR would need to be used. For these steps we need the
relatively sparse chrome regions transferred to the wafer as openings in the PR. With
AZ5214E PR this image reversal is possible, but it is a more complicated process and
sensitive to more variables. See Appendix D of the paper version.

1. Use the photoresist process to transfer the pattern from mask 2 into the oxide. Note that
this time there is a pattern to which to align, and Run Mode 2 is used. Use an oxide etch
time of 6 minutes before checking with the hot point probe for etch completeness. (Be
sure to use the proper etch solution for the oxide.) Expose the PR to a 150mW-sec/cm2
dose of ultraviolet energy (this has been determined empirically to obtain the best
resolution). Don't forget to complete the pattern transfer by removing the PR (as stated in
Appendix D of the paper version).

The hot point probe measurement should always be done in a region of the test area
which originally had the thickest oxide to be etched. There are two oxide thicknesses
present on the wafer at this point. For subsequent mask layers there will be a larger
number of various thicknesses.

The hot point probe measurement alone is NOT a sufficient condition to stop etching.
The wafer should always be inspected under a microscope (preferably without filtered
light.) Check many places on the wafer to verify that all the windows which are supposed
to be open are uniform in appearance and identical in color to the hot point probe test
area for that layer. Of course, the inspection requires familiarity with the mask set. Study
the mask set so you know what to expect.
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ECE344 Fall 2003 Lab Manual

2. Measure the sheet resistance of the boron diffusion with the four point probe using the
leftmost window just opened for the phosphorus diffusion (once again, you may choose
to map the wafer). You may ignore the fact that a slightly different correction factor
should be used because this boron tub is 200 microns larger on a side. The larger size
should result in a smaller measurement, but you will actually get a reading which is
approximately double the previous measurement. Why?

Wafers with PR on them should NOT be probed with the four point probe. Poor aim can
render the tips insulating and thereby yield false results to several students.

Rs = _________ ohms/square.

Phosphorus Predeposition Diffusion

1. Degrease one more time and inspect carefully for complete PR removal. Contamination
of the furnace can affect more than just your wafer. In addition to the wafers of innocent
students, there is several thousands of dollars worth of quartzware and source wafers
which could be ruined.
2. If it has been more than an hour since opening the diffusion windows, perform a 10-15
second etch in 50:1 DI:HF, DI rinse, and N2 dry.
3. Perform a phosphorus predeposition diffusion at 1000°C for 25 minutes. The gases are
switched for you. Nitrogen flows at the standby rate for the first 15 minutes, then switches
to oxygen for the remaining time (it leaves the nitrogen on the entire time). A low oxygen
concentration (~5%) is used in order to minimize the phosphorus silicide formation
described in 7.12 of Anner. The contribution to the field oxide thickness may be ignored
for prediction purposes. Record the actual flow rates in your electronic logsheet.
28
ECE344 Fall 2003 Lab Manual

4. Use the Veeco four point probe to get a rough idea of the sheet resistance. Consult the
instructor if it’s outside the range 10-40 ohms/ . Be sure "auto-penetrate" is on and use
the correct test area.

Don't worry if the N and P lights flash - the Veeco cannot reliably determine the type for your wafer's surface
concentration.

Rs= _________ ohms/square.

Which area should you measure?

Remove Phosphosilicate Glass

1. Phosphosilicate glass is supposed to be considerably easier to remove than borosilicate

glass, but we'll use the same procedure to remove it. High surface concentrations of
phosphorus are detrimental to photoresist adhesion so it is imperative that we remove it
all.
• Remove the phosphosilicate glass by placing the wafer in the 50:1 DI:HF oxide etch
for 20 seconds. Follow with a thorough DI rinse.
• Immerse the wafer in 1 H2SO4 : 1 HNO3 for 10 minutes.
• Rinse thoroughly with DI water and return to the 50 DI:1 HF oxide etch for another 10
seconds.
• Wash very thoroughly in DI water and dry carefully with N2.
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ECE344 Fall 2003 Lab Manual

2. Re-measure the sheet resistance. Did it change? Enter it in the electronic logsheet
ASAP.

Rs= ________ ohms/square.

3. Use the hot point probe to verify that the largest test area (on left) has indeed been
changed back to N-type. Consult your instructor if it did not.

PR3 - Open Windows for Gate Oxidation

Use the photoresist process to transfer the pattern from mask 3 into the oxide. Use the 3-
minute bakeout option to help recover the loss of PR adhesion due to the high phosphorus
concentrations. Increasing the hard-bake time to 2 minutes may also aid the PR adhesion.
Use an oxide etch time of 6 minutes before checking with the hot point probe for etch
completeness. As in PR-2, expose the PR to a 150mW-sec/cm2 dose of ultraviolet energy.
There tends to be excessive undercutting during the oxide etch due to poor adhesion. What
consequences will this have on the devices?

Gate Oxidation

1. Degrease your wafer before this critical step. If we were going to employ one more RCA
clean in this process, this is where it would be. If time permits, we will perform another
RCA clean at this point. Ask your instructor.
2. Grow 250 Å of dry oxide at 1000°C in the newly opened windows. Use the gate oxidation
furnace. It's up to you to calculate the oxidation time. Use the <100> curve to figure out
the necessary oxidation time and check with the instructor to see if this is correct (it is
also a good idea to manually calculate the time using Grove’s model in GT-8). Check that
the O2 flow = 100. If it is not, notify your instructor. During the oxidation, take the
opportunity to familiarize yourself with the workstations and/or fill in your logsheet file.

Oxide Thickness Measurements

Since all the high temperature steps are completed, anytime you are waiting for other
equipment you should use the ellipsometer and thin film measurement system to measure all
the various oxide thicknesses on your wafer. The test areas should be sufficient for this
purpose except when you have unpatterned aluminum on the wafer. Consider this a "filler"
activity that MUST be completed in time for the final report.
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ECE344 Fall 2003 Lab Manual

PR4 - Open Contact Windows

1. Use the standard photoresist process to transfer the pattern from mask 4 into the oxide.
Use an oxide etch time of 6.5 minutes before checking with the hot point probe for etch
completeness. As in PR-1, expose the PR to a 150mW-sec/cm2 dose of ultraviolet
energy. Don't forget to follow- up with a thorough microscope inspection. An incomplete
etch here may result in device failure, particularly in the schottky diodes so check them
carefully. A short 15-30 second overetch after a positive inspection will help ensure good
contacts.
2. Measure the sheet resistances of the phosphorus and boron diffusions with the four point
probe.
• Rsboron= ________ Ω/

• RSphosphorus= ________Ω/

What β do you expect from your BJTs given the measured sheet resistances? How does this
compare with the β predicted from DIFCAD?

A Time for Contemplation

You are nearly finished! Congratulations. But… do you know what you have really done up
to this point? Now is a good time to think about all of the processing steps.
Try this: draw a cross-sectional diagram of the wafer for both a BJT and a FET. Draw and
label what occurs for each step (including oxide layer thicknesses, silicon consumption,
junction depths, etc.). Don’t forget to include the consumption of silicon during oxide growth!
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ECE344 Fall 2003 Lab Manual

Processing Report
The purpose of this report is to show that you know what has been going on inside the wafer
during processing. In addition, the questions have been designed to help you see how the
various processing steps are related to device parameters. This is a very important part of
process design. If something is not clear to you, ask! Completing this report should be
educational, not merely a contest!

1. Use Difcad to help construct a band diagram of your vertical BJTs at equilibrium. Show
the collector and emitter contacts (and everything in between) and depletion regions in
the diagram. You may neglect showing the base contact because it cannot be elegantly
presented in the same band diagram. Calculate the energy levels at several points in
each region of the structure.

Note that DIFCAD will only give you the net doping profile. You must use that information
to calculate the energy bands. This can easily be done by using an Excel spreadsheet,
but be careful about depletion regions! They are not so easily included, and must be
calculated and drawn in.

2. List all the processing reasons (other than contamination) you can think of that may
cause the real energy bands in your fabricated device to be different from what you
determined above. Understanding the limitations of the theories you use is almost as
important as the theories themselves. For each of the processing steps, think about what
actually goes on, but is not included in your DIFCAD calculations. (For example, why is
the base doping profile not the same as what is calculated in DIFCAD?)

3. Draw the cross section of one of your P-channel FETs. Include all significant regions
while the device is biased in saturation. Your diagram should show at least the following
items:
• lateral diffusion of dopants
• diffusion depths
• the channel
• depletion regions
• varying oxide thicknesses, labeled with thicknesses
• height variations of the silicon surface, due to consumption during oxidation
• some idea of lateral dimensions

The horizontal and vertical scales should not be the same. Why? You may use the (100)
oxidation curves or oxide thicknesses measured using the ellipsometer. Be sure to state
whether you are using the measured or calculated thicknesses.
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ECE344 Fall 2003 Lab Manual

4. Draw a detailed cross section of one of your BJTs unbiased and at equilibrium. Be sure
to state whether you are using the measured or calculated oxide thicknesses. Your
diagram should show at least the following:
• lateral diffusion of dopants
• diffusion depths
• depletion regions
• varying oxide thicknesses, labeled with thickness
• height variations of the silicon surface, due to consumption during oxidation
• some idea of lateral dimensions

5. The ECE 344 recipe compromises the performance between the three main transistor
types. In this question, you will explore the effects of processing parameter changes on
the performance of the different transistor types present on your wafer:
• Construct a table like the one below. Fill in the table by listing the effect that each
processing step has on the physical device parameters (after all processing is
completed) if the time or temperature is increased.

Note: xjC and xjE are the junction depths of the collector/base and emitter/base
junctions, respectively, Wb is the base width, and Ci is the capacitance of the
insulator in the gate of the FETs.

Note that some steps will not affect some parameters.

xjC xjE Wb |Nd-Na| in n- |Nd-Na| in p- Ci

type type
regions regions
Initial
Oxidation
Boron
Predep
Boron
Drive
Phosphorus
Predep
Gate
Oxidation
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ECE344 Fall 2003 Lab Manual

• Construct a second table like the following one. Fill in this table by listing the effect
that each physical device parameter has on the electrical performance
characteristics of the device (like Beta, Vt...) if the time or temperature is increased.
(Note: an N-channel MOSFET has an n-type source and drain.)

β of BJTs |Vt| of p-channel |Vt| of n-channel Rseries of p-

MOSFETs MOSFETs channel
MOSFET source
and drain
xjC

xjE

Wb

|Nd-Na| in n-type
regions
|Nd-Na| in p-type
regions
Ci

6. Use your tables from above to aid in determining specific changes to the recipe you would
make in order to improve the performance of each type of transistor (e.g. increase time of
_____ in order to....) (These should be changes to the processing parameters only, not to the
mask layout.) Do not specify processes which you cannot perform in the ECE 344 facility
(e.g. ion implantation). Specifically:
• What change(s) would you make to improve the performance of the npn BJTs, and
how will that affect the performance of the P-MOSFETs and N-MOSFETs.
• What change(s) would you make to improve the performance of the P-MOSFETs,
and how will that affect the performance of the N-MOSFETs and npn BJTs.
• What change(s) would you make to improve the performance of the N-MOSFETs,
and how will that affect the performance of the P-MOSFETs and npn BJTs.
7. The ECE 344 device layouts compromise the performance of the three main transistor types
for the sake of processing tolerance. For each type of transistor (NPN BJTs, N-MOSFETs,
and P-MOSFETs) describe or illustrate a single change to the layout you would make in
order to improve its performance in some way. Briefly discuss the ramifications of your
proposed changes if they were implemented (e.g. less misalignment tolerance). Look closely
at the device cell mask set in Appendix I.
• BJTs: (Hint: The distance between contacts is relatively large. What does that do to
device performance? How could you change the layout to improve the performance?
What effect does that have on processing tolerance?)
• P-MOSFETs: (Hint: The gate oxide and metal overlap the Source and Drain regions.
What does that do to device performance? How could you change the layout to
improve the performance. What effect does that have on processing tolerance?)
• N-MOSFETs
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ECE344 Fall 2003 Lab Manual

Define Metal Contacts

The method for metal definition used in class is called lift-off. The photoresist is applied and
exposed using a darkfield mask to define areas where the aluminum will contact the silicon
and form contacts. Aluminum is then evaporated over the entire wafer, and the PR is then
removed. The aluminum will stick to the silicon, but will “lift off” where it has deposited on the
photoresist. There are problems with this method, mainly unwanted step coverage (i.e. the
aluminum forms a continuous layer over the entire wafer) due to sloping photoresist walls.
This will cause unwanted removal of the aluminum in contact areas. To overcome this
problem, undercutting of the photoresist is desired, and can be achieved by several methods.

1. If more than an hour has passed since PR-4, remove the native oxide with a 10-15
second dip in the 50:1 DI:HF, DI rinse, and N2 dry.
2. Spin photoresist onto the wafer as usual in preparation for exposure. As in PR-1, expose
the PR to an 150mW-sec/cm2 dose of ultraviolet energy through Mask 5.
3. <OPTIONAL>Before developing, perform a 3 minute soak in chlorobenzene (check with
your instructor to see if this step will be performed).
What is the chlorobenzene for? It forms a ‘skin’ on the top surface of the photoresist
which is less soluble in developer. Therefore, it develops more slowly than the PR
beneath, causing undercutting, which in turn reduces the possibility of step coverage and
the undesirable lift-off of the contacts.
Warning: chlorobenzene should not be inhaled. Perform this under the solvent hood
only.
4. Develop as normal.
5. Don't forget to follow-up with a thorough microscope inspection. Do not perform the
hardbake - it will only increase the amount of time required to remove the PR and lift off
the metal.

Aluminum Evaporation for Contacts

1. In the Varian evaporation system, load the wafer into the holder directly above the
aluminum (pattern side down), manually pump down and evaporate all the Aluminum as
per Appendix B in the paper version. Do not use the filaments in series. Approximately
2000 Å will be deposited.
2. Vent and remove wafer for inspection.

Lift-off Aluminum

1. Place the wafer into the container marked Lift-off Acetone.

2. Make sure the wafer is covered entirely with acetone and soak for 10 minutes. The
aluminum will begin to ‘peel off.’ Slight agitation of the container will help lift-off the
metal. If the aluminum has not completely lifted off after 10 minutes, take a swab and
gently wipe the wafer to remove the metal.
3. Degrease your wafer after all excess aluminum has lifted off.
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ECE344 Fall 2003 Lab Manual

Anneal Contacts

1. Adjust N2 flow to 100 on the flowmeter if it is not there already.

2. Load your wafer into the annealing furnace for 15 minutes at T =475-500°C.
3. When the 15 minutes have elapsed, remove the wafer from the furnace and place it in
your wafer carrier. Be sure that the boat pushrod is fully inserted into the quartz tube so
that it will not be broken. Return the empty boat to the front of the furnace tube.

Electrical Testing

Electrical testing will be accomplished in two waves. Since there are only 5 test stations, only
5 in each section will make measurements on the basic device types at a time. When
everyone is done with the set of fundamental semiconductor measurements, the remainder
of the semester will be spent on more advanced measurements.
Review appendix J in the paper version for tips on the proper operation of the probers. Refer
to the World Wide Web or the ICS Tutorial for help in using ICS.

There is also information there about

• which BJTs to test
• which FETs to test,
• which Capacitors to test,
• which Diodes to test,
as well as which probes to place on the contacts. It is suggested that you start with the
devices that are most likely to work (FETs and capacitors).
Understand and fill in each data set in the my_models.mdl model file with data from 3 of each
device type (although the number may be modified depending on time constraints – ask your
instructor). The three types of FETs it takes to fill in one model are sufficient for the first round
of testing.
One part of the measurement setups not covered well in the ECE 340 text are the gummel
plots for the BJTs.
Gummel plots are simply the display of the natural log of base and collector currents as Vbe
and Vce(=Vbe) are varied simultaneously . The collector and base potentials are kept identical
and the currents measured independently as the emitter potential is swept. The base current
will display the characteristic regions of thermal recombination-generation dominance at low
currents (I=Io e(qV/2kT)), quasi-ideal (I=Io e(qV/kT)), and current limiting ohmic effects at high
currents. The corresponding collector current through these ranges can tell a lot about how
useful the BJT will be for certain applications. The ratio of the two currents, beta, will usually
have a peak somewhere in the middle, the broader the better. It can tell the circuit designer
how sensitive the device is to the bias point.
The additional advanced testing will be handled using a handout when it seems clear just
how much time will be available.
36
ECE344 Fall 2003 Lab Manual

FINAL REPORT
The questions here are intended to help you learn about the devices you fabricated and
tested. Of course, they are also used as a means for assessing what you have learned. If
something is not clear to you, ask! Completing this report should be educational, not merely a
contest!
NOTE: In this report, as in any engineering level report, state your assumptions clearly.
Making reasonable assumptions is OK, but you must clearly state and justify them. Full credit
cannot be given in cases where, say, the voltage reference direction is important, but not
stated. Pictures often help in clearing up such ambiguities. Device location information is also
important if verification of results is to be possible. Show all work in the written report.
This report will be submitted partially in electronic form. No printouts of the ICS files or your
logsheet file will be necessary except for your own benefit. In the questions that ask you to
generate plots in ICS, be sure to save the plots in your file. After completing the items below,
you are to submit your data files to your via email.
Even if your wafer didn't work or work completely, do the best you can with answering the
questions and completing the tasks below. We can't give partial credit for answers like "my
BJTs didn't work".

1. LOGSHEET: Enter or verify all the process variables in the logsheet on the web. In your lab
notebook, enter any observations and conclusions you can make from the data. Do not make
up numbers if you missed collecting some of them. The data will be used to demonstrate
Statistical Process Control concepts.

2. After fabrication of your FETs, the actual gate lengths are shorter than the designed gate
lengths as drawn using the CAD system. The diagram below shows the designed gate mask
and the gate region of one of your diffused p-channel FETs. The designed gate width drawn
on the CAD system is L, and L-∆L is the final (actual) gate length.

Note: the designed mask is not necessarily the same as the actual mask.

Designed Mask
(actual mask may differ)
L

Diffused FET
p source p drain
L-∆L
n-type silicon
 37
ECE344 Fall 2003 Lab Manual

a) Think about all of the steps that come between designing a mask using a CAD system
and the final (diffused) device. Why is the actual gate length shorter than the length in the
CAD drawing for the mask? (i.e., what causes ∆L?) There are several contributing
factors.
b) What happens if ∆L is greater than L? How does that show up while testing the device?
c) What was the shortest gate length device that worked on your wafer? What upper bound
does that place on ∆L? What is a reasonable lower bound?
d) For two FETs in the same device cell, nearly the same amount (∆L) is subtracted from
the gate length for each device. In other words, ∆L does not depend on L. It is possible to
determine the discrepancy between the actual and the as designed channel lengths from
measurements of two different FETs. Create plots (in ICS) of gm (transconductance) vs.
vg in the large and short FET setups. Use a transform to do the derivative (i.e., to
calculate gm). The slopes of the gm curves in the saturation region are functions of the
channel lengths. (Be careful about what the saturation region is!) The relationships may
be found in section 8.3.5 of Streetman. Find ∆L.

3. Ideality factor of diodes:

a) Create a plot called ideality in the Ifwd_vs_V test of the diodes setup to plot the ideality
factor, n, from equation 5-71 in section 5.6.2 of Streetman:

where V is the voltage across the junction, Io is the reverse leakage current, and n is the
ideality factor.

b) Plot n vs. current. Use GT.19 for the value of kT/q. Io may be taken as the leakage
current with a reverse bias of 1 volt (the value can be found on the data spreadsheet of
the test). Use the transform editor to create a plottable dataset for n and enter it into the
Y-data of a plot.
c) Why shouldn't you plot the ideality factor vs. voltage? (There is a practical reason related
to the way testing is done. Try it if it is not immediately obvious).
d) The voltage you measured for your diode includes the series resistance of the contacts
and the n and p-type material on each side of the junction in addition to the voltage
across the junction itself. The voltage used in equation 5-71 of Streetman should be only
the voltage across the junction, whereas the entire measured voltage was used in the
plot you created. Make a correction to the equation to take the series resistance into
account. The forward series resistance of your diode can be determined from the slope
of the I-V curve in the linear, high-current region. For each diode, use the value of the
resistance to make a new plot called ideality _corrected, which plots the ideality factor
vs. current, eliminating the voltage due to series resistance.
38
ECE344 Fall 2003 Lab Manual

e) What effect does correcting for the resistance have on your ideality plots?
f) What is the effect of using a smaller value for Io in your ideality plots?
g) What do expect to see in the ideality plots (see Streetman)? Do you see it?

4. For a one-sided step junction, the junction capacitance is given by

,
where A is the area, V is the applied voltage (V < 0 for reverse bias), and N is the doping on
the lighter-doped side.

For a one-sided junction with linear grading on the lighter-doped side, the junction
capacitance is given by

where G is the grade constant (slope of N at the junction). (See Streetman.) Real diffused
junctions are somewhere between these two cases.
a) What should the slope of a log(C) vs. log(Vo-V) curve be for a one-sided step junction?
b) What should the slope of a log(C) vs. log(Vo-V) curve be for a one-sided junction with
linear grading?
c) For each C-V plot of the pn junctions (in the diodes setup), plot log10(C) vs. log10(Vo-V)
using ICS, where V is referenced as a positive voltage under forward bias. Refer to the
band diagram in your Processing Report to make an initial guess for Vo. Improve your
estimate for the built-in voltage for each pn junction by extrapolating a plot of C(1/slope) vs.
V to the x-axis, where "slope" is the slope in the high voltage region of your first plot. Use
ICS to generate and fit the plot. Plug the new value for Vo back into the first plot and
iterate this process until you get the same value out of the second plot (within a few
percent). Note: if you cannot reasonably fit a line to the entire voltage range, use the high
voltage regions.
 39
ECE344 Fall 2003 Lab Manual
d) Compare the slopes of your log(C) vs. log(Vo-V) curves for the emitter/base and
collector/base junctions. What does this say about your junctions? Is it what you would
expect?

5. Export the data as an ASCII file and email it to your instructor. The deadline for this may be
before the written report.
6. Capacitor breakdown: Determine the breakdown field of the capacitors from your measured
breakdown voltage and the oxide thickness for each of the three methods of determining
oxide thickness. Use the oxide thickness as determined in the following three different ways.
Discuss any discrepancies between them. Use the oxide thickness:
a) predicted by the appropriate oxidation curves,
b) determined by the ellipsometer measurement,
c) determined by the thin film measurement system, and
d) calculated from your measured capacitance vs. voltage curves.

7. There is a great deal of information contained within your measured capacitance vs. voltage
curves. In this question, you will extract some of the information, including the doping level of
the silicon epi-layer. See Streetman or any other reference concerning MOS capacitors.
(Note that in this question, the capacitances are NOT per unit area, as they are in
Streetman.) You can find information about the capacitor area by using the interactive mask
set on the ECE344 WWW home page.
a) What is your measured value of the insulator capacitance, Ci?
b) What is your measured value of the total capacitance, Cmin, when the capacitor is biased
such that the depletion region is at maximum width?
c) What is happening in the portion of the C vs. V curve where C is not constant? (i.e., what
is changing in the device that causes the capacitance to vary?)
d) From your values of Ci and Cmin, what is the value of the depletion capacitance, Cd, when
the capacitor is biased such that the depletion region is at maximum width?
e) From Cd, what is the maximum depletion width, wm, of the capacitor?
f) At what measured value of voltage does the capacitor reach maximum depletion width,
and what parameter of an FET should that voltage correspond to?
g) From the maximum depletion width, wm, find the doping concentration, Nd, of the silicon
epi-layer.
h) How would your measured C vs. V curve be different if:
• The epi-layer was p-type?
• the doping level was higher?
• the gate oxide was thicker?
• How do the threshold voltages from the FET measurements compare with those from
the capacitor B measurements? Which would you trust more?
• Compared to the single diffused diodes you measured (C-B junction), what
differences would you expect if you:
(1) used a substrate contact several device cells away?
(2) measured the round Schottky diode?
40
ECE344 Fall 2003 Lab Manual

8. List all the effects you can think of which cause the geometry of the various regions of the
final devices to differ from the CAD layout. (Note that not all of these reasons will be
processing mistakes.)

9. DIODES: Compare the values of the built-in voltage obtained in the following three ways:
a) Vo determined from your capacitance data (log[C] vs. log [Vo-V] curves.)
b) Vo determined by extrapolating a line from the linear portion of the forward I-V
characteristics of the junctions.
c) Vo predicted by the BJT band diagram in your processing report.
d) Compare and discuss ALL the possible reasons you can think of for discrepancies
between the background doping levels determined from the manufacturer's stated value
of the starting epi-layer resistivity and the capacitor measurements.
 41
ECE344 Fall 2003 Lab Manual

References

1. SUPPLEMENTARY REFERENCES ON OXIDATION.

o M. Atalla, E. Tannenbaum, E. J. Scheibner, "Stabilization of Si Surfaces by Thermally Grown Oxides," Bell
System Tech. J., 38, 749 (May 1959). (Same as Bell Telephone Monograph 3254, see especially pp. 15
and 16.)
o E. Deal and A. S. Grove, "General Relationship for the Thermal Oxidation of Silicon," J.A.P., 36, 37770
(December 1965).
o J. Frosch and L. Derick, "Surface Protection and Selective Masking During Diffusion in Si," J. Electrochem.
Soc., l04, 547 (1957).
o Burger and Donovan, Fundamentals of Silicon Integrated Device Technology, Vol. 1, pp. 93- 98.
o Ghandhi, The Theory and Practice of Microelectronics, Ch. 6.
o Glaser/Subak-Sharpe, Integrated Circuit Engineering, Section 5.6.
o Anner, Planar Processing Primer, Ch 5.
2. SUPPLEMENTARY REFERENCES FOR 4-POINT PROBE MEASUREMENTS.
o Anner, Planar Processing Primer, Sections 3.4 - 3.11.
o Gibbons, "Ion Implantation in Semiconductors - Part I, Range Distribution Theory and Experiments," Proc. IEEE
56, (1968), p. 295.
o Ghandhi, Chapters 4 and 5.
o Bond and F. M. Smits, "Interference Microscope for Measurement of Extremely Thin Surface Layers," BSTJ, 35,
1209 (Sept. 1956). (Same as BT Monograph 3682.)
3. METAL-SEMICONDUCTOR SYSTEMS
o Biondi, Transistor Technology, 3, 1958, Chapter 7.
o Warner and Fordemwalt, eds., Integrated Circuits, Design Principles and Fabrication, 1965, pp. 307-309.
4. P-N JUNCTION CAPACITANCE
o SEEC, Vol. 2, Section 5.4, pp. 93-96.
5. VACUUM TECHNOLOGY
o Van Atta, Vacuum Science and Engineering, McGraw-Hill.
o Brunner and Batzer, Practical Vacuum Technique, Reinhold.
o Guthrie, Vacuum Technology, Wiley.
6. THEORETICAL
o Smits, "Formation of Junction Structures by Solid State Diffusion," Proc. IRE, 43, 1049 (1958). (Same as BT
Monograph 3136.)

7. DIFFUSION
o D'Asaro, "Diffusion and Oxide Masking in Si by the Box Method," S.S.E., 1, 3 (1960). (Same as BT Monograph
3704.)
o Goldsmith, Olmstead, and Scott, Jr., “Boron Nitride as a Diffusion Source for Silicon," RCA Review, 28, 2, pp.
344-350 (June, 1967).
o Anner, Planar Processing Primer, Chapters 6 and 7.

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SEMICONDUCTOR TECHNICAL DATA by P2N2222A/D

 

NPN Silicon
COLLECTOR

1

2
BASE

3
EMITTER

MAXIMUM RATINGS
Rating Symbol Value Unit 1
2
Collector – Emitter Voltage VCEO 40 Vdc 3

Collector – Base Voltage VCBO 75 Vdc

CASE 29–04, STYLE 17
Emitter – Base Voltage VEBO 6.0 Vdc TO–92 (TO–226AA)
Collector Current — Continuous IC 600 mAdc
Total Device Dissipation @ TA = 25°C PD 625 mW
Derate above 25°C 5.0 mW/°C
Total Device Dissipation @ TC = 25°C PD 1.5 Watts
Derate above 25°C 12 mW/°C
Operating and Storage Junction TJ, Tstg – 55 to +150 °C
Temperature Range

THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Ambient RqJA 200 °C/W
Thermal Resistance, Junction to Case RqJC 83.3 °C/W

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)

Characteristic Symbol Min Max Unit

OFF CHARACTERISTICS
Collector – Emitter Breakdown Voltage V(BR)CEO 40 — Vdc
(IC = 10 mAdc, IB = 0)
Collector – Base Breakdown Voltage V(BR)CBO 75 — Vdc
(IC = 10 mAdc, IE = 0)
Emitter – Base Breakdown Voltage V(BR)EBO 6.0 — Vdc
(IE = 10 mAdc, IC = 0)
Collector Cutoff Current ICEX — 10 nAdc
(VCE = 60 Vdc, VEB(off) = 3.0 Vdc)
Collector Cutoff Current ICBO µAdc
(VCB = 60 Vdc, IE = 0) — 0.01
(VCB = 60 Vdc, IE = 0, TA = 150°C) — 10
Emitter Cutoff Current IEBO — 10 nAdc
(VEB = 3.0 Vdc, IC = 0)
Collector Cutoff Current ICEO — 10 nAdc
(VCE = 10 V)
Base Cutoff Current IBEX — 20 nAdc
(VCE = 60 Vdc, VEB(off) = 3.0 Vdc)

Motorola Small–Signal Transistors, FETs and Diodes Device Data 1

 Motorola, Inc. 1996
P2N2222A
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)
Characteristic Symbol Min Max Unit
ON CHARACTERISTICS
DC Current Gain hFE —
(IC = 0.1 mAdc, VCE = 10 Vdc) 35 —
(IC = 1.0 mAdc, VCE = 10 Vdc) 50 —
(IC = 10 mAdc, VCE = 10 Vdc) 75 —
(IC = 10 mAdc, VCE = 10 Vdc, TA = –55°C) 35 —
(IC = 150 mAdc, VCE = 10 Vdc)(1) 100 300
(IC = 150 mAdc, VCE = 1.0 Vdc)(1) 50 —
(IC = 500 mAdc, VCE = 10 Vdc)(1) 40 —
Collector – Emitter Saturation Voltage(1) VCE(sat) Vdc
(IC = 150 mAdc, IB = 15 mAdc) — 0.3
(IC = 500 mAdc, IB = 50 mAdc) — 1.0
Base – Emitter Saturation Voltage(1) VBE(sat) Vdc
(IC = 150 mAdc, IB = 15 mAdc) 0.6 1.2
(IC = 500 mAdc, IB = 50 mAdc) — 2.0

SMALL– SIGNAL CHARACTERISTICS

Current – Gain — Bandwidth Product(2) fT 300 — MHz
(IC = 20 mAdc, VCE = 20 Vdc, f = 100 MHz)
Output Capacitance Cobo — 8.0 pF
(VCB = 10 Vdc, IE = 0, f = 1.0 MHz)
Input Capacitance Cibo — 25 pF
(VEB = 0.5 Vdc, IC = 0, f = 1.0 MHz)
Input Impedance hie kΩ
(IC = 1.0 mAdc, VCE = 10 Vdc, f = 1.0 kHz) 2.0 8.0
(IC = 10 mAdc, VCE = 10 Vdc, f = 1.0 kHz) 0.25 1.25
Voltage Feedback Ratio hre X 10– 4
(IC = 1.0 mAdc, VCE = 10 Vdc, f = 1.0 kHz) — 8.0
(IC = 10 mAdc, VCE = 10 Vdc, f = 1.0 kHz) — 4.0
Small–Signal Current Gain hfe —
(IC = 1.0 mAdc, VCE = 10 Vdc, f = 1.0 kHz) 50 300
(IC = 10 mAdc, VCE = 10 Vdc, f = 1.0 kHz) 75 375
Output Admittance hoe mmhos
(IC = 1.0 mAdc, VCE = 10 Vdc, f = 1.0 kHz) 5.0 35
(IC = 10 mAdc, VCE = 10 Vdc, f = 1.0 kHz) 25 200
Collector Base Time Constant rb′Cc — 150 ps
(IE = 20 mAdc, VCB = 20 Vdc, f = 31.8 MHz)
Noise Figure NF — 4.0 dB
(IC = 100 mAdc, VCE = 10 Vdc, RS = 1.0 kΩ, f = 1.0 kHz)

SWITCHING CHARACTERISTICS
Delay Time (VCC = 30 Vdc, VBE(off) = –2.0 Vdc, td — 10 ns
Rise Time IC = 150 mAdc, IB1 = 15 mAdc) (Figure 1) tr — 25 ns
Storage Time (VCC = 30 Vdc, IC = 150 mAdc, ts — 225 ns
IB1 = IB2 = 15 mAdc) (Figure 2)
Fall Time tf — 60 ns

1. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2.0%.

2. fT is defined as the frequency at which |hfe| extrapolates to unity.

2 Motorola Small–Signal Transistors, FETs and Diodes Device Data

 P2N2222A
SWITCHING TIME EQUIVALENT TEST CIRCUITS

+ 30 V + 30 V
1.0 to 100 µs, 1.0 to 100 µs, 200
200
+16 V DUTY CYCLE ≈ 2.0%
+16 V DUTY CYCLE ≈ 2.0%

0 0
1 kΩ –14 V 1k CS* < 10 pF
–2 V CS* < 10 pF
< 2 ns < 20 ns
1N914

Scope rise time < 4 ns –4 V

*Total shunt capacitance of test jig,
connectors, and oscilloscope.
Figure 1. Turn–On Time Figure 2. Turn–Off Time

1000
700
500 TJ = 125°C
hFE , DC CURRENT GAIN

300
200
25°C
100
70
–55°C
50
30 VCE = 1.0 V
20 VCE = 10 V

10
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100 200 300 500 700 1.0 k
IC, COLLECTOR CURRENT (mA)

Figure 3. DC Current Gain

VCE , COLLECTOR–EMITTER VOLTAGE (VOLTS)

1.0
TJ = 25°C
0.8

0.6 IC = 1.0 mA 10 mA 150 mA 500 mA

0.4

0.2

0
0.005 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50
IB, BASE CURRENT (mA)

Figure 4. Collector Saturation Region

Motorola Small–Signal Transistors, FETs and Diodes Device Data 3

P2N2222A
200 500
IC/IB = 10 VCC = 30 V
300 IC/IB = 10
100 TJ = 25°C
200 t′s = ts – 1/8 tf IB1 = IB2
70 tr @ VCC = 30 V
50 TJ = 25°C
td @ VEB(off) = 2.0 V
100
td @ VEB(off) = 0
t, TIME (ns)

30

t, TIME (ns)
70
20 tf
50
30
10
7.0 20
5.0
10
3.0 7.0
2.0 5.0
5.0 7.0 10 20 30 50 70 100 200 300 500 5.0 7.0 10 20 30 50 70 100 200 300 500
IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)

Figure 5. Turn – On Time Figure 6. Turn – Off Time

10 10
RS = OPTIMUM f = 1.0 kHz
IC = 1.0 mA, RS = 150 Ω RS = SOURCE
8.0 RS = RESISTANCE 8.0
500 µA, RS = 200 Ω IC = 50 µA
NF, NOISE FIGURE (dB)

NF, NOISE FIGURE (dB)

100 µA, RS = 2.0 kΩ 100 µA
6.0 50 µA, RS = 4.0 kΩ 6.0 500 µA
1.0 mA

4.0 4.0

2.0 2.0

0 0
0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 50 100 200 500 1.0 k 2.0 k 5.0 k 10 k 20 k 50 k 100 k
f, FREQUENCY (kHz) RS, SOURCE RESISTANCE (OHMS)

Figure 7. Frequency Effects Figure 8. Source Resistance Effects

f T, CURRENT–GAIN BANDWIDTH PRODUCT (MHz)

30 500
VCE = 20 V
20 TJ = 25°C
300
Ceb
CAPACITANCE (pF)

10 200

7.0

5.0
100
Ccb
3.0 70

2.0 50
0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
REVERSE VOLTAGE (VOLTS) IC, COLLECTOR CURRENT (mA)

Figure 9. Capacitances Figure 10. Current–Gain Bandwidth Product

4 Motorola Small–Signal Transistors, FETs and Diodes Device Data

 P2N2222A
1.0 +0.5
TJ = 25°C

0.8 0 RqVC for VCE(sat)

COEFFICIENT (mV/ °C)

V, VOLTAGE (VOLTS)

VBE(sat) @ IC/IB = 10
1.0 V – 0.5
0.6
VBE(on) @ VCE = 10 V – 1.0
0.4
– 1.5

0.2
– 2.0 RqVB for VBE
VCE(sat) @ IC/IB = 10
0 – 2.5
0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1.0 k 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500
IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)

Figure 11. “On” Voltages Figure 12. Temperature Coefficients

Motorola Small–Signal Transistors, FETs and Diodes Device Data 5

P2N2222A
PACKAGE DIMENSIONS

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
A B
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
R 4. DIMENSION F APPLIES BETWEEN P AND L.
DIMENSION D AND J APPLY BETWEEN L AND K
P MINIMUM. LEAD DIMENSION IS UNCONTROLLED
IN P AND BEYOND DIMENSION K MINIMUM.
L
SEATING F
PLANE K INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.175 0.205 4.45 5.20
D B 0.170 0.210 4.32 5.33
C 0.125 0.165 3.18 4.19
J D 0.016 0.022 0.41 0.55
X X F 0.016 0.019 0.41 0.48
G G 0.045 0.055 1.15 1.39
H H 0.095 0.105 2.42 2.66
SECTION X–X J 0.015 0.020 0.39 0.50
V C K 0.500 ––– 12.70 –––
L 0.250 ––– 6.35 –––
N 0.080 0.105 2.04 2.66
1 N P ––– 0.100 ––– 2.54
R 0.115 ––– 2.93 –––
N V 0.135 ––– 3.43 –––

STYLE 17:
CASE 029–04 PIN 1. COLLECTOR
2. BASE
(TO–226AA) 3. EMITTER
ISSUE AD

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*P2N2222A/D*
6 ◊ P2N2222A/D
Motorola Small–Signal Transistors, FETs and Diodes Device Data



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SEMICONDUCTOR TECHNICAL DATA by MTP2955V/D

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P–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
TMOS V is a new technology designed to achieve an on–resis- 12 AMPERES
tance area product about one–half that of standard MOSFETs. This 60 VOLTS
new technology more than doubles the present cell density of our RDS(on) = 0.230 OHM
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and TM
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients. D

New Features of TMOS V

• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology G
• Faster Switching than E–FET Predecessors

Features Common to TMOS V and TMOS E–FETS S CASE 221A–09, Style 5

• Avalanche Energy Specified TO–220AB
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E–FET

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

Rating Symbol Value Unit
Drain–to–Source Voltage VDSS 60 Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc
Gate–to–Source Voltage — Continuous VGS ± 15 Vdc
Gate–to–Source Voltage — Non–Repetitive (tp ≤ 10 ms) VGSM ± 25 Vpk

Drain Current — Continuous ID 12 Adc

Drain Current — Continuous @ 100°C ID 8.0
Drain Current — Single Pulse (tp ≤ 10 µs) IDM 42 Apk
Total Power Dissipation PD 60 Watts
Derate above 25°C 0.40 W/°C

Operating and Storage Temperature Range TJ, Tstg – 55 to 175 °C

Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C EAS 216 mJ
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.0 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case RθJC 2.5 °C/W
Thermal Resistance — Junction to Ambient RθJA 62.5

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

REV 3

 Motorola TMOS
Motorola, Inc. 1997 Power MOSFET Transistor Device Data 1
MTP2955V
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (3) V(BR)DSS
(VGS = 0 Vdc, ID = 0.25 mAdc) 60 — — Vdc
Temperature Coefficient (Positive) — 58 — mV/°C
Zero Gate Voltage Drain Current IDSS µAdc
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) — — 100
Gate–Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS — — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage (Cpk ≥ 2.0) (3) VGS(th)
(VDS = VGS, ID = 250 µAdc) 2.0 2.8 4.0 Vdc
Threshold Temperature Coefficient (Negative) — 5.0 — mV/°C
Static Drain–to–Source On–Resistance (Cpk ≥ 1.5) (3) RDS(on) Ohm
(VGS = 10 Vdc, ID = 6.0 Adc) — 0.185 0.230

Drain–to–Source On–Voltage VDS(on) Vdc

(VGS = 10 Vdc, ID = 12 Adc) — — 2.9
(VGS = 10 Vdc, ID = 6.0 Adc, TJ = 150°C) — — 2.5
Forward Transconductance (VDS = 10 Vdc, ID = 6.0 Adc) gFS 3.0 5.0 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance Ciss — 550 700 pF
Output Capacitance (VDS = 25 Vdc,
Vdc VGS = 0 Vdc,
Vdc
Coss — 200 280
f = 1.0 MHz)
Reverse Transfer Capacitance Crss — 50 100
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time td(on) — 15 30 ns
Rise Time (VDD = 30 Vdc,
Vd ID = 12 Adc,
Ad tr — 50 100
VGS = 10 Vdc
Vdc,
Turn–Off Delay Time RG = 9.1 Ω)) td(off) — 24 50
Fall Time tf — 39 80
Gate Charge QT — 19 30 nC

((VDS = 48 Vdc,
Vd , ID = 12 Adc,
Ad , Q1 — 4.0 —
VGS = 10 Vdc) Q2 — 9.0 —
Q3 — 7.0 —

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (1) VSD Vdc
(IS = 12 Adc, VGS = 0 Vdc)
— 1.8 3.0
(IS = 12 Adc, VGS = 0 Vdc, TJ = 150°C)
— 1.5 —
Reverse Recovery Time trr — 115 — ns

((IS = 12 Adc,
Ad , VGS = 0 Vdc,
Vd , ta — 90 —
dIS/dt = 100 A/µs) tb — 25 —
Reverse Recovery Stored Charge QRR — 0.53 — µC

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance LD nH
(Measured from the drain lead 0.25″ from package to center of die) — 4.5 —

Internal Source Inductance LS nH

(Measured from the source lead 0.25″ from package to source bond pad) — 7.5 —
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values. Max limit – Typ
Cpk =
3 x SIGMA

2 Motorola TMOS Power MOSFET Transistor Device Data

 MTP2955V
TYPICAL ELECTRICAL CHARACTERISTICS

25 24
TJ = 25°C VGS = 10 V VDS ≥ 10 V TJ = – 55°C
9V 8V
21 100°C
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

20 25°C
18
7V 15
15
12
10 6V 9

6
5
5V
3

0 0
0 1 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

R DS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)

R DS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)

0.40 0.250
VGS = 10 V TJ = 25°C
0.35 0.225
VGS = 10 V
0.30 TJ = 100°C 0.200

0.25 0.175
25°C 15 V
0.20 0.150

0.15 – 55°C 0.125

0.10 0.100

0.05 0.075

0 0.050
0 3 6 9 12 15 18 21 24 0 3 6 9 12 15 18 21 24
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Current Figure 4. On–Resistance versus Drain Current
and Temperature and Gate Voltage

2.0 1000
RDS(on) , DRAIN–TO–SOURCE RESISTANCE

VGS = 0 V
1.8 VGS = 10 V
ID = 6 A
1.6
1.4 TJ = 125°C
I DSS , LEAKAGE (nA)
(NORMALIZED)

1.2
1.0 100 100°C

0.8
0.6
0.4
0.2
0 10
– 50 – 25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 5. On–Resistance Variation with Figure 6. Drain–To–Source Leakage

Temperature Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data 3

MTP2955V
POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.

1800
VDS = 0 V VGS = 0 V TJ = 25°C
1600
Ciss
1400
C, CAPACITANCE (pF)

Crss
1200
1000
800
Ciss
600
400 Coss
200 Crss
0
10 5 0 5 10 15 20 25
VGS VDS

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4 Motorola TMOS Power MOSFET Transistor Device Data

 MTP2955V
10 30 1000

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)

QT VDD = 30 V
9 27 ID = 12 A
8 24 VGS = 10 V
Q1 Q2
TJ = 25°C
7 VGS 21
100

t, TIME (ns)
6 18
tr
5 15 tf
td(off)
4 12 td(on)
10
3 ID = 12 A 9
2 TJ = 25°C 6
1 Q3 3
VDS
0 0 1
0 2 4 6 8 10 12 14 16 18 20 1 10 100
QT, TOTAL CHARGE (nC) RG, GATE RESISTANCE (OHMS)

Figure 8. Gate–To–Source and Drain–To–Source Figure 9. Resistive Switching Time

Voltage versus Total Charge Variation versus Gate Resistance

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

12
11 VGS = 0 V
TJ = 25°C
10
I S , SOURCE CURRENT (AMPS)

9
8
7
6
5
4
3
2
1
0
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define able operation, the stored energy from circuit inductance dis-
the maximum simultaneous drain–to–source voltage and sipated in the transistor while in avalanche must be less than
drain current that a transistor can handle safely when it is for- the rated limit and adjusted for operating conditions differing
ward biased. Curves are based upon maximum peak junc- from those specified. Although industry practice is to rate in
tion temperature and a case temperature (TC) of 25°C. Peak terms of energy, avalanche energy capability is not a
repetitive pulsed power limits are determined by using the constant. The energy rating decreases non–linearly with an
thermal response data in conjunction with the procedures increase of peak current in avalanche and peak junction tem-
discussed in AN569, “Transient Thermal Resistance–General
perature.
Data and Its Use.”
Although many E–FETs can withstand the stress of drain–
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM) to–source avalanche at currents up to rated pulsed current
nor rated voltage (VDSS) is exceeded and the transition time (IDM), the energy rating is specified at rated continuous cur-
(tr,tf) do not exceed 10 µs. In addition the total power aver- rent (ID), in accordance with industry custom. The energy rat-
aged over a complete switching cycle must not exceed ing must be derated for temperature as shown in the
(TJ(MAX) – TC)/(RθJC). accompanying graph (Figure 13). Maximum energy at cur-
A Power MOSFET designated E–FET can be safely used rents below rated continuous ID can safely be assumed to
in switching circuits with unclamped inductive loads. For reli- equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data 5

MTP2955V
SAFE OPERATING AREA

100 225
VGS = 15 V ID = 12 A

EAS, SINGLE PULSE DRAIN–TO–SOURCE

SINGLE PULSE 200
I D , DRAIN CURRENT (AMPS)

TC = 25°C 175

AVALANCHE ENERGY (mJ)

10 150
125
100 µs
1 ms 100
10 ms
1.0 dc 75

RDS(on) LIMIT 50
THERMAL LIMIT 25
PACKAGE LIMIT
0.1 0
0.1 1.0 10 100 25 50 75 100 125 150 175
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature

1.0
D = 0.5
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE

0.2

0.1
0.05
0.1 P(pk)
0.02 RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
0.01
PULSE TRAIN SHOWN
SINGLE PULSE t1 READ TIME AT t1
t2 TJ(pk) – TC = P(pk) RθJC(t)
DUTY CYCLE, D = t1/t2
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta tb
TIME

tp 0.25 IS

IS

Figure 14. Diode Reverse Recovery Waveform

6 Motorola TMOS Power MOSFET Transistor Device Data

 MTP2955V
PACKAGE DIMENSIONS

NOTES:
SEATING 1. DIMENSIONING AND TOLERANCING PER ANSI
–T– PLANE
Y14.5M, 1982.
C 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
T S BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
4
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
Q A 0.570 0.620 14.48 15.75
STYLE 5: B 0.380 0.405 9.66 10.28
1 2 3 U PIN 1. GATE C 0.160 0.190 4.07 4.82
2. DRAIN
H 3. SOURCE
D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
K 4. DRAIN G 0.095 0.105 2.42 2.66
Z H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
L R N 0.190 0.210 4.83 5.33
V Q 0.100 0.120 2.54 3.04
J R 0.080 0.110 2.04 2.79
G S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
D U 0.000 0.050 0.00 1.27
N V 0.045 ––– 1.15 –––
Z ––– 0.080 ––– 2.04

CASE 221A–09
ISSUE Z

Motorola TMOS Power MOSFET Transistor Device Data 7

MTP2955V

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
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8 ◊ MTP2955V/D
Motorola TMOS Power MOSFET Transistor Device Data
 COLOR CHART FOR SiO2: GT7

Film Thickness Å Color of Film

500 tan
700 brown
1000 dark violet to red violet
1200 royal blue
1500 light blue to metallic blue
1700 metallic to very light yellow-green
2000 light gold or yellow - slightly metallic
2200 gold with slight yellow-orange
2500 orange to melon
2700 red-violet
3000 blue to violet-blue
3100 blue
3200 blue to blue-green
3400 light green
3500 green to yellow-green
3600 yellow-green
3700 green-yellow
3900 yellow
4100 light orange
4200 carnation pink
4400 violet-red
4600 red-violet
4700 violet
4800 blue-violet
4900 blue
5000 blue-green
5200 green
5400 yellow-green
5600 green-yellow
5700 yellow to “yellowish” (at times appears light
5800 light orange or yellow to pink
6000 carnation pink
6300 violet-red
6800 “bluish” (appears between violet-red and blue-
7200 blue-green to green
7700 “yellowish”
8000 orange
8200 salmon
8500 dull light red-violet
8600 violet
8700 blue-violet
8900 blue
9200 blue-green
9500 dull yellow-green
9700 yellow to “yellowish”
9900 orange

Note the cyclical reappearance of the colors as thickness increases. For example, compare
1000,2700, 4600, and 6300Å. The equation which shows this cyclical pattern in SiO2 is:
. t
584
λk =
2k + 1
Where λ = wavelength t = oxide thickness k = 0, 1, 2, ...
GT8: SOME PROPERTIES OF SILICON DIOXIDE

Diffusivities

Diffusant A* B* D@1200°°C
H2 3.02 3490 4 x 10-6cm2/s
He 6.57 1050 5 x 10-8
H2O 2 x 10-9
O2 3 x 10-8
Al 2 x 10-11
Ga 4 x 10-12
Sb 2 x 10-14
P (open tube, P2O5) 3 x 10-15
B 3.55 15400 (T<1100°C) 2.5 x 10-16
10.24 6300 (T>1100°C)

 B
−  A+ 
 T
D = 10 , T in Kelvin

Relative dielectric constant: εr = 3.9

Atom concentration = 2.3 x 1022cm-3

Sources: Burger and Donovan, Vol. 1

Grove
Ghandi

Equations for oxide growth based on Grove’s Model:

A 4 B( t + τ ) 
xox = − 1 + 1 + 
2
 A2 

x ox ( x ox + A) (
xi xi + A )
t= −τ , τ =
B B

 −b  B  −b 
B = C1 exp 1  , = C2 exp 2  , T in Kelvin
 T  A  T 

C1 (cm2/s) C2 (cm/s) b1 (K) b2 (K)

Dry 2.144 x 10-9 0.173 1.427 x 104 2.320 x 104

Wet 5.940 x 10-10 2.490 8.237 x 103 2.320 x 104
Steam 1.070 x 10-9 4.530 9.049 x 103 2.378 x 104
GT10: DIFFUSION DATA

Boron and Phosphorus in Silicon

B, P B P
T, °C D (cm2/s) Nsl (cm-3) Nsl (cm-3)

900 1.5 x 10-15 3.7 x 1020 6.0 x 1020

950 6.6 x 10-15 3.9 x 1020 7.8 x 1020
1000 2.6 x 10-14 4.1 x 1020 1.0 x 1021
1050 9.3 x 10-14 4.3 x 1020 1.2 x 1021
1100 3.0 x 10-13 4.5 x 1020 1.4 x 1021
1150 9.1 x 10-13 4.8 x 1020 1.5 x 1021
1200 2.5 x 10-12 5.0 x 1020 1.5 x 1021
1250 6.5 x 10-12 5.2 x 1020 1.4 x 1021
1300 1.6 x 10-11 5.4 x 1020 1.1 x 1021
1350 3.7 x 10-11 5.7 x 1020 7.1 x 1020

Diffusivity Data for Dopants in Silicon

Dopant P* As** Sb** B* Al** Ga** In*

D∞ (cm2/s) 10.5 0.058 3.94 10.5 1.77 0.573 16.5
Ea/k (K) 4.28 x 104 3.83 x 104 4.49 x 104 4.28 x 104 3.78 x 104 3.77 x 104 4.52 x 104

*Reference Ghandhi p.71

**Highly dependent on doping level. These are PLATO values.

Diffusivity Data for Boron in SiO2

D∞ (cm2/s) Ea (eV)
T<1100°C 2.8 x 10-4 3.06
T>1100°C 5.8 x 10-11 1.25

Reference Burger and Donovan Vol.1 p.159

Diffusivity Data for Phosphorus in SiO2 (open tube, P2O5 source)-Highly Variable

D∞ = 1.59 x 10-11 cm2/s Ea = 1.1 eV

Reference Burger and Donovan Vol 1 p.159

This page intentionally blank
 GT-13

x erfc x
0.01 9.89E-01 0.77 2.76E-01 1.53 3.05E-02 2.29 1.20E-03 3.05 1.61E-05 3.81 7.13E-08
0.02 9.77E-01 0.78 2.70E-01 1.54 2.94E-02 2.30 1.14E-03 3.06 1.52E-05 3.82 6.59E-08
0.03 9.66E-01 0.79 2.64E-01 1.55 2.84E-02 2.31 1.09E-03 3.07 1.42E-05 3.83 6.09E-08
0.04 9.55E-01 0.80 2.58E-01 1.56 2.74E-02 2.32 1.03E-03 3.08 1.33E-05 3.84 5.63E-08
0.05 9.44E-01 0.81 2.52E-01 1.57 2.64E-02 2.33 9.84E-04 3.09 1.24E-05 3.85 5.20E-08
0.06 9.32E-01 0.82 2.46E-01 1.58 2.55E-02 2.34 9.36E-04 3.10 1.17E-05 3.86 4.80E-08
0.07 9.21E-01 0.83 2.40E-01 1.59 2.45E-02 2.35 8.89E-04 3.11 1.09E-05 3.87 4.44E-08
0.08 9.10E-01 0.84 2.35E-01 1.60 2.37E-02 2.36 8.45E-04 3.12 1.02E-05 3.88 4.09E-08
0.09 8.99E-01 0.85 2.29E-01 1.61 2.28E-02 2.37 8.03E-04 3.13 9.59E-06 3.89 3.78E-08
0.10 8.88E-01 0.86 2.24E-01 1.62 2.20E-02 2.38 7.63E-04 3.14 8.98E-06 3.90 3.49E-08
0.11 8.76E-01 0.87 2.19E-01 1.63 2.12E-02 2.39 7.25E-04 3.15 8.41E-06 3.91 3.22E-08
0.12 8.56E-01 0.88 2.13E-01 1.64 2.04E-02 2.40 6.89E-04 3.16 7.87E-06 3.92 2.97E-08
0.13 8.54E-01 0.89 2.08E-01 1.65 1.96E-02 2.41 6.54E-04 3.17 7.36E-06 3.93 2.74E-08
0.14 8.43E-01 0.90 2.03E-01 1.66 1.89E-02 2.42 6.21E-04 3.18 6.89E-06 3.94 2.52E-08
0.15 8.32E-01 0.91 1.98E-01 1.67 1.82E-02 2.43 5.89E-04 3.19 6.45E-06 3.95 2.33E-08
0.16 8.21E-01 0.92 1.93E-01 1.68 1.75E-02 2.44 5.59E-04 3.20 6.03E-06 3.96 2.15E-08
0.17 8.10E-01 0.93 1.88E-01 1.69 1.68E-02 2.45 5.31E-04 3.21 5.64E-06 3.97 1.98E-08
0.18 7.99E-01 0.94 1.84E-01 1.70 1.62E-02 2.46 5.03E-04 3.22 5.27E-06 3.98 1.82E-08
0.19 7.88E-01 0.95 1.79E-01 1.71 1.56E-02 2.47 4.78E-04 3.23 4.93E-06 3.99 1.68E-08
0.20 7.77E-01 0.96 1.75E-01 1.72 1.50E-02 2.48 4.53E-04 3.24 4.61E-06 4.00 1.55E-08
0.21 7.66E-01 0.97 1.70E-01 1.73 1.44E-02 2.49 4.29E-04 3.25 4.31E-06 4.01 1.42E-08
0.22 7.56E-01 0.98 1.66E-01 1.74 1.39E-02 2.50 4.07E-04 3.26 4.02E-06 4.02 1.31E-08
0.23 7.45E-01 0.99 1.61E-01 1.75 1.33E-02 2.51 3.86E-04 3.27 3.76E-06 4.03 1.21E-08
0.24 7.34E-01 1.00 1.57E-01 1.76 1.28E-02 2.52 3.66E-04 3.28 3.51E-06 4.04 1.11E-08
0.25 7.24E-01 1.01 1.53E-01 1.77 1.30E-02 2.53 3.46E-04 3.29 3.28E-06 4.05 1.02E-08
0.26 7.13E-01 1.02 1.49E-01 1.78 1.18E-02 2.54 3.28E-04 3.30 3.06E-06 4.06 9.40E-09
0.27 7.03E-01 1.03 1.45E-01 1.79 1.14E-02 2.55 3.11E-04 3.31 2.86E-06 4.07 8.65E-09
0.28 6.92E-01 1.04 1.41E-01 1.80 1.09E-02 2.56 2.94E-04 3.32 2.67E-06 4.08 7.95E-09
0.29 6.82E-01 1.05 1.38E-01 1.81 1.05E-02 2.57 2.79E-04 3.33 2.49E-06 4.09 7.31E-09
0.30 6.71E-01 1.06 1.34E-01 1.82 1.01E-02 2.58 2.64E-04 3.34 2.32E-06 4.10 6.72E-09
0.31 6.61E-01 1.07 1.30E-01 1.83 9.65E-03 2.59 2.50E-04 3.35 2.17E-06 4.11 6.18E-09
0.32 6.51E-01 1.08 1.27E-01 1.84 9.26E-03 2.60 2.36E-04 3.36 2.02E-06 4.12 5.68E-09
0.33 6.41E-01 1.09 1.23E-01 1.85 8.89E-03 2.61 2.23E-04 3.37 1.88E-06 4.13 5.21E-09
0.34 6.31E-01 1.10 1.20E-01 1.86 8.56E-03 2.62 2.11E-04 3.38 1.75E-06 4.14 4.79E-09
0.35 6.21E-01 1.11 1.16E-01 1.87 8.18E-03 2.63 2.00E-04 3.39 1.64E-06 4.15 4.40E-09
0.36 6.11E-01 1.12 1.13E-01 1.88 7.84E-03 2.64 1.89E-04 3.40 1.52E-06 4.16 4.04E-09
0.37 6.01E-01 1.13 1.10E-01 1.89 7.52E-03 2.65 1.79E-04 3.41 1.42E-06 4.17 3.71E-09
0.38 5.91E-01 1.14 1.07E-01 1.90 7.21E-03 2.66 1.69E-04 3.42 1.32E-06 4.18 3.40E-09
0.39 5.81E-01 1.15 1.04E-01 1.91 6.91E-03 2.67 1.59E-04 3.43 1.23E-06 4.19 3.12E-09
0.40 5.72E-01 1.16 1.01E-01 1.92 6.62E-03 2.68 1.51E-04 3.44 1.15E-06 4.20 2.87E-09
0.41 5.62E-01 1.17 9.80E-02 1.93 6.34E-03 2.69 1.42E-04 3.45 1.07E-06 4.21 2.63E-09
0.42 5.53E-01 1.18 9.50E-02 1.94 6.08E-03 2.70 1.34E-04 3.46 9.94E-07 4.22 2.41E-09
0.43 5.43E-01 1.19 9.24E-02 1.95 5.82E-03 2.71 1.27E-04 3.47 9.25E-07 4.23 2.21E-09
0.44 5.34E-01 1.20 8.97E-02 1.96 5.57E-03 2.72 1.20E-04 3.48 8.60E-07 4.24 2.03E-09
0.45 5.25E-01 1.21 8.70E-02 1.97 5.34E-03 2.73 1.13E-04 3.49 8.00E-07 4.25 1.86E-09
0.46 5.15E-01 1.22 8.45E-02 1.98 5.11E-03 2.74 1.07E-04 3.50 7.44E-07 4.26 1.70E-09
0.47 5.06E-01 1.23 8.19E-02 1.99 4.89E-03 2.75 1.01E-04 3.51 6.92E-07 4.27 1.56E-09
0.48 4.97E-01 1.24 7.95E-02 2.00 4.88E-03 2.76 9.50E-05 3.52 6.43E-07 4.28 1.43E-09
0.49 4.88E-01 1.25 7.71E-02 2.01 4.48E-03 2.77 8.96E-05 3.53 5.98E-07 4.29 1.31E-09
0.50 4.79E-01 1.26 7.48E-02 2.02 4.28E-03 2.78 8.44E-05 3.54 5.56E-07 4.30 1.20E-09
0.51 4.71E-01 1.27 7.25E-02 2.03 4.09E-03 2.79 7.96E-05 3.55 5.16E-07 4.31 1.10E-09
0.52 4.62E-01 1.28 7.03E-02 2.04 3.91E-03 2.80 7.50E-05 3.56 4.80E-07 4.32 1.00E-09
0.53 4.54E-01 1.29 6.81E-02 2.05 3.74E-03 2.81 7.07E-05 3.57 4.45E-07 4.33 9.19E-10
0.54 4.45E-01 1.30 6.60E-02 2.06 3.58E-03 2.82 6.66E-05 3.58 4.14E-07 4.34 8.41E-10
0.55 4.37E-01 1.31 6.39E-02 2.07 3.42E-03 2.83 6.28E-05 3.59 3.84E-07 4.35 7.69E-10
0.56 4.28E-01 1.32 6.19E-02 2.08 3.27E-03 2.84 5.91E-05 3.60 3.56E-07 4.36 7.03E-10
0.57 4.20E-01 1.33 6.00E-02 2.09 3.12E-03 2.85 5.57E-05 3.61 3.31E-07 4.37 6.43E-10
0.58 4.12E-01 1.34 5.81E-02 2.10 2.98E-03 2.86 5.24E-05 3.62 3.07E-07 4.38 5.88E-10
0.59 4.04E-01 1.35 5.62E-02 2.11 2.85E-03 2.87 4.94E-05 3.63 2.85E-07 4.39 5.37E-10
0.60 3.96E-01 1.36 5.44E-02 2.12 2.72E-03 2.88 4.64E-05 3.64 2.64E-07 4.40 4.91E-10
0.61 3.88E-01 1.37 5.27E-02 2.13 2.59E-03 2.89 4.37E-05 3.65 2.45E-07 4.41 4.49E-10
0.62 3.81E-01 1.38 5.10E-02 2.14 2.47E-03 2.90 4.11E-05 3.66 2.27E-07 4.42 4.10E-10
0.63 3.73E-01 1.39 4.92E-02 2.15 2.36E-03 2.91 3.87E-05 3.67 2.11E-07 4.43 3.74E-10
0.64 3.65E-01 1.40 4.77E-02 2.16 2.25E-03 2.92 3.64E-05 3.68 1.95E-07 4.44 3.43E-10
0.65 3.58E-01 1.41 4.61E-02 2.17 2.15E-03 2.93 3.42E-05 3.69 1.81E-07 4.45 3.12E-10
0.66 3.51E-01 1.42 4.46E-02 2.18 2.05E-03 2.94 3.22E-05 3.70 1.67E-07 4.46 2.85E-10
0.67 3.43E-01 1.43 4.31E-02 2.19 1.95E-03 2.95 3.02E-05 3.71 1.55E-07 4.47 2.60E-10
0.68 3.36E-01 1.44 4.17E-02 2.20 1.86E-03 2.96 2.84E-05 3.72 1.44E-07 4.48 2.37E-10
0.69 3.29E-01 1.45 4.03E-02 2.21 1.78E-03 2.97 2.67E-05 3.73 1.22E-07 4.49 2.17E-10
0.70 3.22E-01 1.46 3.89E-02 2.22 1.69E-03 2.98 2.51E-05 3.74 1.23E-07 4.50 1.98E-10
0.71 3.15E-01 1.47 3.76E-02 2.23 1.61E-03 2.99 2.35E-05 3.75 1.14E-07
0.72 3.02E-01 1.48 3.63E-02 2.24 1.54E-03 3.00 2.21E-05 3.76 1.05E-07
0.73 3.01E-01 1.49 3.51E-02 2.25 1.46E-03 3.01 2.08E-05 3.77 9.76E-08
0.74 2.95E-01 1.50 3.39E-02 2.26 1.39E-03 3.02 1.95E-05 3.78 9.03E-08
0.75 2.89E-01 1.51 3.27E-02 2.27 1.33E-03 3.03 1.83E-05 3.79 8.35E-08
0.76 2.82E-01 1.52 3.16E-02 2.28 1.26E-03 3.04 1.72E-05 3.80 7.72E-08
GT14:
SOME PROPERTIES OF THE ERROR FUNCTION

2 w 2  w3 w5 
erf w =
π ∫
0
e −z2
dz =
π
w − + ...
3 × 1! 5 × 2! 

erf(-w) = - erf w
2 ∞ −z2
π ∫w
erfc w = 1 − erf w = e dz

erfc(-w) = 1 + erf w

2w
erf w = for w << 1
π

1 e− w
2

efc w = for w << 1

π w

for w>2: erf w >0.995 and erfc w < 0.005

erf(∞) = 1 erf(0) = 0
erfc(0) = 1 erfc(∞) = 0

d ( erf w) 2 −w2
= e
dw π

1
( )
w
∫ erfc z dz = w erfc w + 1 − e− w
2

0 π

∞ 1
∫ 0
erfc z dz =
π

∞ π w π
∫ e − w dw = ∫ e − z dz =
2 2
, erf w
0 2 0 2

erfc z = (a1t + a 2 t 2 + a 3 t 3 )e − z
2

1
where t = and
1 + pz
p = 0.47047 a1 = 0.3480242
a2 = -0.0958798 a3 = 0.7478556
 GT15:

Ion Implantation: Effective Range Data*

P in Si P in SiO2 B in Si B in SiO2
Energy (kEv) Rp ∆Rp Rp ∆Rp Rp ∆Rp Rp ∆Rp
10 0.0139 0.0069 0.0108 0.0048 0.0333 0.0171 0.0298 0.0143

20 0.0253 0.0119 0.0199 0.0084 0.0662 0.0283 0.0622 0.0252

30 0.0368 0.0166 0.0292 0.0119 0.0987 0.0371 0.0954 0.0342

40 0.0486 0.0212 0.0388 0.0152 0.1302 0.0443 0.1283 0.0418

50 0.0607 0.0256 0.0486 0.0185 0.1608 0.0504 0.1606 0.0483

60 0.0730 0.0298 0.0586 0.0216 0.1903 0.0556 0.1921 0.0540

70 0.0855 0.0340 0.0688 0.0247 0.2188 0.0601 0.2228 0.0590

80 0.0981 0.0380 0.0792 0.0276 0.2465 0.0641 0.2528 0.0634

90 0.1109 0.0418 0.0896 0.0305 0.2733 0.0677 0.2819 0.0674

100 0.1238 0.0456 0.1002 0.0333 0.2994 0.0710 0.3104 0.0710

110 0.1367 0.0492 0.1108 0.0360 0.3248 0.0739 0.3382 0.0743

120 0.1497 0.0528 0.1215 0.0387 0.3496 0.0766 0.3653 0.0774

130 0.1627 0.0562 0.132 0.0412 0.3737 0.0790 0.3919 0.0801

140 0.1727 0.0595 0.1429 0.0437 0.3974 0.0813 0.4179 0.0827

150 0.1888 0.0628 0.1537 0.0461 0.4205 0.0834 0.4434 0.0851

Rp and ∆Rp in µm

*After
Gibbons, Johnson, and Mylroie, Projected Range Statistics, 2nd. Ed., Dowden,
Hutchison, and Ross, Inc.
This page intentionally blank
 Physical Constants: GT19

k = 8.62 x 10-5 eV/K

q = 1.6 x 10-19 C

ε0 = 8.85 x 10-14 F/cm

kT 1 1
= 0.0259 V = = at room temperature
q 38.6 λ

NA = 6.02 x 1023 molecules/mole = Avogadro’s number

Room Temperature Values for Semiconductors and Insulators

Material Eg (eV) χ (eV) εr ε (pF/cm) ni (cm-3) N (cm-3)

Si 1.1 4.03 11.8 1.04 1.5 x 1010 5 x 1022
Ge 0.67 4.0 16 1.42 2.5 x 1013 4.42 x 1022
GaAs 1.43 4.07 13.2 1.17 9.0 x 107 2.21 x 1022
SiO2 (a) 8 1 3.9 0.345 2.3 x 1022
Si3N4 (a) 5 7.5 0.664

(a) = amorphous

Work Functions of Metals

Metal Al, Pb Mo Cr Au Ni Pt
φ (eV) 4.0 4.3 4.6 4.7 5.1 5.3
This page intentionally blank
 APPENDIX A
EVAPORATORS

INTRODUCTION TO THE VARIAN 3120 THERMAL

EVAPORATOR
The Varian 3120 thermal evaporator is a high volume production tool. It was originally used by
Intel to evaporate gold and chrome, although it is used for aluminum in the ece344 lab.

Although the system was originally introduced in the mid- to late 1970s, Intel modified it by
replacing nearly every component except the chassis with newer technology equipment.

As with all high-vacuum systems, it consists of two pumps: the roughing pump, which pumps
from atmospheric pressure (~760 Torr) to low vacuum (~10-2 Torr), and the high-vac pump, which takes
over from low vacuum and pumps to high vacuum (~10-6 Torr). The high-vac pump is what differentiates
it from the Cooke CVE 301 that is also used in the lab.

The Varian uses a cryogenic pump for its high-vac pump. The basic concept of a cryo-pump is to
condense or ‘freeze’ everything to a cryogenic surface. The cryogenic surfaces are at 77K and 15K:
virtually everything will freeze at these temperatures (except for hydrogen and helium).

However, the cryo-pump is a ‘capture’ pump – everything that is pumped stays in the pump.
There is a limit as to how much material can be pumped. As more and more particles freeze on the
cryogenic surfaces, the less efficient it is at conducting energy away from incoming particles. There is a
point at which it stops pumping and must be regenerated (heat up to room temperture and purge).

The major advantage to using a cryo-pump is cleanliness. There is no hydrocarbon oil present to
contaminate the wafers.

Thin film deposition can be done by many methods. You will use the simplest. Once the
atmosphere is sufficiently removed for a clean deposition, aluminum will be boiled by an electrically heated
filament coating everything within sight of it.
A.2
ECE344 Lab Manual
Appendix A
OPERATION OF THE VARIAN 3120
There are only three valves used to control the evaporator:

• hi-vac valve: used to pump on the chamber with the hi-vac pump
• roughing valve: used to pump on the chamber with the roughing pump
• vent valve: used to bring the chamber back to atmospheric pressure

Only one valve should be opened at any time. If the hi-vac valve and any other
valve are open at the same time, the cryo-pump will be swamped and will require
a regeneration (which takes approximately eight hours!).

Standby

In standby, the valves should be in the following position:

• hi-vac valve: off

• roughing valve: off
• vent valve: off

The chamber should be at low vacuum (~500 mTorr) and the ion gauge should
be off. The cryo-head temperature should be <20K.

Loading Wafers Into Chamber

From standby:

1. Open (up position) the vent valve

2. Check chamber pressure
3. When chamber pressure ~720 Torr close vent valve
4. Raise the bell jar with the rocker switch located on the right side of the
table around the bell jar until it almost touches the ceiling
5. Remove the stainless shield from the left side of the carousel
6. Slowly rotate the carousel by hand counter clockwise until the triangular
wafer carrier is in the vertical position
7. Slide out the wafer carrier and load the wafer(s)
8. Check the condition of the evaporation boats
a. Replace if necessary
b. If low on aluminum, recharge with demalloy (Al with 1%Si)
9. Load the wafer carrier into the carousel
10. Rotate the carousel clockwise until the wafer carrier is in the top position
11. Return the stainless shield to the carousel
12. Lower the bell jar – it will stop when it is seated
 A.3
ECE344 Lab Manual
Appendix A
Rough the Chamber

1. Open (up position) the roughing valve

2. When the convectron gauge reaches 500 mTorr, close the roughing valve
3. Wait 10 seconds for valve to fully close

Bring Chamber to High-Vac

1. Open (up position) the high-vac valve

2. The ion gauge will automatically turn on
3. Pump until the ion gauge displays ~5 x 10-6 Torr

Evaporate

1. Turn on (up position) the Concordia filament power supply (220V switch in
the upper left hand corner)
2. Check that the right recipe is selected (consult your TA)
3. Press <START> on the Inficon IC6000
a. The display will show the percent power being applied by the
filament power supply, the instantaneous deposition rate, and the
total film thickness
b. The program will ramp up to 45% power, soak for 45 seconds, then
ramp to 47% power and soak for 15 seconds
c. Deposition normally does not occur for power less than 47%, so
the instantaneously growth rate should be 0A/s
d. The deposition rate will be controlled at 10A/s for a total thickness
of 2000A
4. When the target film thickness is reached, the controller will ramp power
back to 0% and display ‘FINISHED’
5. Turn off (down position) the Concordia filament power supply
6. Wait 30 seconds for the boats to cool down
A.4
ECE344 Lab Manual
Appendix A
Unload Wafers

1. Close (down position) the hi-vac valve

2. Wait 15 seconds for the valve to close fully
3. Turn off the ion gauge (left side)
4. Turn on (up position) the vent valve
5. When chamber pressure ~720 Torr close vent valve
6. Raise the bell jar with the rocker switch located on the right side of the
table around the bell jar until it almost touches the ceiling
7. Remove the stainless shield from the left side of the carousel
8. Slowly rotate the carousel by hand counter clockwise until the triangular
wafer carrier is in the vertical position
9. Slide out the wafer carrier and unload the wafer(s)
10. Load the wafer carrier into the carousel
11. Rotate the carousel clockwise until the wafer carrier is in the top position
12. Return the stainless shield to the carousel
13. Lower the bell jar – it will stop when it is seated

Return to Standby

1. Open (up position) the roughing valve

2. When the chamber pressure ~500mTorr, close roughing valve
 A.5
ECE344 Lab Manual
Appendix A
INTRODUCTION TO THE COOKE CVE 301
The Cooke CVE 301 is a low cost ($12K) one button pump down vacuum evaporator. Although it
can pump down from a standby state with the push of a button, you will be operating the system in manual
mode. This means you must have an understanding of how the system works.

The basic concept of a diffusion pump is to remove the atmosphere that diffuses into jets of
boiling hot oil directed away from the chamber. The momentum transfer from the diffusion pump oil
molecules to the atmospheric particles carries the undesirable atmosphere away so it cannot contaminate
the film to be deposited. The pumping mechanism is not unlike the cause of the wind that one feels at the
bottom of a waterfall on a calm day.

Complications arise from the fact that no diffusion pump oil known is capable of pumping from
atmospheric pressure to more than eight orders of magnitude below. The problem is oxidation of the
pump oil. It proceeds at an unacceptable rate at pressures above about 10-4 atmospheres. Therefore a
mechanical pump must be employed to keep the pressure at either end of the diffusion pump below 100
microns when the diffusion pump oil is hot. Your responsibility will be to make sure the valves are
sequenced properly to keep the oil from "cracking" (a term for rapid oxidation of pump oil)..

The special property that distinguishes diffusion pump oil from other oils is that it can be recycled
within the diffusion pump. See figure 1. Water cooled side walls of the pump body condense virtually all
the diffusion pump oil. The oil is then re-boiled (high vapor pressure) at the base of the diffusion pump
while the mechanical pump removes other particles swept down by the oil jets.

Diffusion pump oil does have a measurable vapor pressure of its own, even at the cooling water
temperature. The price goes up as that vapor pressure goes down. To keep diffusion pump oil from
diffusing up into the chamber, first a water cooled (chevron) baffle and then a liquid nitrogen cooled "trap"
are used to contain the oil. Both are "optically dense" meaning that light or particles with a mean free path
greater than the system dimensions must collide with at least one surface. The cool surfaces will
condense the majority of diffusion pump oil. The 77 K walls of the liquid nitrogen trap also enhance
pumping speed by literally freezing out some of the atmosphere and compacting the rest (PV=nRT), a
phenomenon called cryopumping.

Thin film deposition can be done by many methods. You will use the simplest. Once the
atmosphere is sufficiently removed for a clean deposition, aluminum will be boiled by an electrically heated
filament coating everything within sight of it. Aluminum has the useful property of clinging to the relatively
inexpensive tungsten filaments when it melts rather than falling through.
A.6
ECE344 Lab Manual
Appendix A

-4 -3
100 50 30
-5 10 10
500
200 10
5 -6 10 -2
ATM 0 10 10

TC1 TC2 ON
CC GAUGE
VENT
RAISE VALVE

LIFT ROUGHING
VALVE
LOWER OPEN
OPEN
TC2 HI-VAC
START OPEN
STOP VALVE
ON

AUTO MANUAL
TC1
OFF
MECHANICAL PUMP FORELINE
CONTROL POWER VALVE DIFFUSION PUMP

Figure 2
Control Panel of CVE-301

EMERGENCY PROCEDURE: A popular topic for lab final questions tests your
response to high (>80 microns) pressure in a hot diffusion pump. If the foreline
pressure ever does go too high, you should:

1) Close the Hi-Vac valve.

2) Turn off the diffusion pump heater.
3) Make sure the mechanical pump is pumping through the foreline valve.
a) Mechanical pump should be running.
b) Roughing valve should be closed.
c) Foreline valve should be open.
4) Check for leaks if system is still not recovering. Pumping out the bell jar
helps Hi-Vac leaks.

Normally your instructor will warm up the system before lab periods requiring it.
 A.7
ECE344 Lab Manual
Appendix A

OPERATION OF THE COOKE 301

Warm Up (To be done by TAs only)*

1. Turn on the following utilities:*

2. COOLING WATER - ON
3. LINE AIR PRESSURE - ON ( > 80 PSI)
4. NITROGEN - ON (minimum pressure which will vent the bell jar in one vent cycle)

5. Put the panel switches in the following positions:*

THERMOCOUPLE GAUGE - TC1 (LEFT)

COLD CATHODE GAUGE - OFF (DOWN)
VENT VALVE - CLOSED (DOWN)
HI VAC VALVE - CLOSED (DOWN)
ROUGHING VALVE - CLOSED (DOWN)
FORELINE VALVE - CLOSED(DOWN)
MECHANICAL PUMP - ON (UP)
DIFFUSION PUMP - OFF (DOWN)
AUTO/MANUAL - MANUAL (RIGHT)
MECHANICAL PUMP VENT (INSIDE CABINET) - CLOSED

6. Turn on the power strip. The mechanical pump should start.*

7. Press CONTROL POWER ON. The MANUAL light should come ON.*

8. OPEN the FORELINE VALVE (UP). Note: The system will not go into manual unless
all the valves are momentarily closed.*

9. When TC1 reads < 50 microns, you may turn on the diffusion pump heater as long as
TC1 stays below 100 microns. Turn off as necessary. Tend the unit long enough to
be sure it will stay below 100 (at least 5 minutes!). Note the time when the diffusion
pump was turned on.*

10. About 5 minutes after the diffusion pump is turned on, activate the cold cathode
gauge. If it reads > .01 torr, turn it off and try later. Cold Cathode gauges cannot
reliably initiate ionization when the pressure is too low. The power supply can be
damaged by excessive current when the pressure is too high, however.*

11. Switch to AUTO if it will be used in the automatic mode (usually not). Since this vents
the system, it is best to wait until load time.*

* To be done by the instructor before class.

A.8
ECE344 Lab Manual
Appendix A

Prepare to Pump Down

The diffusion pump must be given at least 20 minutes to warm up before attempting to
pump down (step 7 below).

Do not touch anything with ungloved hands which must go into the vacuum. Water, finger
grease, and similar contaminants will severely slow down the pumping speed and decrease the
MTBF (Mean Time Between Failures). It is good practice not to even touch anything which will
touch anything which will touch anything ... which goes into the vacuum system.

1. Raise the bell jar carefully. If you can't raise the bell jar, cycle the vent switch if
necessary until the bell jar can be raised. If in AUTO, switch to MANUAL, close (turn
DOWN) all the valve switches, and open (flip UP) the foreline and vent switches.

2. Carefully lift the metal chimney straight up and place it on the glass plate by the
asher. Be careful that any microscope slides do not slide off.

3. Load the filament(s) with three 0.025" diameter 3cm long aluminum wires cleaned
with IPA and a kimwipe. By assuming that the entire volume of aluminum will be
deposited uniformly in all directions, it is possible for you to calculate the thickness of
the aluminum on your wafer if you measure the distance from the filament to your
wafer.
NOTE1: If a filament is broken or severely deteriorated, have your instructor look at it. If
you plan to use both filaments in series, they should look nearly identical. If one
seems more used than the other, then they should only be used one at a time.

NOTE2: Always compare the configuration of the copper bars behind the door below the
variac with the drawing below to see which filament(s) are active. Ask your instructor
if you need a different configuration. Normally the filament on the front left (F1) will be
used.

NOTE3: Bent pieces of quartz are provided to prevent the aluminum from evaporating
down into the diffusion pump. A third piece can also be used to prevent both filaments
from evaporating through a metal mask and generating double images. This is
desireable for the dry oxide experiment.

4. Carefully load wafers into all six positions. It should go without saying that the
thickest film will be on the wafers directly above an active loaded filament(s) so that is
where your wafer should be. Use "dummy" wafers as necessary to fill all the other
holes so the bell jar is not coated. This can be done concurrently with the previous
step.

5. Return the chimney assembly back to it's position. Carefully guide the hole in the
wafer plate over the vent tube.

6. If there are no uncoated areas left on the slides, replace them with an IPA and
kimwiped slide and discard the old one(s).
 A.9
ECE344 Lab Manual
Appendix A
7. Make sure there is no path for aluminum from a filament to the bell jar. Monitor
slides should be placed over the small holes near the filaments. These get visibly
coated during the evaporation.

It is strongly recommended that you also place slides such that every silicon wafer has
part of a slide over it. Otherwise, the wafers may move and possibly break during
venting.

8. Wipe down (with IPA on a kimwipe) as many surfaces as you can except for the bell
jar gasket and surfaces inside the chimney/wafer holder assembly. The bell jar
gasket has high vacuum grease on it which should never be removed. The inside of
the chimney has layers of aluminum which flake off and get into the rest of the system
when disturbed. The instructors will take care of excessive aluminum deposits.

Generally, time invested in cleaning is repaid with interest by a fast pump down.

9. Exercising extreme care, slowly lower the $425 bell jar into position.

Automatic Pump Down

Skip to Manual Pump Down since only manual pumpdown is performed.

While pressing the bell jar down onto the base plate press START. You may
take your hand away as soon as the mechanical pump begins to pull a vacuum
on the jar.

Pour in a thermos full of liquid nitrogen. Use only light finger pressure to close
the liquid nitrogen tank valve.

As the system pumps down, monitor TC1. If it goes above 100 microns, tell your
instructor. Occasionally check TC2 to monitor the bell jar pressure. If using an
external cold cathode gauge controller, put it into the START mode until TC2
reads <20 microns.

Manual Pump Down

Skip to Evaporation if Automatic Pump Down was used. Manual pumpdown can be
dangerous to the system, but if done properly, it will be better for both the pump and the thin film.
The operator can make sure the hot diffusion pump oil is never exposed to as much pressure as it
often is during the automatic pump down sequence. The film quality can be better because the
bell jar does not have to be evacuated as much by the mechanical pump before switching to the
diffusion pump. Therefore, "backstreaming" of mechanical pump oil into the bell jar and onto the
wafer is minimized. Cold traps or oil-free pumps are sometimes used to keep oil out of the bell
jar.
The key concept to keep in mind during pump down is that the diffusion pump oil must
never be exposed to more than 100 microns of pressure. For this reason, leave the thermocouple
switch on TC-1 except for short periods to monitor TC-2. Always be ready to answer the question:
What would you do if TC-1 suddenly went above 100 microns?

1. If not already in Manual mode, switch to Manual.

2. Close the foreline valve by flipping the switch downward.

A.10
ECE344 Lab Manual
Appendix A
3. While pressing the bell jar down onto the base plate, open the roughing valve by
flipping its switch upward. You may take your hand away as soon as the mechanical
pump begins to pull a vacuum on the jar.

4. Pour in a thermos full of liquid nitrogen. Use only light finger pressure to close the
liquid nitrogen tank valve.

5. WHILE TC-2 measures >80 microns, DO

Monitor TC-1, checking TC-2 only occasionally.

IF TC-1 > 80 microns THEN
Close roughing valve
Wait 5 seconds
Open Foreline valve until TC-1 < 20 microns.
Close Foreline valve
Re-open roughing valve
END IF

6. When TC-2 = 80 microns, close the roughing valve

7. Wait 5 seconds.

8. Open the Foreline valve.

9. Wait at least 10 seconds for the Foreline pressure to "blank off" (reach its ultimate
pressure).

10. If using an external cold cathode gauge controller, switch it to START now.

11. Open the Hi Vac valve. If the foreline pressure goes above 100 microns, close the Hi
Vac valve until the foreline is settles back down to 80 microns, then open the foreline
valve again. Observe how high the foreline pressure got.

An external cold cathode gauge controller can now be safely turned to the appropriate
scale to monitor the pump down.
 A.11
ECE344 Lab Manual
Appendix A

Evaporation and Vent

When the cold cathode gauge reads less than 1 X 10-5 torr you may perform the
evaporation, but the lower the pressure, the better the film will be.

NOTE: If using an external gauge controller, return it to START before evaporating.

Rotate the variac control all the way to zero (CCW).

Turn on the power supply switch.

When two filaments are used in series, rotate the variac slowly clockwise (CW) to obtain
and maintain a current of 60A for 5 seconds after the aluminum begins to darken the
viewing slide. Then quickly return the variac to zero.

When a single filament is used by itself, 80 AMPs may be used which should result in
complete evaporation in just 3 seconds after the monitor slide begins to darken. Excessive
durations will deposit tungsten from the filament itself as well as other materials nearby.

Turn off the power supply switch.

Wait about 20 seconds to allow the filament to cool.

If in Auto Mode, Press STOP.

If in Manual Mode, Close the Hi Vac valve and then open the vent valve.

Wait for 20 more seconds after the system has vented to allow further cooling in the
nitrogen before exposing the hot surfaces to oxygen. Why?

Carefully, raise the bell jar and remove your wafers. If you can't raise the bell jar, it's
probably because the vent cycle was incomplete. The following sub-steps are for
additional venting if necessary:

Switch to MANUAL mode.

Close (flip DOWN) all the valve switches.

Open (flip UP) the foreline and vent valve switches.

Cycle the vent switch if necessary until the bell jar can be raised.

Close the vent valve and return to AUTO. An automatic vent cycle will start, but
don't worry about it.

Wipe out the system as in step 5. Keeping a vacuum system scrupulously clean is so
important that the instructors will deduct lab performance points from persons ignoring
this step.

Lower the bell jar even more carefully than before. Do not get careless with equipment as
you get more "used to it."
A.12
ECE344 Lab Manual
Appendix A

Standby (To be done by TAs)*

Switch to MANUAL mode.*

Close all the valves.*

While pressing down on the bell jar, open the Roughing valve.*

Wait 30 seconds, then close the roughing valve.*

Wait 5 seconds, then open the foreline valve.*

Shutdown (To be done by the TA at the end of the day)*

Overnight, the system should be left OFF as far as utilities go. The bell jar and diffusion pump
body should be left under vacuum; however, the mechanical pump must never be left OFF with vacuum
on one side of its seals and atmospheric pressure on the other. Therefore, the following procedure must
be executed by the instructor before leaving the lab for the day.

1. Switch OFF (DOWN) the diffusion pump heater. It is strongly recommended that this
be done immediately after the last students to use the system have vented
(STOPPED). It will take about an hour for the diffusion pump oil to cool.*

2. Place the panel switches in the following positions (if they are not there already).*

THERMOCOUPLE GAUGE - TC1 (LEFT)

COLD CATHODE GAUGE - OFF (DOWN)
VENT VALVE - CLOSED (DOWN)
HI VAC VALVE - CLOSED (DOWN)
ROUGHING VALVE - CLOSED (DOWN)
FORELINE VALVE - OPEN (UP)
MECHANICAL PUMP - ON (UP)
DIFFUSION PUMP - OFF (DOWN)
AUTO/MANUAL - AUTO (LEFT)

3. Switch to manual.*

4. AUTO/MANUAL - MANUAL (RIGHT)

5. Close the foreline valve.*

6. FORELINE VALVE - CLOSED (DOWN)

7. Open the roughing valve.*

8. ROUGHING VALVE - OPEN (UP)

9. Monitor TC2. Rough out the bell jar for 30 seconds or until TC2 reaches 80 microns.
Whichever is less. Return to monitoring TC1.*
 A.13
ECE344 Lab Manual
Appendix A

10. Close the roughing valve.*

ROUGHING VALVE - CLOSED (DOWN)

11. Wait 2 seconds.*

12. Open the foreline valve.*

FORELINE VALVE - OPEN (UP)

13. Wait until ALL parts of the diffusion pump body (behind the main access door) are
cool enough that you could rest your hand on them indefinitely.*

14. When the diffusion pump is cool, close the foreline valve.*

15. Turn off and vent the mechanical pump. Use the manual vent valve behind the
access door.*

16. Unplug the main power cord. (I disagree with the microprocessor's program. A
power glitch would open the foreline valve.)*

17. Turn off the other utilities.*

COOLING WATER - OFF (unless Liquid Nitrogen was used within the last hour)
LINE AIR PRESSURE - OFF
NITROGEN - OFF

* To be done by TAs after class only.

This page intentionally blank
 APPENDIX B
WAFER CLEANING
Two methods are used for cleaning wafers in the ECE 344 lab. The first presented here is
ultrasonic vapor degreasing. The other is the industry standard RCA clean. Both procedures are posted in
the wet lab area so you do not need to take your copy of this into the area. Not only is space limited, but
paper is very dirty and dusty by semiconductor industry standards. There is no point in carefully cleaning a
wafer if it is not kept in a clean environment. Use your individual wafer carriers to keep your wafer clean
and safe from accidents after either of these cleaning procedures.

DEGREASING PROCEDURE*
The term degrease refers to the removal of the grime that often coats surfaces exposed to the
atmosphere. The thin film is mostly organic in nature and is probably due to the presence of humans.
1,1,1 Trichloroethane (TCA) is particularly effective in dissolving this "grease" which is why it is commonly
used in industry. Substitutes must be found, however, since compounds containing halogens (chlorine,
fluorine, and bromine) are destroying our ozone.
TCA is boiled in the left sump of the degreaser. Clean TCA boils at 162 F. Contaminants will
raise this temperature. When cool wafers are placed on the screen above the boiling TCA, distilled quality
TCA condenses on the wafers. The fumes are contained within the degreaser by cooling coils which you'll
see dripping TCA into a trough. The trough drains into the rightmost sump which is for water separation.
TCA must go under a baffle and past an additional cooling coil. Since water and most other likely
contaminants are lighter than TCA, they can't get past the baffle. A TA will periodically drain off the top
layer which may contain water. The water separation sump overflows into the middle sump which has
ultrasonic transducers attached to it. Ultrasonic energy can mechanically dislodge stubborn contaminants
from submerged surfaces. This sump overflows into the boiling sump completing the loop for the TCA.
CAUTION: The degreaser fume hood is throttled down to a substandard face velocity so as to
avoid carrying excessive quantities of the solvent, trichloroethane, up the exhaust. Technically, the
degreaser is not required to be in a fume hood at all. Please minimize disturbances of the fumes within
the tank by moving slowly(<11ft/min). You should also use a nitrile glove (although nitrile is not the best
material for solvents) over your latex glove and hold your breath whenever you load and unload the
degreaser. You should take about 10 seconds for your hand to descend into the tank and also 10
seconds to return so the vapors are minimally disturbed. Please hold your face shield with your free hand
so it can not fall into the tank.
 B.2
ECE344 Lab Manual
Appendix B

Wafer Boat

5
4
3

1. Turn on the ultra-sonic transducers by pressing the U/S button behind the right hand fume hood door.
Be sure to close the door afterward.
2. Load the wafer carrier or cleaning basket on the glass plate. The plate is cleaned before class by the
instructor.
3. Open the lid of the degreaser and prop it up in the rear of the hood while holding your breath. Your
instructor can show you how to do this with minimal disturbance of the vapor blanket.
4. Slowly (<11ft/min) place the wafer carrier or cleaning basket on the screen above the boiling sump,
the sump on the left. (#1 in the diagram)
 B.3
ECE344 Lab Manual
Appendix B
Usually, you should degrease both the wafer and the tweezers together. There is no point in having
one clean and the other not since they would contaminate each other.
5. Wait for the dripping to stop - about 20 seconds.
6. If there is aluminum on the wafer or parts, then skip to step B.1.12. Aluminum reacts with TCA
causing the TCA to become acidic.
7. Slowly (<11ft/min) place the wafer carrier or cleaning basket on the screen in the ultrasonic sump, the
center sump. (#2 in the diagram)
8. Wait 1 minute in the ultrasonic sump
9. Slowly (<11ft/min) place the wafer carrier or cleaning basket on the screen above the water separation
sump. (#3 in the diagram)
10. Wait for the dripping to stop and the parts to cool. About one minute. If nobody is going to use the
degreaser soon, turn of the ultrasonic transducers by pressing the OFF button below the U/S button.
Be sure to close the door.
11. Slowly (<11ft/min) move the carrier or basket back down into the fumes over the boiling sump. This
condenses fresh, pure TCA on the parts to wash away any residues left by the ultrasonic sump. (#4 in
the diagram)
12. Slowly (<11ft/min) place the wafer carrier or cleaning basket back to the screen above the water
separation sump to cool. (#5 in the diagram)
13. Slowly (<11ft/min) remove the carrier or basket after about 20 seconds and unload on the glass plate.
(#6 in the diagram)
14. Replace the lid of the degreaser slowly. Hold your breath.
********************************Simple Degreasing********************************

15. Wafers should always be squirted with acetone, then IPA, sprayed with D.I., squirted again
with IPA, and dried with nitrogen to remove any remaining residues not soluble in TCA.

**************************************************************************************

Acetone and IPA should be used over the "waste acetone and IPA" container. Always put the lid
back on the waste container when finished.
Note : Acetone dissolves TCA residue. IPA dissolves acetone residue. Water dissolves IPA
residue. The final IPA rinse is only for making it easier to dry the wafer.
*The vapor cleaning procedure just presented is based on 1,1-trichloroethane (TCA) which
is no longer available (Clean Air Act of 1995). There are alternatives to TCA as a
degreasing agent (TCE, methylene chloride), although they are potentially carcinogenic.
An alternative degreasing method will be explained in the laboratory
 B.4
ECE344 Lab Manual
Appendix B

THE RCA CLEAN

This cleaning method is the industry standard way to clean wafers. Although every company has its
own way of implementing the RCA clean and may have introduced their own proprietary improvements,
they have all been significantly influenced by the work of Kern, a chemist at RCA. One of his articles is
included at the end of this appendix. Please read it. Below is the recipe for our particular implementation.
We substitute sulfuric acid for hydrochloric acid as described in the other article at the end of this
appendix. Ideally, if we had time, we would use this procedure before EVERY diffusion furnace operation.

Preliminary Clean

Transfer the wafers to a teflon wafer carrier specifically reserved for the RCA clean.
1. Securely mount the teflon wafer carrier handle, also reserved for the RCA clean.
2. The wafers should be degreased before continuing. The SC-1 solution can be prepared during the
degreasing procedure.
3. Etch the wafers for 30 seconds in the 50:1 DI:HF etch.

SC - 1: Remove residual organics and certain metals using

the RCA Standard Clean Solution 1
1. Rinse the quartz tub, temperature sensor and thermometer under the SC-1 acid hood.
2. Place the tub on the hotplate with the temperature sensor and thermometer inside.
3. Add 1800 ml of deionized water.
4. Turn on the temperature controller. It has been set for 75° C.
NOTE: Whenever handling strong chemicals it is a very good idea to have DI slowly flowing from
a faucet first. Not only will it help dilute accidental spills, but it allows you to rinse your gloves
without getting the faucet valve contaminated. Always use nitrile gloves over the latex gloves
when handling strong chemicals and rinse them afterward!
5. Slowly add 360 ml of hydrogen peroxide (30%).
6. Slowly add 180 ml of ammonium hydroxide (58%). Be sure to rinse the nitrile gloves, the
graduated cylinder, and the outside of the chemical containers with DI when finished.
7. Slowly stir the solution with a thermometer. (Don't break it!)
8. Slowly place the wafer carrier into the solution.
9. Occasionally stir the solution until it has been over 75°C for 10 minutes.
10. After the 10 minute clean, immerse the wafer carrier in the DI Rinse tank for 15-20 seconds.
11. Spray rinse the wafer carrier and as much of the handle as you can without getting your glove wet.
Remember, at this point a drop of water from a relatively dirty glove could compromise the whole
cleaning process.
12. Move the wafer carrier to the cascade rinse tank for at least 2 minutes.
 B.5
ECE344 Lab Manual
Appendix B
NOTE: While waiting for the temperature to rise it is possible to begin preparation of the SC-2
solution. Do not forget to occasionally stir and check the temperature of the SC-1 solution!

Prepare SC-2 solution

1. Rinse the quartz tub, temperature sensor and thermometer under the SC-2 acid hood.
2. Place the tub on the hotplate with the temperature sensor and thermometer inside.
3. Add 1820 ml of deionized water.
4. Turn on the temperature controller. Verify that its set for 80°C.
5. Slowly add 320 ml of hydrogen peroxide (30%).
6. Slowly add 110 ml of sulfuric acid.
7. Occasionally stir the solution with the thermometer.
8. When the solution has reached 75°C, continue.

Strip hydrous oxide

1. Move the wafer carrier to the 50:1 HF:DI tank for 15 seconds.
2. Agitate the carrier in the DI rinse tank for 20 to 30 seconds.

Desorb remaining contaminants

1. Place the wafer carrier in the hot SC-2 solution for 10 minutes.
2. Turn off the temperature controller.
3. Carefully move the wafer carrier to SC-2 DI rinse tank for 20 seconds.
4. Spray rinse the wafer carrier and as much of the handle as you can without getting your glove wet.
Remember, at this point a drop of water from a relatively dirty glove could compromise the whole
cleaning process.
5. Move the wafer carrier to the cascade rinse tank for 5 minutes. Kern recommended 20 minutes.
 B.6
ECE344 Lab Manual
Appendix B

Dry the wafers

1. Verify that the rinser-dryer is set for:
2. Rinse time = 180 seconds
3. Dry time = 300 seconds
4. Resistivity set point = 10 MΩ-cm
5. Rinse the special handle for lifting the wafer carrier from one end and switch it with the other
handle.
6. Load the wafer carrier into the rinser dryer and press start.
7. Wait for the rinser dryer to stop by itself. Use the time wisely (e.g. prepare for the subsequent
furnace operation).
8. Return the wafer carrier to the rinser-dryer after removing the wafers.

Clean and reorganize the area. If the next days' instructor discovers the telltale crystals of
dried acid, your whole group will loose performance points.
W. Kern
Hydrogen peroxide solutions
for silicon wafer cleaning
The “RCA Standard Clean” process is so well known
throughout the semiconductor industry that many may
not know its RCA origins. Further refinements are described
in this article.
Abstract: Clean silicon
wafer surfaces suitable for device
fabrication have been prepared
successfully for nearly 20 years by the
simple and safe sequential process
described in this paper. The process is
based on oxidation and dissolution of
residual organic impurities and certain
metal contaminants in a mixture of
H20-NH3OH-O2O2 at 75 to 80°C,
followed by dissolution and complexing
of remaining trace metals and
chemisorbed ions in H2O-HCl-H2O2 at
75 to 80°C. The effectiveness of the
method was demonstrated originally by
radioactive-tracer techniques, and was
later confirmed by extensive analytical
studies and device reliability tests.
The RCA method has become
widely accepted in the semiconductor
industry. The original paper, published
in 1970, is one of the most frequently
cited publications in its field. The
present report traces the development of
the process since its origin in 1961,
notes the supporting data from
radioactive-tracer studies, and
summarizes the essential facts
underlying the effectiveness of the
process. Additional information
obtained more recently on the process
and its implementation is briefly
presented. An outline of the processing
procedures that are now recommended
has also been included.
1983 RCA Corporation
Final manuscript received June 1,
1983
Reprint RE-28-4-9
The RCA method for
chemically cleaning silicon wafers
has become widely accepted in the
semiconductor industry. The
original paper1 is one of the most
frequently cited publication in its
field, according to the Science
Citation Index. The Institute for
Scientific Information has requested
a commentary on this work for
publication in the “Citation
Classics” section of Current
Contents.2 The present paper traces
the historical development of the
process since its origin in 1961, notes
the supporting data from
radioactive-tracer studies, and
summarizes the essential facts
underlying the procedures. An
outline of the recommended
processing procedures has been
included in an accompanying box.
Need and
requirements of a
cleaning procedure
The work published in our
1970 article originated in 1961 at the
RCA Solid State Division is
Somerville, New Jersey, when it was
realized that residual trace
impurities on silicon surfaces prior
to high-temperature processing -
particularly diffusion, thermal
oxidation, and epitaxial growth - can
have detrimental effects on surface
stability, reliability, electrical
performance, and production yield
of devices, especially sensitive
metal-oxide-semiconductor types. It
became clear to me that a highly
effective yet simple and hazard free
process was needed for purifying
pre-cleaned silicon wafers, as well as
thermally oxidized patterned or
unpatterned wafers.
The procedures used up to that
time involved hot mixtures of
concentrated sulfuric acid and
hydrogen peroxide, or of
concentrated sulfuric acid and
chromic acid. The first was
suspected of causing sulfur
contamination and was extremely
hazardous when used by operators
in a production environment. The
second was suspected of leading to
chromium contamination and posed
serious ecological problems of
disposal. Clearly, a procedure was
needed that was effective, free of
contaminants introduced by the
reagents, safe, economical, and
ecologically acceptable.
Chemical
considerations
The new cleaning method
to be developed had to first be based
on first removing organic
contaminants (such as grease films
and photoresist residues masking
the surface) to expose the wafer
surface and render it hydrophilic
(“water loving”)., thereby rendering
it accessible to aqueous chemical
 Taken from RCA Engineer, Vol. 28, No. 4 (July/August 1983)
reagents. This step would then be
followed by the removal of
inorganic contaminants (such as
trace metals and chemisorbed ions).
Ideally, the reagents to accomplish
these objectives had to be
completely volatile and
commercially available at high
purity and low cost.
On the basis or reaction
chemistry and reagent purity, water
diluted, unstabilized hydrogen
peroxide at high pH, attained by the
addition of ammonium hydroxide
solution appeared to be the ideal
reagent for removing residual
organic contaminants by oxidative
breakdown and dissolution, if used
at an elevated temperature for a
suitable period of time. In addition,
this solution would also remove
several types of metals such as Cu,
Ag, Ni, Co, Cd, and Au, due to
complexing by the ammonium
hydroxide.
For the second solution, I
selected diluted hydrogen peroxide
at low pH, prepared by adding
hydrochloric acid solution. Used
again at elevated temperature, this
solution was to remove alkali ions
and remaining metallic impurities.
Displacement replating of heavy
metals from solution would be
prevented by the formation of
soluble complexes with the resulting
dissolved ions.
Deionized, distilled, and
microfilterd water served as the
diluent and rinsing agent. To
prevent leaching of alkali and boron
from Pyrex (DuPont), and wafer
holders of Teflon (DuPont), and
conducted systematic experiments
for establishing optimal processing
conditions and solution
concentrations. Surface chemical
analysis techniques and radioactive-
tracer measurements served as very
sensitive analytical methods for
evaluating the efficiency of various
cleaning processes in the course of
this development.
The results of these experiments
subsequently showed that the
solution compositions are not critical
for the effectiveness of the process,
as long as one operates within
volume ratios of 4:1:1 to 6:1:1 of
H2O, 30 w/w% H2O2, and 29 w/w%
NH4OH (as NH3) for the first
mixture, and 4:1:1 to 6:1:1 of H2O, 30
w/w% H2O2, and 37% HCl for the
second mixture. Treatment periods
of 10 to 20 minutes are sufficient.
The solution temperature can be
maintained at 75 to 85°C, but
preferably should not exceed 80°C.
A higher temperature would cause
rapid decomposition of the
hydrogen peroxide.
Radiochemical
contamination and
cleaning efficiency
studies
Concurrent with these
studies I investigated the origin,
cause, type, and concentration of
contaminants by adding trace
quantities of radioactive cations
(Na22, Na24, Au198, Cu64, Fe59, Cr51,
Zn65, Sb122, Sb124, Mn54, Mo99) and
anions (F18, Cl38, I131, C14 - organics)
to numerous etchant and reagent
solutions. Radioactivity
measurements, autoradiography,
and gamma-ray spectroscopy of
electronic solids (Si, SiO2, Ge, GaAs)
treated with these tagged solutions
allowed quantization of the
resulting surface concentrations of
specific impurities, both initially and
after various rinsing and cleaning
steps with the hydrogen peroxide
mixtures noted.3-8
Application to
silicon device
production
By mid-1960, the peroxide
cleaning technique (dubbed “SC-1”
and “SC-2” to denote “Standard
Clean, Solutions 1 and 2” - see box)
was well established and widely
applied at RCA in the fabrication of
silicon devices. A process patent
that incorporated the HCl-H2O2
desorption process was issued to
RCA in 1966.9 Also in 1966, I
received an RCA Outstanding
Achievement Award shared with
James A. Amick and Arthur I. Stoller
“for new technological advances for
processing integrated circuits,”
which included the peroxide
method for attatining practically
clean silicon surfaces in conjunction
with glass-passivation and tungsten-
metallization processes.
Publications
In 1970 I succeeded in
obtaining permission to publish the
series of papers on the
radiochemical studies and the
peroxide cleaning process: the latter
incorporated the contributions of my
co-author, David A. Puotinen, who
had studied in some detail several
aspects of peroxide cleaning as
applied to silicon device processing.
Several of my colleagues
contributed also to the success of
this work, particularly Norman
Goldsmith and James A. Amick10
during the development and
implementation that extended over
several years, and Alfted Mayer who
introduced megasonic (ultrahigh-
frequency) peroxide cleaning at low
temperature (explained below),
effectively combining the removal of
particulates with the desorption of
adsorbed contaminants.
Introduction of
additional process
step
An additional step in the
procedure, which was not explicitly
noted in our original paper because
of insufficient data at that time, is
the application of a brief etch in
dilute HF solution after the SC-1
cleaning. I reasoned that removal of
the hydrous oxide film formed
during the SC-1 treatment to
reexpose the silicon surface for the
subsequent SC-2 desorption step
should further increase the
purification efficiency. However,
this etching should be done with a
very dilute high-purity HF solution
and for a very short period of time
to avoid replating of the metallic
contaminants from the HF solution
on the silicon surface.
Experiments have shown that a
10-second immersion in 1:50 HF-H20
is sufficient to remove this film, as
evidenced by the change of the
hydrophilic oxidized surface to a
hydrophobic surface, which is
characteristic for a fluoridated,
organic contaminant-free silicon
surface. Subsequent water rinsing
should also be kept very brief (30
seconds), serving only to remove HF
solution from the wafer assembly in
order to minimize regrowth of a
new hydrous oxide film
Fortunately, change of a ≡Si-F
surface to a ≡Si-OH surface in cold
H2O is very slow, minimizing rapid
regrowth of a hydrated oxide film.5
We believe that this additional step

does indeed enhance the
effectiveness of the subsequent SC-2
treatment, and should be part of the
cleaning sequence.
Reasons for
popularity of cleaning
procedure
The original paper of 1970
has been highly cited because
extensive analytical studies and
device reliability and life testing by
many independent researchers have
confirmed the process, now widely
known as “RCA Standard Clean,” to
be the most effective cleaning
method known for attaining the
degree of purity that is imperative in
the fabrication of sensitive silicon
semiconductor devices.
Furthermore, the process is safe and
relatively simple, has attractive
economic and ecological
advantages, uses readily available
high-purity solid free and volatile
reagents, and was accepted by the
American Society for Testing and
Material as a standard procedure.12
Actually the process is so widely
employed that most authors refer to
it without citing our original work,
apparently assuming it to be
common knowledge.
Developments
since 1970
The following section
reviews the more important
literature references on silicon wafer
cleaning with SC-1 and SC-2
hydrogen peroxide solutions. These
references confirm our original
statements and contribute additional
new information on the subject.
Henderson13 published results in
1972 on the analytical evaluation of
the SC-1/SC-2 cleaning process by
high-energy electron diffraction and
Auger electron spectroscopy. He
concluded that the process is well
suited for silicon wafer cleaning
prior to high-temperature
treatments, as long as quartzware is
used for processing, according to
our specifications, to avoid boron
contamination from Pyrex
containers. He also examined the
possible benefits of an additional
final etch treatment in concentrated
HF after completion of the SC-1/SC-
2 steps, but found that it enhances
carbon contamination and causes
Taken from RCA Engineer, Vol. 28, No. 4 (July/August 1983)
surface roughening during vacuum
heating at 1100°C due to loss of the
protective 15-angstrom thick
carbonfree oxide film remaining
after the SC-2 step. Reexposure of a
bare silicon surface to HF after SC-2
would, of course, be ill advised
because of recontamination with
metallic impurities, obliterating the
advantages of peroxide cleaning.
Meek et al, (1973)14 investigated
the removal of inorganic
contaminants, including copper and
heavy metals, from
chemically/mechanically polished
silicon wafers by several reagent
solutions. Using Rutherford back-
scattering with 2-MeV He+ ions as
an analytical tool, they concluded
that the SC-1/SC-2 as preoxidation
cleaning process always removed all
elements heavier than chlorine to
below the level of detectability.
Sulfur and chlorine remained after
either SC-1, SC-2, or other cleaning
procedures studied at levels of about
1013/cm2. SC-1/SC-2 cleaning
eliminated calcium and copper
much more reliable than did HF-
HNO3 treatments.
Murarka et al, (1977)15 studied
methods for oxidizing silicon
without the formation of stacking
faults. They concluded that
chemical cleaning of the wafers with
SC-1/SC-2 prior to an oxidation is
an essential requirement to ensure
the complete elimination of stacking
faults after the high-temperature
processing.
In 1978, we published a review16
of the entire field of surface
contamination and semiconductor
cleaning techniques as part of a book
chapter on the chemical etching of
thin films and substrates.
Gluck (1978)17 presented a paper
in which he discussed the removal
of radioactive gold from silicon
wafers by a variety of baths
containing H2O2, H2O, NH4OH,
and/or HCl. The desorption
efficiency of SC-1 solution was more
effective than that of SC-2, but the
usual sequential treatment of SC-1
followed by SC-2 was the most
effective removal method at higher
gold surface concentration (in the
1014/cm2 range).
Peters and Deckert (1979)18
investigated photoresist stripping b
numerous solvents, chemical agents,
plasma stripping, and heat
treatment in air at 650°C
(combustion, or ashing). They found
that film residues remain on wafers
in all cases except ashing. The SC-1
procedure was the only technique by
which the residues could be
removed consistently and
completely. They recommended
that SC-1 cleaning be applied
routinely to SiO2-patterned silicon
wafers after photoresist stripping
operations in oxide masking.
In a 1981 review article on wafer
cleaning, Burkman19 reported results
of desorption tests for radioactive
gold from silicon wafers with
several reagent solutions. A
centrifugal spray cleaning machine
by FSI Corporation was used rather
than bath immersion. An SC-1 type
of H2O-NH4OH-H2O2 solution was
much more effective than H2SO4-H20
mixtures, but an H2O-HCl-H2O2
solution alone showed poor
efficiency, probably because an
organic film masked the surface,
thereby preventing efficient gold
desorption.
Phillips et al, (1983)20 applied, in
preliminary tests, secondary ion
mass spectrometry to determine the
relative quantities of contaminants
on silicon wafers. Cleaned wafers
were purposely contaminated gross
quantities of numerous inorganic
impurities and then cleaned by
immersion or spray techniques with
various aggressive reagents (aqua
regia,, hot fuming nitric acid,
sulfuric acid-hydrogen peroxide,
and SC-1/HF/SC-2 type of
solutions). The lowest residual
concentrations for most impurity
elements were obtained by spray
cleaning with a sulfuric acid and
hydrogen peroxide mixture as used
for photoresist stripping, followed
by the SC-1/HF/SC-2 cleaning
sequence.
Watanabe et al (1983)21
measured the dissolution rate of
SiO2 and Si3N4 films in H2O-
NH4OH-H2O2 mixtures. The etching
rate of thermally grown SiO2 in SC-1
(5:1:1 of H2O-NH4OH-H2O2) during
a 20-minute treatment at 80°C was a
constant 4 angstroms per minute.
The authors state that this rate of
dissolution is significant for
structures incorporating thin (200
angstroms or so) oxide layers (one
might argue that the processing of
such layers should be designed to
use as-grown films to make chemical
treatments unnecessary). The etch
rate of high-temperature chemically
 Taken from RCA Engineer, Vol. 28, No. 4 (July/August 1983)
vapor-deposited Si3N4 was 2
angstroms per minute under the
same conditions.
Measurements done in 1981 in
the author’s laboratory at RCA,
however, indicated much lower
oxide-dissolution rates under nearly
identical conditions. Changes in
film thickness were measured by
ellipsometry after each of four
consecutive treatments in fresh 5:1:1
SC-1 at 85°C and totaled only 70
angstroms per 80 minutes, or 0.9
angstroms per minute, whereas in
solution without peroxide (1:6 H2O-
NH4OH) the rates were 1.6
angstroms per minute. Under the
same conditions, 6:1:1 SC-2 solution
showed practically no change in the
film thicknesses, as would be
expected.
Alternative
processing techniques
using SC-1/SC-2
The original and widely
used RCA cleaning procedure is
based on simple immersion
techniques. Two alternative and
attractive techniques have been
introduced in recent years:
centrifugal spray cleaning19 and
megasonic cleaning11,12.
In centrifugal spray cleaning,
developed by FSI Corporation, the
wafers are enclosed in a chamber
purged with nitrogen. A sequence
of continuous fine sprays of reagent
solutions, including hot SC-1, SC-2,
and high-purity water, wets the
spinning wafers; N2 finally dries
them for removal. The main
advantages of this automated
system are the reduced volume of
chemicals needed, the continuous
supply of fresh reagent solutions to
the wafer surface, and the controlled
environmental conditions during the
processing. The cleaning efficiency
of the centrifugal spray system is
comparable with that obtained with
the RCA immersion technique,
according to claims by FSI
Corporation.
The megasonic cleaning system
was patented in 1975 by RCA
Corporation11,12 and is manufactured
under license by the Process System
Division of Fluorocarbon Company.
It is a noncontact, brushless
scrubbing machine designed
primarily for safely removing
particulate contaminants from both
sides of silicon wafers by use of
ultrahigh-frequency sonic energy.
Sonic waves of 85 kHz are generated
by an array of piezoelectric
transducers, providing a highly
effective scrubbing action on batches
of wafers immersed in the cleaning
solution. Particles ranging in size
from several micrometers down to
about 0.3 µm can be efficiently
removed with input power densities
of 5 to 10 W/cm2. For comparison,
ultrasonic systems that operate
typically at 25 to 80 kHz require
power densities of up to 50 times
that of the megasonic system, and
are much less effective for removing
very small particles.
An interesting additional aspect
of this machine is its ability to
operate effectively with SC-1 and
SC-2 cleaning solutions for the
removal of organic and many
inorganic contaminants, similar to
the RCA immersion technique, even
though the bath temperature rises to
only 35 to 42°C during operation.
Initial experimental data of
desorption efficiencies for metallic
and ionic contaminants are
impressive, but an extensive and
quantitative evaluation has not yet
been carried out to assess the extent
of effectiveness. At present, any
degree of chemical cleaning and
desorption of contaminants resulting
simultaneously with particle
removal, the main function intended
of the machine, can be considered a
highly desirable additional benefit
of this system. Photographs of a
typical machine are shown in Figs.
1a and 1b.
Comments and
recommendations
It is important to stress
that the wafers during processing
must never be allowed to dry,
because dried residues may be
difficult to redissolve and may mask
the surface during subsequent
treatments. Removal from a hot
bath should therefore be done only
after cooling or quenching the
solution by dilution with cold water.
This technique also minimizes
contamination from the solution/air
interface.
Vapors of NH3 and HCl form a
smog of NH4Cl when brought in
close proximity to each other.
Therefore, the SC-1 must be
separated from the SC-2 processing
by the use of two separate exhaust
hoods to avoid wafer contamination
from colloidal NH4Cl particles.
Disregard of this recommendation
has repeatedly led to problems in
production application.
Pyrex glassware should not be
used with the SC-1 and SC-2
procedures because substantial
amounts of sodium, potassium,
boron, and impurities are leached
out of the glass by the hot solutions.
As noted, beakers of fused silica
should be used instead; high-
quality opaque fused silica is much
less costly than clear fused quartz,
and is acceptable for wafer-cleaning
vessels. Rinse tanks and vessels for
HF solution should be constructed
of high-grade polypropylene plastic.
Operators frequently believe
that if hot SC-1 solution is good for
processing, a boiling solution must
be better. This fallacy is remarkably
difficult to correct. As noted, the
solutions, especially the SC-1,
should be used at a temperature in
the range of 75 to 80°C because, at
higher temperatures, H2O2 rapidly
decomposes and there is increased
volatilization of NH3 from the
NH4OH solution. Fortunately, for
SC-1 solutions the rate of H2O2
decomposition and of NH3
volatilization under the
recommended processing conditions
are similar; ammonia in the absence
of H2O2 would immediately etch
silicon. In the case of SC-2 solutions,
the decomposition of the H2O2 and
volatilization of HCl proceed at
much slower rate than for SC-1, and
there is no danger of silicon etching
under any conditions. Nevertheless,
excessive heating should be avoided
for safe operation.
To illustrate the degree of
decomposition of hydrogen
peroxide in an SC-1 solution as a
function of extreme temperature and
time conditions, the graph from our
original paper1 is reproduced in Fig.
2. It can be seen that the half-life of
the solution at 88 to 90°C was
approximately 5 minutes (versus 50
hours at 23°C), and the time for the
concentration of peroxide to be
reduced to the etching threshold
level for (111)-orientated silicon was
more than 40 minutes after the
solution reached 79°C. Since the
preferred recommended cleaning
time is minutes at a temperature of
75 to 80°C, there is an adequate

margin of safety if the initial
peroxide concentration is at the
recommended level. Recent
measurements, which we conducted
with SC-1/SC-2 reagents that are
now available at much higher purity
than before 1970, have shown
considerably lower rates of
decomposition.
A wide range of SC-1 and SC-2
compositions has been used
successfully by many engineers. The
recommended ratios of 5:1:1 for
H2O-NH4OH-H2O2, and of 6:1:1 for
H2O-HCl-H2O2, are effective and
economical ratios used by most
people. Repeated use of the
solutions, or reconstitution of the
reagent composition, is not
recommended because it would
prevent the safe technique of
overflow-quenching with cold
water. Besides, impurities
accumulate in the solutions and
accelerate the decomposition rate of
H2O2.
The use of unstabilized H2O2,
that is H2O2 without stabilizer
additions, has been specified.
Principal additives in commercial
stabilized H2O2 are sodium
phosphate and or sodium stannate,
compounds that are highly
undesirable contaminants in our
application.
Occasionally, etching of silicon
areas in device wafers during SC-1
cleaning has been encountered. The
most likely explanation for this
effect is a catalytically accelerated
decomposition of the H2O2 due to
trace impurities, especially heavy
metals from tweezers or containers,
or impurities in the reagents.
Decomposition may then take place
even at a low temperature, or on
mixing of the solutions. In the
absence of sufficient quantities of
H2O2 (initial concentrations of less
than 50 percent of what we
recommend), the ammonium
hydroxide will etch silicon at rates
dependent on crystallographic
orientation, dopant types and
concentrations in the silicon, and
proximity of p- and n-type areas.1
The light intensity during this
treatment may also be a factor. A
detailed outline of the exact,
updated processing procedures that
are recommended is presented in the
accompanying box.
Taken from RCA Engineer, Vol. 28, No. 4 (July/August 1983)
15. S.P. Murarka, H.J. Levinstein, R.B.
Acknowledgmen Marcus, and R.S. Wagner, “Oxidation of
Silicon Without the Formation of Stacking
t Faults,” J. Applied Physics, Vol. 48, pp.
4001-4003 (1979)
I wish to thank Richard E. 16. W. Kern and C.A. Deckert, “Chemical
Berger for carrying out the Etching,” Part V-1, Thin Film Processes; J.L.
experimental work and Vossen and W. Kern, Editors, Academic
Press, New York, N.Y., pp 411-413 (1978)
measurements, Stanley Shwartman 17. R.M.Gluck, “Gold Removal from Silicon
for providing the megasonic system with Dilute Peroxide Mixtures Containing
NH4OH and/or HCl,” Electrochem. Soc.
photographs, and George L. Ext. Abstr, 78-2, 640, Abstract No. 238
Schnable for reviewing the (1978)
manuscript and making valuable 18. D.A. Peters and C.A. Deckert, “Removal
of Photoresist Film Residues from Wafer
comments. Surfaces,” J. Electrochem. Soc., Vol. 126, pp.
883-886 (1979)
19. D. Burkman, “Optimizing the Cleaning
References Procedure for Silicon Wafers Prior to High
Temperature Operations,” Semiconductor
1. W. Kern and D.A. Puotinen, “Cleaning
Solutions Based on Hydrogen Peroxide for
International, Vol. 4, No. 7, pp. 103-116
(July 1981)
Use in Silicon Semiconductor
20. B.F. Phillips, D.C. Burkman, W.R.
Technology,” RCA Review, Vol. 31, pp.
Schmidt, and C.A. Peterson, “The Impact
187-206 (1970)
2. W. Kern, “Use of Radioisotopes in the
of Surface Analysis Technolgy on the
Development of Semiconductor Wafer
Semiconductor Field at RCA,” RCA
Cleaning Processess,” J. Vac. Sci. Tech. Vol.
Engineer, Vol. 9, No. 1, pp. 62-68 (1963)
A1, No. 2, pp. 646-649 (1983)
3. W. Kern, “Cleaning Solutions Based on
Hydrogen Peroxide for use in Silicon
21. M. Watanabe, M. Harazono, Y. Hiratsuka,
and T. Edamure, “Etching Rates of SiO2
Semiconductor Technology,” Citation
and Si3N4 Insulating Films in Ammonia
Classic, Current Contents, Engineering,
Technology, and Applied Sciences, Vol. 14,
Hydrogen-Peroxide Cleaning Process, “
Electrochem. Soc. Ext. Abstr., Vol. 83-1, pp.
No. 11, p. 18 (March 14, 1983)
221-222, Abstract No. 139 (1983)
4. W. Kern, “Radioisotopes in
22. S. Shwartzman and A. Mayer, “Megasonic
Semiconductor Science and Technology,”
Semiconductor Products & Solid State
Cleaning of Surfaces,” to be published in
Treatise on Clean Surgace Technology, Vo. III,
Technology, Vol. 6, No. 10, pp. 22-26: No.
K.L. Mittal, Ed., Plenum Publishing
11, pp. 23-27 (October and November
Corporation, New York, N.Y. (1983)
1963)
5. W. Kern, “Radiochemical Studies of
23. J.R. Zuber and A.J. Gaska, “Elimination of
Impurities from Silicon Discs,” U.S. Patent
Semiconductor Contaminations - I.
No. 563,104 (March 28, 1975)
Adsorption of Reagent Components,”
RCA Review, Vol. 31, pp. 207-223 (1973)
24. W. Kern, “A Technique for Measuring
Etch Rates of Dielectric Filsm,” RCA
6. W. Kern, “Radiochemical Studies of
Review, Vol. 29, pp. 557-565 (1968)
Semiconductor Surface Contamination-II.
Adsorption of Trace Impurities,” RCA
Review, Vol. 31, pp. 234-264 (1970)
7. W. Kern, “Radiochemical Study of
Semiconductor Surface Contamination-III.
Deposition of Trace Impurities on
Germanium and Gallium Arsenide,” RCA
Review, Vol. 32, pp. 64-87 (1971)
8. W. Kern, “Semiconductor Surface
Contamination Investigated by
Radioactive Tracer Techniques,” Solid
State Technology, vol. 5, No. 1, pp. 34-38;
No. 2, pp. 39-45 (January and February
1972)
9. J.A. Schramm, “Method of Fabricating a
Semiconductor Device,” U.S. Patent No.
3,281,915 (November 1, 1966)
10. J.A. Amick, “Cleanliness and the Cleaning
of Silicon Wafers,” Solid State Technology,
Vol. 47, No. 11, pp. 47-52 (November
1976)
11. A. Mayer and S. Shwartzman, “Megasonic
Cleaning: A New Cleaning and Drying
System for Use in Semiconductor
Processing,” J. Electronic Materials, Vol. 8,
pp. 855-864 (1979)
12. “Standard Test Method for Detection of
Swirls and Striations in Chemically
Polished Silicon Wafers,” ASTM F416-77;
Annual Book of ASTM Standards, Part 43,
Electronics, American Society for Testing
and Materials, Philadelphia, Pa., pp. 840-
851 (1981)
13. R.C. Henderson, “Silicon Cleaning with
Hydrogen Peroxide Solutions: A High-
Energy Electron Diffraction and Auger
Electron Spectroscopy Study,” J.
Eletrochem. Soc., Vol. 119, pp. 772-775
(1972)
14. R.L. Meek, T.M. buck, and C.F. Gibbon,
“Silicon Surgace Contamination: Polishing
and Cleaning,” J. Electrochem. Soc., Vol.
120, pp. 1241-1246 (1973)
Taken from RCA Engineer, Vol. 28, No. 4 (July/August 1983)
 Keeping the ‘RCA’ in
Wet Chemistry
Cleaning
Engineers will continue to tweak RCA wet chemistry formulae; it is unlikely that
this, perhaps the most durable wafer processing technique, will be replaced en masse
anytime soon.

Hydrogen peroxide-based cases, either the SC-1 or SC-2 step

Pieter Burgrgraaf
Senior Editor
Key
Technologies:
• Chemicals
• Wafer Cleaning Equipment
At A Glance:
Ever since 1965, wafer
processing operators have been
mixing hydrogen peroxide with
ammonium hydroxide and
hydrochloric acid - the reagents in
the infamous RCA clean. And since
then, engineers, while marveling at
the capabilities of these mixtures,
have experimented with the recipes
to improve the results or to keep
their capabilities equal to the
increasing demands of wafer
processing. It is somewhat amazing
that today the RCA formulae are still
the basis of wet chemistry cleaning
in virtually all wafer processing
operations worldwide. In various
easily recognizable forms, often with
an additional step or two added,
many experts foresee hydrogen
peroxide-based wet cleans meeting
the industry’s needs through the turn
of the century. Yet there are
suggested alternatives to this
technology, its relatively high cost
being perhaps the driver for change.
“RCA” wet cleans still dominate in
wafer processing. Researchers have
tweaked the mixtures and
procedures over the years so that
current recipes are just as capable of
cleaning today’s wafers as Werner
Kern’s original recipes (Table 1) were
in cleaning wafers in 1965 at RCA1.
John Rosato, Ph.D., R&D manager at
Santa Clara Plastics, says, “They
continue to be the cleans of choice for
most pre-furnace applications,
particularly for critical steps such as
gate oxidation.”
Tweaking the chemistry
Certainly, much of the
success of wet chemistry wafer
cleaning must be attributed to
today’s high purity reagents that go
into the RCA formulae. Werner
Kern, Werner Kern Associates (East
Windsor, N.J.), notes, “High purity
chemicals, including aluminum free
H2O2, low particulate HF, and low
metal HCl and NH4OH solutions
have led to much lower trace metal
contamination levels than were
previously possible.”
Today it is not uncommon to
find RCA wafer cleaning done with a
variety of sequence and mixture
modifications. Rosato explains,
“These often include adding to or
changing the order of the basic SC-1
and SC-2 cleaning steps. For
example, ‘piranha’ (98% H2SO4 and
30% H2O2) and HF steps may be used
before, after or between the SC-1 and
SC-2 steps. Ending the sequence
with an HF-last step is common for
chemical vapor deposition and pre-
metalization processes.” In other
may be deleted, depending on critical
needs for a particular process.
Work on the HF-last step at the
Interuniversity Micro-Electronics
Center (IMEC, Leuven, Belgium) has
shown that HF-dipping time must be
optimized to obtain a highly
passivated surface that is resistant to
particle recontamination. IMEC
engineers have also shown that the
addition chloroacetic acid to dilute
HF solutions result in excellent metal
removal properties (use of “chelating
agents” are discussed later in this
article).
Other work has shown that
surfactant additives, such as
isopropyl alcohol, can lower the
surface-free energy and increase
surface passivation. For example,
research by Dr. Tadahiro Ohmi at
Tohoku University (Sendai, Japan)
has found that surfactants in HF
improve the wetting of hydrophobic
silicon and help prevent particle
adhesion.
Suggestions for more dramatic
RCA clean sequence and mixture
modifications have also come out of
work at IMEC: Reporting at the May
1994 IES Conference in Chicago,
IMEC engineers said that the
standard SC-2 solution can be
replaced with dilute 0.1 mol/liter
HCl without H2O2. This cuts
chemical consumption and cost,
while maintaining metal removal
efficiency.
The idea that an HF-only or
simplified RCA recipe can
significantly cut the cost of wet
cleaning is a paramount
consideration for future
semiconductor manufacturing. Chris
McConnel, president of CFM
Technologies, notes that systematic
investigations of time, temperature,
reagent strength and acoustic energy
have led to optimized RCA cleaning
recipes. “Along with enhancements
in cleaning performance, some of
these studies have led to startling
reductions in cost-of-ownership; for
example, an IBM study co-sponsored
by CFM and SEMATECH
demonstrated a nearly ten-fold
reduction in chemical consumption.
Other savings come with overall
throughput improvement and total
cost per wafer pass,” he says.
Certainly, the chemical cost side
of wet cleaning will continue to be
addressed: J.T. Baker (Phillipsburg,
N.J.), for example, has an emerging
product with the code name
“Dublin” slated for formal
introduction in July 1994: it’s
described as “an aqueous-based
chemical replacement for the RCA
clean.” Baker’s Mike Thompson
reports, “While ‘Dublin’ is still under
beta site evaluation to correlate yield
and electrical improvements
corresponding to improved trace
impurity and particle removal as
well as improved microroughness,
the significant advancement may be
its reduction in processing time ad
the volume of liquid required for wet
processing.”
Microroughening
Because the SC-1 step
cleans particles and some trace
metals by continuous chemical
growth and etching of a hydrous
oxide film on silicon, it is known that
the standard 5:1:1 solution can cause
microroughening of any exposed
silicon in a circuit pattern. Since the
pioneering work by Ohmi, this
problem has received much attention
in the literature; in one study,
researchers at IBM, CFM and
SEMATECH used atomic force
microscopy to observe bump-like
microroughening caused by bubbles
that blocked the surface reaction of
SC-1 chemistry.
Other work by Ohmi, and
organizations like IMEC, has shown
that the NH4OH:H2O2 ratio and the
temperature of the SC-1 bath have to
be optimized to balance the etching
action of the solution and control
microroughening, as well as particle
removal efficiency. The current trend
is to reduce the NH4OH
Taken from Semiconductor International, pp. 86-89, June 1994
concentration in SC-1 by altering the
mixture ratio to 5:1:0.01-0.25. IMEC
engineers also found that the
chemicals used in this step have to be
ultraclean to avoid problems with the
decomposition of hydrogen peroxide
that is triggered by iron and copper
impurities at part per billion levels.
IMEC’s Marc Heyns says, “Such
work is an excellent illustration of
how a good understanding of the
basic physico-chemical mechanisms
involved is essential to develop
cleaning recipes for the deep
submicron technology era.”
The process temperature of SC-1
chemistry is also crucial. James
Milinaro, senior vice president at
SubMicron Systems, says, “The
ammonia concentration, therefore
cleaning effectiveness, depletes at an
alarming rate for higher process
temperatures.” He advocates point-
of-use ammonia concentration
monitoring to lengthen SC-1 clean
effectiveness and utilization.
Systems with automatic chemical
fill capabilities can also help to
control reagent strength and thereby
counter the unavoidable degradation
of hydrogen peroxide and
evaporative losses of NH4OH and
HCl. McConnel notes, “More
sophisticated systems include on-line
instrumentation to measure chemical
composition in real-time.”
In other work, Michael Olesen,
process engineering manager at
Verteq Process Systems, reports that
megasonic energy, along with
chemistry dilution, helps to remove
sub-0.2µm particles without
increasing surface roughness.
Molinaro adds that high power
acoustics (400-800 W) allow the SC-1
and SC-2 chemistries to operate at
lower temperatures. Lower
temperatures mean lower metallic
contamination and lower etch rate
with SC-1, and higher particle
removal efficiencies.
Indeed, studies at Sandia
National Laboratory (Albuquerque,
N.M.) and Santa Clara Plastics have
shown that acoustic energy can be
used to balance the “low temperature
and concentration” requirements for
controlling microroughening with
the “high temperature and
concentration” requirements for
particle removal efficiency.
In addition to the reduction of
microroughening and associated
improvements in device
performance, Kurt Christenson,
Ph.D., senior process physicist at FSI
International, sees other benefits for
pursuing dilute blend ratios in RCA
cleans: “Because DI water is
normally much purer that the
chemicals used, one way to improve
the purity of your process chemistries
is to further dilute them with pure
water.”
Equipment costs issues
Increasingly, the cost
savings associated with wet
chemistry wafer cleaning are directly
related to the equipment set (Table 2)
used to implement a clean:
• The trend with wet bench
systems for immersion processing is
smaller process vessels with
“cassetteless” operation and fully
robotic wafer handling within a
minienvironment. Here the
advantages include a substantial
reduction in chemical consumption
and shorter rinse times. These factors
generally increase overall
throughput, reduce equipment
footprint, and lower the cost f
ownership. Clearly, the cassetteless
concept has helped change wet
benches from expensive, time
consuming systems that occupy
enormous cleanroom space. For
example, Rosato explains that Santa
Clara Plastics reduced wet bench
footprint by changing from the
standard “poly” boat to a reduced
cassette design. “The use of
minienvironments also reduces
exhaust costs and relaxes the
requirements for the cleanroom,” he
says.
• The capabilities of spray acid
wet processing also has resulted in
savings. Brian Gardner, manger of
the applications laboratory at
Semitool, says, “Once considered too
expensive, spray processors are now
very cost-effective alternatives to
conventional wet bench technology
when considering price, footprint,
chemical consumption and facilities
requirements.” For future
applications, Semitool is developing
an automated high throughput batch
cassetteless processor featuring both
spray and immersion technology.
FSI’s Christenson notes that the work
of Ohmi has demonstrated
significant improvements in metallic
and organic contamination removal
when using spin-spray cleaning
techniques.
 Use of ozone
Ozone has been used by a
few semiconductor manufacturers as
a replacement for H2O2 in piranha
cleans since the early 1980s; the
advantages are a stronger oxidizing
effect and a reduction in metallic
contamination associated with liquid
chemicals. Several researchers have
suggested that ozone injected into DI
water can replace a piranha step used
for light organic cleaning; here
again, the main driving force is
reduction in chemical costs along
with lower chemical waste.
Some cleaning researchers are
suggesting that ozone can be more
widely applied. Indeed, McConnell
state that from the results of a
literature survey, CFM has concluded
that ozone has good potential for
oxidizing noble metals in the SC-2
step, but that its very short half-life
and low solubility in alkaline
solutions precludes its use for
growing silicon dioxide in the SC-1
step.
Chelating agents?
There is an older technique
that may find new use: Adding a
chemical chelating agent, such as
ethylenediaminetetra-acetic acid
(EDTA), to a cleaning solution to
bind and remove metallic ions as a
soluble coordination compound was
developed by Werner at RCA in the
late 1960s. More recently, this
technique has been investigated by
Ohmi and other Japanese engineers
and is likely being used in Japan.
David Bohling at Air Products
and Chemicals (Allentown, Pa.)
explains, “As critical contamination
thresholds diminish, the need for
chelating agents in wet clean
solutions will increase.” Bohling
explains that chelating agents can
reduce redeposition of metals in
solution, both by altering the
reduction-oxidation potential of the
metallic species and by reducing the
chemical activity of the species
through chelation. “Metal chelate
complexes are soluble in the various
wet cleaning baths as discrete
complexes. Equilibrium binding
constants for this chelation effect are
huge,” he says. Good results using
organic chelating agents, as has been
done at IMEC, should make
engineers look more positively on
this technique.
Where from here...
Taken from Semiconductor International, pp. 86-89, June 1994
In the past RCA cleaning • Sulfuric-based cleaning -
was a “cook-book” recipe; today wet IMEC’s proposal is for an H2SO4-
chemistry is truly a science. CFM’s H2O2 step followed by an HF step;
McConnell lists the achievements of among other advantages, this
this science: “Today we understand combination yields a native oxide-
the fluid mechanics of interfacial free surface, eliminates surface
phenomena such as droplets and roughening, drastically reduces
bubbles. We have calculated the metallic contamination, and lowers
contributions of various particle processing costs. This clean may also
adhesion forces. We have benefit from acid reprocessing
mechanistic models for various technology.
reactions including F etching. We So far, however, most users are
can measure and predict surface reluctant to stray too far from proven
roughness from excessive SC-1 RCA formulae. The consensus
treatment and from dissolved oxygen among experts is that the RCA clean,
attack on bare silicon. We can in its various forms, will continue to
quickly measure and control see extensive use in production lines
extremely low levels of metal manufacturing devices down to
contamination using analytical 0.35µm - and even 0.25µm and
techniques, and we have a better beyond. Rosato says, “Most
understanding of adsorption and development work on quarter
desorption equilibria for various micron devices has already been
ionic and metallic species.” demonstrated using standard wet
The challenges left for wet cleaning techniques.”
chemistry cleaning include a further What is more likely is a change
reduction of metallic and particle in dominance of conventional wet
contamination, and improved rinsing bench equipment sets for
efficiency. Enhanced drying implementing RCA-based cleaning,
techniques will also be needed, along especially as 300 and 400 mm wafers
with a better understanding of water are used in production. Spray
spots an their deleterious impact technologies offer a way around the
between films. Greater high chemical and water use
understanding of gate-oxide growth required for larger diameter wafers.
is need as well, especially relative to
hydrogen terminated silicon surfaces. Reference
Rosato says, “One of the biggest Kern, Werner, ed.,
issues for wet processing is to Handbook of Semiconductor Wafer
achieve a controlled chemical Cleaning Technology, Noyes
bonding state.” Wet chemistry Publications, N.J., 1993.
process costs, while not part of the
science, are also a challenge, perhaps
the challenge through the end of the
century: Users interviewed by
Semiconductor International stress the
importance of reducing chemical and
DI water consumption, and
increasing equipment utilization.
The solutions will likely come from
creative combination of chemistry an
equipment engineering.
Some researchers have suggested
that the future lies with an
alternative wet chemistry cleaning
technology. The most commonly
referenced possibilities are:
• HF-based cleaning - HF-last or
HF-only cleans result in low metallic
contamination, a hydrophobic
hydrogen-terminated oxide-free
surface, and a reduction in the
number of cleaning steps required,
meaning higher throughput and
lower costs. HF, especially
reprocessed HF, can be one of the
cleanest chemical available.
This page intentionally blank
 Appendix C
ECE 344 PHOTORESIST PROCESSING
Photoresist Chemistry
The ECE 344 lab currently uses AZ 5214 photoresist (PR) because it's safer than most and
because it can be processed as either positive or negative PR. It is also the choice of many of many
researchers. Since it costs ~$600 per gallon, it will never be competitive in large-scale production,
however. Luckily, the chemistries for all positive photoresists are similar so learning about this one will not
be for naught. Photoresists all contain 3 basic components: an organic polymer (usually novolak resin)
which is what "resists" etchants, a solvent carrier (usually an acetate) so it's a liquid for easy application by
spinning, and a photoactive component often called a sensitizer (usually a diazamine), which causes the
solubility to become dependent upon exposure to UV radiation.
AZ 5214 uses novolak polymer, propylene glycol monomethyl ether acetate (PGMEA) solvent,
and diazonaphthoquinone as the sensitizer. On the next page is the chemical reaction used to create the
novolak resin. Below that are the three distinguishable reactions undergone by the sensitizer attached to
the novolak matrix during exposure. Note that some water is actually required.
For image reversal (negative) processing the indenecarboxylic acid is decomposed by a post
exposure bake giving off carbon monoxide and rendering the sensitizer insoluble to the alkali developer.
The previously unexposed sensitizer can then be made soluble by a subsequent flood exposure. Since
there is no longer sensitizer in the previously exposed areas they will remain insoluble.
Most of the instructions for patterning with photoresist are included in this appendix, but the
operation of the Kasper mask aligners is described in Appendix G, and the operation of the Ultratech
steppers is described in Appendix H. Some specific variables, such as etch time, which mask to use and
whether to use the image reversal technique, are left to the experiment which references this appendix.
The tasks presented here take place in three locations and, therefore, are split accordingly into directions
suitable for posting at the spinner hood, the development station, and the PR removal station.
C.2
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Appendix C
 C.3
ECE344 Lab Manual
Appendix C
PREPARATION OF PHOTORESIST
(to be posted on the spinner hood)

Before beginning, record the conditions of the PR room and equipment by making entries in your
notebook. The wafer surface should be scrupulously clean before beginning this process.

1. Drive any moisture out of your wafer with a 2-minute bake on the bakeout hotplate (3 minutes if
the room humidity is >60%). While you wait, check that the spinner is set for a 30 second
duration.
2. Allow your wafer to cool on the "cool block" for 20 seconds. Wipe off the spinner chuck with a
Kimwipe while waiting.
3. Center the wafer on the spinner chuck and start the spinner by momentarily pressing the front of
the foot switch.
4. While the wafer is spinning, spray it with nitrogen from the N2 arm and check that it's spinning at
3000 rpm.

Vacuum is applied to the chuck only while spinning. You may stop the spinner by pressing the
back of the foot switch, but don't continue blowing nitrogen on it when it stops. The spinner will
automatically stop after the preset time.

5. While the spinner is spinning the wafer, drop 6 drops of hexamethyldisilazane (HMDS) onto the
center of the wafer and stop the spinner as soon as the appearance of the wafer remains
constant.

HMDS behaves as a surfactant, a wetting agent. It helps the photoresist adhere better. Think of it
much like a detergent. In this case, the organic end (hexamethyl-) of the molecule is similar to
and binds well to the organic PR. The silazane end, being silicon based, sticks well to the
wafer/oxide surfaces (this is a simplistic description of the mechanism - see if you can find the
actual mechanism in Grainger). It even seems to help adhesion on aluminum as well.

6. Immediately place 26 to 30 drops of AZ 5214 positive resist on and around the center of the wafer
using the filtered syringe. A pattern like that below works well for the first 9 drops. Use the last few
to fill in any voids between the drops. Use extra drops if necessary to fill all interior dry spots within
the PR puddle.
 C.4
ECE344 Lab Manual
Appendix C

7. Wait at least 5 seconds after the drops completely flow together, then start the spinner. This time,
let the spinner stop by itself.

Complete coverage of the wafer is critical to the operation of the steppers. There are targets on
the wafer which must not be etched away. If your wafer is not completely covered, ask your TA
since there are places which can be etched while still allowing the stepper to perform. Check the
uniformity of the resist by looking for a bull’s-eye effect - if you see it, it is not uniform (which is not
critical to our process - what problem does nonuniformity cause?). The thickness of the PR is
~1.6µm, and exhibits thin film interference effects, much like oxide. The color of the film is altered
by varying thickness.

8. Bake for 45 seconds on the Softbake hotplate.

9. Allow the wafer to cool for a few seconds on the "cool" plate.
10. The photoresist is now ready for exposure to ultraviolet light through a mask. Refer to the
instructions for the mask aligners (Appendix G) and steppers (Appendix H).
11. If image reversal is desired, expose for a dose of 125mW cm^2/sec. Follow the exposure by a 60
second bake on the reversal bake hotplate and a 20 second flood exposure. This may reduce the
development time unless more dilute developer is used.
12. Develop until pattern is sharp (see Development procedure to be posted on developer hood.)
13. Finally, complete the preparation of the PR for use as an etch stop by performing a 60 second
hardbake on the hardbake hotplate (currently the same as the softbake hotplate).
14. Cool the PR for a few seconds on the "cool" plate before putting it in the wafer carrier.
15. The photoresist is now prepared for the etch (or deposition if using the lift-off technique).
 C.5
ECE344 Lab Manual
Appendix C

DEVELOPMENT
(to be posted at developer hood.)

Two methods of development will be presented in lab. A standard artists air brush will be used to
continuously spray fresh developer on the wafer for 2” wafer development.. Dip development has the
advantage of not pitting the surface of the PR and is used for development of the 4” wafers, although
careful inspections must be followed since development slow as the PR loads up after multiple wafers
have been processed. In industry, 500rpm spinners beneath a low velocity nozzle are common.

Spray Development

1. It is strongly recommended that you change the D.I. rinses before beginning.
2. Open the faucet valve just barely enough to maintain a continuous stream (as opposed to a
sequence of individual drops.)
3. Hold the wafer horizontally over the sink at the counter top height with tweezers from the side.
4. Pick up the sprayer and your wafer (use tweezers for your wafer of course.)
5. Note the time on the clock at the back of the hood so you can measure the development interval.
6. Begin spraying downward at a steep angle next to the wafer from a height of 8" to 10". Try to
avoid getting any developer on your gloves.
7. Move the spray onto the wafer and employ a circular motion to make a uniform puddle form on
the wafer.
8. As soon as the puddle covers the wafer, use a spiral motion to move in to a distance of 4" + 1".
Let the developer puddle on your wafer. A radius of of motion of about .5" to .75" will help
counteract the fact that the UV illumination was strongest in the center. Keep the wafer flat so a
deep puddle protects the PR from the mechanical force of the sprayer at this distance. All the PR
is soluble, it's just a matter of degree.
9. Spray until the pattern is sharp, approximately 35-40 seconds for the positive lithographic process.
Pay most attention to the test areas. They will quickly cloud up with a pattern of multicolored blobs
as the PR gets so thin that interference effects cause all the colors of the rainbow to be
accentuated by the continuum of PR thicknesses. When they seem clear and uniform (or don't
seem to change for 5 seconds), quit.
10. Quickly quench the developer in the first DI rinse and return the sprayer to its holder. Be careful
not to break your wafer by swishing it too fast in the rinse.
11. Note the time.
12. Move to the FINAL RINSE tank for at least 10 seconds while you calculate the total time spent
developing.
 C.6
ECE344 Lab Manual
Appendix C

13. Gently rinse your wafer with DI from the faucet (near the nozzle) and N2 dry (NO IPA.) Excessive
water velocity can pit the surface of the PR. Although this is not usually a problem, it does look
bad until the PR is removed. Fresh DI from the sprayer is used in case the rinse tank has enough
PR in it from previous students to deposit a thin invisible film on the wafer. Students may change
the DI rinse at their own discretion.
14. Return the wafer to the carrier face up.
15. Gloves and tweezers should be rinsed in D.I. if developer is suspected on them. Used developer
is highly water soluble, but can be difficult to remove if left to dry on things.
16. Inspect the development under a UV filtered microscope. Pay particular attention to the smallest
windows to be opened. They may take a little longer to develop because it's harder for fresh
developer to reach the bottom to dissolve the PR. Gross under development will appear as
splotches with multicolored rings in the larger areas which should be clear of PR. Why? Ignore the
outer rim of the wafer because edge beading of the PR causes it to be too thick to expect proper
patterning.
17. Repeat in 10-second intervals if necessary.
 C.7
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Appendix C

4” Immersion Development
1. It is strongly recommended that you change the D.I. rinses before beginning.
2. Open the faucet valve just barely enough to maintain a continuous stream (as opposed to a
sequence of individual drops.)
3. Make sure there is sufficient developer in the developing container to cover the entire wafer. If not
ask your TA to fill it.
4. Load your wafer into the 4” wafer holder.
5. Check the number of times that the developer has been used on its check sheet. If you are the
first user, you will develop for 40 seconds. Each additional use will add 20 seconds to the
development time (i.e. use 2 will be 60 seconds, etc.), up to a maximum of three uses.
6. Note the time on the clock at the back of the hood so you can measure the development interval.
7. Immerse the wafer and holder into the developing container and begin timing.
8. Gently agitate the wafer holder and develop for the time determined from above.
9. Quickly quench the developer in the first DI rinse. Be careful not to break your wafer by swishing it
too fast in the rinse.
10. Note the time.
11. Move to the FINAL RINSE tank for at least 10 seconds while you calculate the total time spent
developing.
12. Gently rinse your wafer with DI from the faucet (near the nozzle) and N2 dry (NO IPA.) Excessive
water velocity can pit the surface of the PR. Although this is not usually a problem, it does look
bad until the PR is removed. Fresh DI from the sprayer is used in case the rinse tank has enough
PR in it from previous students to deposit a thin invisible film on the wafer. Students may change
the DI rinse at their own discretion.
13. Unload the wafer from the wafer holder.
14. Return the wafer to the carrier face up.
15. Gloves and tweezers should be rinsed in D.I. if developer is suspected on them. Used developer
is highly water soluble, but can be difficult to remove if left to dry on things.
16. Inspect the development under a UV filtered microscope. Pay particular attention to the smallest
windows to be opened. They may take a little longer to develop because it's harder for fresh
developer to reach the bottom to dissolve the PR. Gross under development will appear as
splotches with multicolored rings in the larger areas which should be clear of PR. Why?
17. Repeat in 10-second intervals if necessary.
 C.8
ECE344 Lab Manual
Appendix C

Discussion
The solubility change during exposure of photoresist is a couple of orders of magnitude at best
(although chemists are constantly improving it). Consequently, all the PR will eventually dissolve in the
developer. Before that happens the openings in the PR will widen and loose their sharpness. Therefore,
development time should be minimized. The smallest windows which are to be opened are usually the
limiting factor because fresh developer must diffuse down to the surface in order to do its job. This
diffusion is slowed when the width of the window in the PR is comparable to its depth. A possible
technique to minimize this effect would be to hold the wafer at an angle so the PR could not puddle.
Unfortunately, PR adhesion and sprayer uniformity become greater problems (at least in ECE 344 lab). A
compromise seems to be the best solution. Periodic tilting of the wafer to help change the developer in
the small windows is suggested. Exactly how often is optimum has not been determined. Record any
useful observations you make which would help in your notebook.
 C.9
ECE344 Lab Manual
Appendix C
PHOTORESIST REMOVAL
(to be posted on developer hood)

1. After the etch, the PR may be removed by ONE of the following three methods. Do not try one of
the other methods before performing the microscope inspection step.
1.1. Use acetone, PGMEA, or other solvent to remove the majority of the PR by making a puddle
of the solvent on the wafer while holding it level above the proper waste container. Pour the
solvent off after 10-15 seconds and repeat until there is no significant improvement. Then
degrease it in the "PR" degreaser for 1 minute (if TCE is available), squirt with acetone, IPA,
water, IPA again, and N2 dry.
1.2. Use the plasma asher. See http://www.ece.uiuc.edu/ece344/equipment/Asher/Instructi
ons.html for instructions. This is the most reliable method, but also the most time consuming.
Please try it at least once during the semester.
1.3. Use acetone, PGMEA, or other solvent to remove the majority of the PR as in the first
method. Then use heated Posistrip, Microposit Remover, or other proprietary positive PR
remover. DI rinse, N2 dry.
2. Inspect for residual PR under a microscope (preferably outside the wet lab).

Pay particular attention to the rim of the wafer where edge beading during the spin on process left
extra thick PR. Removing the yellow UV filter from the illuminator will help you see PR, but be
sure to return it. The residue will often look similar to slightly underdeveloped PR. Since such
residues are likely to be very thin with respect to visible light wavelengths, they often take on a
rainbow of colorations as the thickness variations cause different interference patterns. PR is a
furnace contaminant and must be completely removed. The whole class is counting on you keep
the furnaces clean.

3. If PR residue is detectable, go back to step 1. If there is only a little left, additional soaking with
acetone will usually take care of it. Stubborn PR may need the plasma asher however.
Occasionally, etched features will look like PR residue so consult with your instructor before going
back to step 1 a third time.
This page intentionally blank
 Appendix D
HOT POINT PROBE

A basic electrical property of semiconductor materials is their type of conductivity, i.e., whether
their majority carriers are holes (p-type) or electrons (n-type). This property is very quickly and simply
determined by employing the hot point probe. It is also a quick way of determining if all the oxide has been
removed from a test area.
The free carriers in a semiconductor behave in some ways as a gas of charged particles, a
plasma. Just as heat makes a gas expand (PV=nRT), the hot point makes carriers expand away from the
contact point. The charge of the dominant carrier species (electrons or holes) determines the direction of
the net current flow. A small component of the net current may be due to the heat reducing the probability
that carriers remain confined spatially around their associated dopant atoms, but room temperature is so
high (above absolute zero) that virtually all dopant atoms are already "excited." The extra excitation is
negligible. Carrier pair generation caused by the heating does not affect this measurement since the
current components from thermally generated electron-hole pairs would cancel. Note that the
measurement situation is a non-equilibrium condition.

Operating Instructions
1. Turn on the power supply. This starts heating the tip.
2. Turn on the picoammeter. Make sure it's in "Auto" scale mode.
3. Load your wafer.
3.1. Move the wafer chuck all the way toward the front.
3.2. Place your wafer on the chuck. Be careful not to hit the probe tips. As long as the test area is
on the chuck, centering is not important. Do not bother to slide the wafer beneath the tips, it
will only make it difficult to remove.
4. Probe the wafer.
4.1. Use the x-y stage to position the appropriate test area beneath the probes. Plastic "spokes"
on the chuck allow rotation of the wafer. One is broken already.
4.2. Watch the probes closely as you use the green button to lower them onto the wafer.
Excessive "skating" can scratch the wafer. Control of the probe descent is enhanced if you
simultaneously apply some pressure to the white button while the green button is pressed.
Consult your instructor if you suspect the prober needs adjustment. Please do not re-adjust
any of the knobs on the probe assembly unless you know how to properly reset them.
5. Interpret the reading
5.1. Trace the wires to determine which direction the picoammeter is connected into the circuit. Is
its positive reference input (center conductor if it uses a BNC connector) connected to the hot
or cold tip? Note the red and white dots on the holders for the probe tips. These correspond
to the similarly colored banana jacks.
 D.2
ECE344 Lab Manual
Appendix D

5.2. Type determination. The picoammeter registers a positive current when direct current flows
into its positive reference input. We leave it up to you to decide which sign on the
picoammeter's display corresponds to which conduction mechanism in the semiconductor. A
solid reading in the nanoamp range is sufficient. It may climb slowly as the hot point heats up.
No reading means either that the circuit is open (possibly from dirty tips), the tip is not hot. Or
that the material is either insulating (oxide) or intrinsic (compensated). Consult your instructor
if you have reason to believe that prober has a problem. Usually, oxide is the problem.
6. Remove the sample.
6.1. Use the white button to raise the tips.
6.2. Use the x-y stage to bring the wafer out from under the tips.
6.3. Remove the wafer from the chuck. A drop of water can make a wafer stick to flat surfaces
with enough force that it's possible to break the wafer by lifting it straight up. If the wafer
resists lifting, slide it off.
7. Turn off the picoammeter and power supply unless someone else is going to use it next. Since the
tips are so close, continuous heating may warm up the "cold" point and reduce the sensitivity of
the apparatus, but the main reason for turning off the power supply is that we don't have a spare
heater. So don't skip this step!
 APPENDIX E
Four Point Probe
Resistivity (ρ) is a particularly important semiconductor parameter because it can be related
directly to the impurity content of a sample; see GT section Figure GT-1. These plots have been
determined experimentally and are specifically valid for homogeneous single crystals of Silicon at room
temperature (300 K). The four point probe is the apparatus typically used to determine bulk resistivity, and
in conjunction with plots like GT-l, permits one to ascertain the impurity content of a given sample.
Note that the mobility of the carriers depends upon temperature, crystal defect density, and ALL
impurities present. If your sample differs in these respects from that used to determine the empirical GT-1
curves, the actual dopant concentration you determine will only be close, not exact. Hall effect
measurements can determine the mobility of the carriers in a given sample to allow for more accurate
dopant concentration measurements, but Hall measurements are usually destructive to the sample. We'll
use the GT-1 curves.
The four point probe, as depicted schematically in Figure 1, contains four thin collinearly placed
tungsten wires which are made to contact the sample under test. Current I is made to flow between the
outer probes, and voltage V is measured between the two inner probes, ideally without drawing any
current. If the sample is of semi-infinite volume and if the interprobe spacings are s1= s2 = s3 = s, then it
can be shown that the resistivity of the semi-infinite volume is given by

ρ=
( 2πs)V (1)
I

Figure 1
 E.2
ECE344 Lab Manual
Appendix E

The subscript o in the preceding equation indicates the measured value of the resistivity and is
equal to the actual value, ρ, only if the sample is of semi-infinite volume. Practical samples, of course, are
of finite size. Hence, in general, ρ != ρo. Correction factors for six different boundary configurations have
been derived by Valdes.(1) These show that in general if l, the distance from any probe to the nearest
boundary, is at least 5s, no correction is required. For the cases when the sample thickness is <= 5s, we
can compute the true resistivity from
V
ρ = a 2πs = aρo (2)
I
where a is the thickness correction factor which is plotted on page GT-2. From an examination of
the plot we see that for values of t/s >= 5 the corresponding value of a is unity. Thus for samples whose
thickness is at least 5 times the probe spacing, no correction factor is needed. Typical probe spacings are
25-60 mils and the wafers used in most cases are only 10-20 mils, so unfortunately we cannot ignore the
correction factor. Looking again at the plot, however, we see that the curve is a straight line for values of
t/s <= 0.5. Since it is a log-log plot the equation for the line must be of the form
m
t
a = K  (3)
 s

where K is the value of a at (t/s) = 1, and m is the slope. Inspection of the plot shows that in this
case m = 1. K is determined to be 0.72 by extrapolating the linear region up to the value at (t/s) - 1. (The
exact value can be shown to be 1/(2 ln 2).) Hence for slices equal to or less than one half the probe
spacing
a = 0.72 t/s
When substituted into the basic equation we get:
V V
ρ = a 2πs = 4.53t for t/s ≤ 0.5 (4)
I I
All samples we will be using in the lab satisfy the one-half relationship so we can use the above
formula to determine ρ. We will perform resistivity measurements on the starting material for each
experiment. The value of r obtained will be referred to as the bulk resistivity, and the units are Ω-cm.
If both sides of Equation (4) are divided by t we get
Rs = ρ/t = 4.53 V/I for t/s ≤ 0.5 (5)
which we refer to as sheet resistance. When the thickness t is very small, as would be the case
for a diffused layer, this is the preferred measurement quantity. Note that Rs is independent of any
geometrical dimension and is therefore a function of the material alone. The significance of the sheet
resistance can be more easily seen if we refer to the end-to-end resistance of a rectangular sample.
From the familiar resistance formula

R = ρ l/wt (6)
we see that if w = l (a square) we get
R = ρ/t = Rs
Therefore, Rs may be interpreted as the resistance of a square sample, and for
this reason the units of Rs are taken to be Ohms per square or Ω/ . Dimensionally this
is the same as Ω, but this notation serves as a convenient reminder of the geometrical
significance of sheet resistance.
 E.3
ECE344 Lab Manual
Appendix E
So far in our discussion of resistivity measurements we have assumed that the size of our sample
is large compared to the probe spacing so that edge effects could be ignored. This is usually the case for
the bulk resistivity measurement. However, our sheet resistance measurements will be made on a "test
area" on our wafer and the test area dimensions (nominally 2.9 by 5.8mm) are not that large compared to
the probe spacing (25 mils). In order to get accurate measurements we will need to correct for the edge
effects. The figure on page GT-3 gives the correction factors for two common sample geometries.
In general then
Rs = C V/I (7)
where C is the correction factor.
Note that for d/s > 40, C = 4.53, the value we had as the multiplier in Equation (5).

References

1. Valdes, L. G., Proc. I.R.E., 42, pp. 420-427 (February 1954).

2. Smits, F. M., "Measurements of Sheet Resistivity with the Four-Point Probe," BSTJ, 37, p. 371
(1958). (Same as BT Monograph, 3894, Part 2).
 E.4
ECE344 Lab Manual
Appendix E

The VEECO Four Point Probe

The Veeco four point probe provides a constant current which flows between two outer probes
and then measures the voltage across the two inner probes to obtain the fundamental V/I parameter.
For the bulk resistivity measurement, the relevant formula is
ρ = 4.53 t V/I
For sheet resistance measurements the formula is
Rs = C V/I
and the measured V/I value is multiplied by C (this value is already set on the probe). Refer to
Fig. GT.3 for correction factor determination, but divide the number by 4.53 for the Veeco. The probe
spacing S is 25 mil.
The Veeco can penetrate thin insulating surface layers by applying a short 170v pulse to the
probe tips when the PENETRATE function is selected. Then, after making the resistivity measurement,
the unit can determine the type of the semiconductor. For low resistivity samples the type is determined
by applying an ac signal between two probes and monitoring the dc bias of the wafer with a third probe.
Lightly doped semiconductors will form rectifying contacts with the probe tips causing the wafer bias to go
up (positive) for N type material and negative for P type material. Highly doped semiconductors will not
develop a conclusive wafer bias, but the applied ac signal can heat such material sufficiently for
observation of the thermoelectric effect (as in the hot-point probe). If neither method is conclusive, both N
and P indicators will flash.
NOTE: The electronics does not always know when the tests for conductivity type are
inconclusive. If it disagrees with the hot point probe, disregard it.

Operation
1. For Bulk Resistivity: press <SLICE RES> and dial in the wafer thickness (including the units!)
2. For Sheet Resistance: press <SHT. RES> and dial in the posted geometry correction factor.
3. For V/I ratio: press <V/I>.
4. Press the <Type Auto> button in.
5. Lift cover and place wafer on the glass plate. Center the 4 probes in the test area by lowering the
probes (depress bar in front manually) until they are just above, but NOT TOUCHING, your wafer.
Adjust the glass plate until your test area is centered.
6. Lower cover. Depress and hold down cover using the front lip of the cover. Press <retest> until
you get two consecutive readings that are the same with the possible exception of the least
significant digit. Record the values. If different from the 1st value, average the two numbers.
7. With the cover still held down, press <Rev. Curr> twice and record the values. Disagreement with
the other values may mean a tip is bent or a poor contact exists. 10% agreement is acceptable.
8. Average the four measurements. Note that the readings are in mΩ, Ω or kΩ as per the LEDs on
the display. If measuring Rs, units are (m,K) Ω/ .
If measuring ρ, units are (m,K) Ω-cm.
 APPENDIX F
Lindberg/Tempress 8500 Dual Stack Furnace Bank
In general the furnaces in the cleanroom are kept at a standby temperature of 600°C for the drive
and oxidation furnaces, and 400°C for the solid source predeps. A higher temperature standby condition is
not utilized because the life of the furnace core windings decreases rapidly at elevated temperatures. The
furnaces are not completely shut off when not in use because the cycling of temperature from below
275°C to above 1100°C devitrifies (crystallizes) the quartz tubes. The term "quartz" is a common
misnomer implying crystallinity. The material is actually anything but crystalline. Although a thin surface
layer of crystal (cristabolite) is beneficial, only ultra-high purity and totally amorphous SiO2 has the
properties needed in a diffusion furnace tube. Extreme temperatures and thermal gradients are
experienced by the furnace tubes. They also provide a barrier to contaminants and are themselves
"clean."
The ECE 344 furnaces can provide pyrogenic steam (combustion of hydrogen and oxygen within
the chamber) when rapid oxidation is required. Proper interlocks and sensors make the process relatively
safe. Silicon is not the only material that gets oxidized in the furnaces. The boron source wafers, actually
boron nitride, are oxidized to form a B2O3 layer prior the predeposition run (usually by a TA). It is the oxide
which has a significant vapor pressure at the diffusion temperatures. B2O3 reacts with silicon to form SiO2
with an extremely high concentration of boron. The wafers used for phosphorus predeposition are made
with SiP2O7 on a fine SiO2 matrix. The SiP2O7 decomposes at diffusion temperatures to form P2O5 which
vaporizes and reacts with silicon. The student is encouraged to balance the predeposition reactions (or to
read section 6.14 of Anner) since they are basic to understanding how you make ICs and are, therefore,
excellent lab final material.
The furnace is divided into two sides: manual loading and autoloading. This arrangement allows
you to experience first hand the advantages and disadvantages of both types of systems.

Control
The furnaces are controlled either by a Digital Temperature Controller (DTC) on the manual side,
or a combination of a DTC and a Digital Process Controller (DPC) on the autoloader side.

DTC
The DTC is a PID (Proportional, Integral, Derivative) controller, which in simplest terms means
that the temperature can be ramped extremely fast with no overshoot, allows for quick recovery during
thermal loading (loading in a cool boat full of wafers), and very stable setpoint temperature maintenance
(±0.1 °C deviation).
The input for the temperature control comes from two types of thermocouples: spike and paddle.
There are three type R spike thermocouples on the outside surface of the chamber, located in the center
of each heating element (source, center, and handle). These are used during the normal operation of the
furnace, although the temperature read by the TCs is different from the actual temperature that the wafers
(inside the chamber) are at. There is also one type BX paddle thermocouple which is inserted inside the
chambers. This TC is used to calibrate the setpoints required for the spike TCs to achieve the desired
temperature on the inside of the furnace. The paddle TC can also be used to control the furnace
temperature once it is inside the chamber.
 F.2
ECE344 Lab Manual
Appendix F

DPC
The DPC is used in conjunction with the DTC on the autoload side of the furnace. Its function is
to allow for automation of the furnace since there are more operations going on other than just
temperature control. The DPC consists of a microprocessor interfaced with analog and digital inputs and
outputs.
The digital inputs currently are used for location setpoints for the cantilever loading system. The
digital outputs are used for the control of the stepper motors in the loading system. Currently, the analog
I/O is not used, but will be used in the future for control of mass flow controllers (MFCs). The digital
outputs can also be used for control of additional equipment, and will be used for solenoid valves in the
future.
The DPC is also the master of the DTC when the two are connected, disabling manual setting of
temperature through the DTC. The DPC will set the correct temperature recipe in the DTC based on the
program input into the DPC.
The DPC can contain up to 16 programs which are input through a simple programming recipe.

Overtemp Modules
The furnace is also equipped with overtemperature detection which prevents accidental melt down
of the quartz chambers in the event of equipment failure. There are three TCs per chamber which provide
redundancy to the spike TCs - if the temperature rises above the overtemp setpoints, the system will trip
off the circuit breakers supplying power to the individual furnaces.

Hydrogen
To create pyrogenic steam, hydrogen and oxygen are combusted in the chamber. The presence
of hydrogen and oxygen together can be a potentially dangerous situation, but is minimized with proper
interlocks. The furnace gas delivery system is interlocked to prevent the introduction of hydrogen if two
criteria are not met:
low temperature: the furnace temperature must be >800°C for spontaneous combustion
gas ratio analyzer: the quantity of hydrogen is greater than the stoichiometric ratio
required for complete combustion of hydrogen
A hydrogen gas detection system is also present to detect any potential leaks or failures of the
interlocks. There are three monitoring points designed to detect the presence of gas when it exceeds 5%
LEL (lower explosion limit). This system is connected to a local alarm system which is activated by the
low alarm (5% LEL) to warn of a potential release. If the high alarm (10% LEL is activated, the system will
sound the building alarm to provide for evacuation and the notification of the fire department.
 F. 3
ECE344 Lab Manual
Appendix F
Furnace Operating Instructions
FURNACE LOADING: Manual

The ECE 344 diffusion furnaces are very much like those described in Appendix H of Anner's
Planar Processing Primer. Refer to it for construction details. The following instructions are for manual
operation, however.
CAUTION: Quartz hot enough to severely burn does not necessarily look any different than
cool quartz. Quartz is also extremely expensive and can be ruined by contamination. The 6"
furnace tubes cost over $1000, the boats over $200. The worst thing a student can do is to
knowingly spread contamination from, say a small piece of burned glove on a boat, to the other
quartzware and, consequently, to the wafers of classmates. IF YOU SUSPECT ACCIDENTAL
CONTAMINATION, NOTIFY THE INSTRUCTOR IMMEDIATELY! Do not worry about your letter
grade.

1. Verify that the furnace is at the proper temperature for the processing step by checking the
temperature setting on the Digital Temperature controller for the chamber you are using.
a) If the actual temperature (TA) of the three zones is not displayed, press the following keys:
i) <clear and display>
ii) <temp>
b) You can check individual setpoints (SP) and actual temperatures (TA) by pressing:
i) <1> = handle
ii) <2> = center
iii) <3> = source
iv) <0> = all three zones (default)
2. Check that the gas panel power is ON and that it is in the MANUAL mode.
3. Check that only nitrogen is flowing in the furnace.
4. Put on the high temperature gloves over your latex gloves.
5. Put on the high temperature gloves and unload the boat from the mouth of the chamber.
6. Carefully place the boat on the quartz plate located on the stainless steel table.
7. Remove the high temperature gloves.
8. Load your wafer into the boat.
 F.4
ECE344 Lab Manual
Appendix F

If doing a predep, the wafer should face the nearest source wafer. Otherwise it should not
matter, but note which way it is loaded as a matter of good scientific practice. In the case of
predeps, use the diagram below to determine the boat position of your wafer for the electronic
logsheet entry. It will help if you observe the dimensions of the boat now since you will have to
hook it at a considerable distance without damaging the wafers later. Dummy wafers are used
in all the boats not only for protection from the pull rods, but because the first and last wafers
experience different gas flow conditions.

Gas Flow

10 98 76 54 32 1

Silicon
Source wafer
Dummy wafer

9. Put on the high temperature gloves.

10. Reload the boat into the mouth of the chamber.
11. With the high temperature gloves, use the appropriate long pull rod to slowly push the boat until
the tape mark is flush with the scavenger hood face. Each furnace has its own long pullrod.
12. Allow the pull rod to cool for several seconds before returning it to the quartz storage tube.
13. Switch gases as the "recipe" dictates.
 F. 5
ECE344 Lab Manual
Appendix F

FURNACE UNLOADING: Manual

The unloading procedure is basically the same with the obvious differences that the long pull rod
must be used to retrieve the boat from the center of the furnace and wafers will be removed from the boat.
1. Put on the high temperature gloves over your latex gloves.
2. 30 second slow pull. Pull the boat to the mouth of the furnace using the long pull rod for that
furnace.

Depth perception helps a great deal in hooking the boat when it's in the middle of the furnace.
Remember, the boat was left where the tape lined up with the face plate. It may help to gently
touch the boat without lifting the pullrod in order to calibrate the depth. It also helps to use the
end of the furnace tube as a fulcrum and pivot the hook upward as you hook the boat. Avoid
touching the wafers with the rod. Pulling too fast will result in an abnormally high sheet
resistance because a significant number of atoms will be frozen off lattice sites, making them
inactive.

3. Allow the pull rod to cool for several seconds before returning it to the quartz storage tube.
4. Use the lifting fork to move the boat to the quartz disc. Leave the fork in the boat.
5. Unload the boat. Remember, it's hot!

Hold the wafers in air for 10 seconds or so to cool before placing them into the plastic
wafer carriers. Although wafers cool very fast, the quartz boat will retain heat and keep
wafers hot for a relatively long time. What implications does this have on the "real"
diffusion time?

6. Reload the boat into the mouth of the chamber using the lifting fork and high temperature gloves.
 F.6
ECE344 Lab Manual
Appendix F

Autoload Processing
To run the process recipe for the autoloader side of the furnace, press the following keys on the DPC:

1. <clear and display> repeatedly until DISPLAY of PROCESS NAME appears (where PROCESS
NAME = BORON DRIVE, PHOSPHORUS PREDEP, or GATE OX)
2. <run/halt>
3. Make sure the display says EMPTSTMCN1 RUN? If not, press:
a) <recipe>
b) <1>
c) <enter>
d) <clear and display>
e) <run/halt>
4. The display should now read EMPTSTMCN1 RUN?
5. <enter>

The process is totally automatic for the Phosphorus Predep. Additional steps must be taken for the Boron
Drive:

1. When the elephant and boat are fully loaded into the chamber the display will read: <START
GASES>
2. As soon as this is displayed, flow your gases as specified in the lab manual and begin timing.
3. When the process is complete, press <clear and display>
4. Press <run/halt>
5. Press <enter>

The furnace will then continue the recipe and unload.

 APPENDIX G
KASPER MASK ALIGNERS
A mask aligner must serve two important functions. First, it must provide means for moving a
semiconductor wafer relative to a photomask so that the diffused regions in the wafer may be positioned
or aligned with great accuracy relative to the photomask pattern. A microscope system is usually provided
so that the alignment may be checked visually.
Secondly, the aligner must provide means for holding the photoresist-covered wafer in intimate
contact with a photomask during exposure to ultraviolet light. A third ancillary function is the inclusion of a
UV source and system of exposure control.
The Kasper Mask Aligners are relatively sophisticated units that have all these features. A fine
micropositioner allows precise alignment of wafer to mask, both of which are vacuum-held to chucks. The
microscope system incorporates split optics which allow simultaneous checking of alignment in two
different regions of the pattern.
After alignment is completed the wafer is moved upwards and held tightly against the mask by air
pressure. A UV source and associated timer are incorporated for photoresist exposure.
The Kasper units were designed for commercial production and provide automatic application of
vacuum and pressure to the wafer chuck when the wafer is placed in the alignment position. In addition it
will automatically load and eject the wafer.
For use in the Undergraduate Integrated Circuit Fabrication Laboratory several of these automatic
features may be bypassed to help you understand the aligner operation and to minimize wafer damage
which can result if the automatic controls malfunction.
It is essential that you follow these instructions step-by-step to avoid damage to the aligner, the
mask, and your wafer. The instructions were written for the operation of the Kasper 2001. The wet lab
has two of the model 2001s and, therefore, they are the most convenient to use.
First familiarize yourself with the aligners. With the aid of Figures G-1 and G-2 and the description
on the following pages locate the parts and controls.
G.2
ECE344 Lab Manual
Appendix G

Figure G-1
Kasper 17A Mask Aligner - Top View
 G.3
ECE344 Lab Manual
Appendix G

Schematic Not Available

Figure G-2
Kasper 2001 Mask Aligner - Top View
 G.4
ECE344 Lab Manual
Appendix G
Position and Definition of Controls, Connectors, and Indicators
Item 1: AUTOMATIC EXPOSE SWITCH
Activating this switch causes the system to automatically expose when in contact mode and the optical
turret is in the expose position.
Item 2: MANUAL EXPOSE SWITCH
Activating this switch causes the exposure of the wafer to occur. After exposure, the wafer is automatically
ejected from the chuck to the wafer tray and the chuck returns to the proper position for loading another
wafer.
Item 3: FINE FOCUSING KNOB
Optimum simultaneous focusing of the wafer and mask is achieved by rotating this knob only when using
Split Field Microscope.
Item 4: SEPARATION SWITCH
Activating this switch separates the wafer from the mask by an amount determined by the setting of Item
12. The wafer is in the separation position as long as the switch lamp is lighted. Both scanning and aligning
can be done with the wafer in this position.
Item 5: CONTACT SWITCH
Activating this switch causes the wafer to be brought in contact with the mask. Scanning can be performed
with the wafer in this position. Exposure is accomplished with the wafer in this position.
Item 6: EXPOSURE TIMER
The exposure time is indicated by the position of the red dial pointer. The exposure time is adjusted by
rotating the knob on the face of the timer.
Item 7: SCANNING DISC LOCK
Pushing this button allows the scanning disc to be moved. This disc is movable as long as the button is held
down. Releasing the button locks the mask in relation to the eyepieces.
Item 8: SCANNING DISC
Movement of this hand disc causes simultaneous X-Y movement of the wafer and mask in relation to the
eyepieces.
Item 9: SPLIT FIELD LENS SEPARATOR ADJUSTMENT
The separation between the two split field objective lens is changed by rotating this knob.
Item 10: ROTATION ADJUSTMENT
The fine rotational alignment of the wafer to the mask is accomplished by rotating this knob. On the Kasper
2001, after several turns in the fine adjust mode, the ratio will change to a coarse mode.
Item 11: WAFER POSITION ADJUSTING SCREW
The position of the wafer when loaded on to the chuck can be adjusted by loosening this screw and
adjusting the wafer load arm position.
Item 12: MASK AND WAFER SEPARATION ADJUSTMENT
The amount of separation between the mask and the wafer is set by rotating this knob.
Item 13: BINOCULAR MICROSCOPE HEAD
Focusing of the eyepiece (left) is done by rotating the left eyepiece barrel, only for Row & Column
Microscope.
Focusing of the right eyepiece is done by rotating the right eyepiece barrel, only for Row & Column
Microscope.
Item 14: WAFER LOAD SWITCH
Activating this switch causes the wafer loading arm to load a wafer on the chuck and return, and then
causes the wafer chuck to raise into the contact position and lower to the separation position.
Item 15: COARSE ROTATION LOCK
On the 17A, the coarse rotational alignment of the wafer to the mask is accomplished by loosening this
knob and sliding the rotation assembly in the desired direction. This control is not present on the 2001.
Item 16: ALIGNING DISC
Movement of this hand disc causes X-Y movement of the wafer in relation to the mask and the eyepieces.
 G.5
ECE344 Lab Manual
Appendix G
Item 17: ALIGNING SELECTOR
With the button released, fine alignment motion is achieved by motion of the hand disc. With the button
depressed, coarse alignment motion is achieved.
Item 18: POWER SWITCH
Activating this switch turns the instrument electrical power on. The power is on as long as the indicator lamp
is lighted. Reactivating this switch turns the power off.
Item 19: MASK LOAD SWITCH
Activating this switch causes the optics head containing the binocular head and optics turret to raise to a
position sufficiently high for conveniently loading a mask in the mask holder. Reactivating this switch
causes the optics head to lower to the normal operating position.
Item 20: ILLUMINATION INTENSITY CONTROL
The intensity of the tungsten light can be adjusted by rotating this knob.
Item 21: VISUAL ALIGNMENT SWITCH
Activating this switch causes the optics head to raise without unlocking the mask plate. (also labeled HEAD
LIFT)
Item 22: EJECT SWITCH
Activating this switch causes the eject arm to eject a wafer from the chuck to the wafer tray and can be
activated at any stage of the operation. The principal utility of this switch is to remove a wafer from the
chuck without exposure since the exposure switch function normally causes the wafer to be ejected after
exposure.
Item 23: WAFER MANUAL LOAD SWITCH
Activating this switch causes the chuck to be raised to the contact position and then lowered to the
separation position. This switch is intended for use only when a wafer or chip has been hand loaded to the
chuck. (also labeled LOADED MANUAL)
Item 24: VAC CHUCK
2001 only. Please leave this switch OFF. It only affects what happens in the CONTACT mode. If activated,
a seal ring would be pressed against the mask and the space between the mask and wafer evacuated.
Fewer things can go wrong with it off. Then, in contact mode, the wafer is pressed into the mask by an air or
nitrogen pillow applied through the vacuum holes.
Item 25: P. LOCK
2001 only. Proximity Mode Switch. Please leave this switch OFF. It affects the WAFER LOAD process.
Item 26: CALIB.
2001 only. Please leave this switch OFF. It is for an option we don't have.
 G.6
ECE344 Lab Manual
Appendix G

2001 Operation

Start-Up (This should have been performed by the TA)

1. Compressed air supply ON - 60 psi.
2. Vacuum source ON.
3. Lamp power supply - ON and started (10 minute warm-up).
4. Cycle the wafer chuck up and down, then turn off the POWER switch (18).
Mask and Wafer Loading
1. If the U.V. light does not seem to be ON, notify your instructor.
2. Turn the aligner POWER switch (18) ON.
3. Press the VISUAL ALIGN switch (21) (may also be labeled HEAD LIFT). The optical head will rise
to its upper position.
4. Press the MASK LOAD switch (19).
5. Open the mask holder against the stop.
6. Kasper 17A only: Center the Coarse Rotation adjustment within it's mechanical limits. Losen the
Coarse rotation lock (15) 1/4 turn and push or pull it to center it. Relock it in position using a small
amount of torque.
7. Place the wafer on the center of the vacuum chuck. It is recommended that you keep the wafer
flat toward you.
Kasper 2001 only: Try to place the wafer such that the flat is bisected by the notch of the chuck
(see diagram). The Kasper 2001 will have the vacuum chuck ON at this point. If a large amount of
position or rotation error exists, press EJECT and try again. It does not have to be perfect and it
may be dangerous to attempt to push the wafer around with the vacuum applied.

Wafer on Kasper 2001 chuck

 G.7
ECE344 Lab Manual
Appendix G

8. Place the mask against the three alignment pins of the mask holder plate. The chrome side
should be facing you.

The ECE 344 mask set will appear right side up when viewed through the microscope if the
one test area window which is opened on each of the five mask layers is on the left when
you load the mask. It is the largest of the three test area widows which are opened on the
first mask. See appendix I for more information on the test area. If the mask is labeled, the
label should be at the top and readable when the mask holder is in the load position.

9. Lower the mask holder; be ready to catch the mask with your hand in case it falls as the holder
passes vertical.
10. Again press the MASK LOAD switch (19), and press down firmly on both sides of the mask holder
plate to insure vacuum hold down. Pull up lightly on the mask holder to check that it is held down
firmly.
11.Press the LOADED MANUAL switch (23) and wait for the chuck to cycle into separation mode
after rising into contact with the mask. The SEPARATION switch (4) should be illuminated.
NOTE: To stop the process at any point after this, press the EJECT switch (22), and the
wafer will be ejected into the wafer tray.

Wafer to Mask Alignment

1. The optical head should still be in the raised position. If it is not, press the VISUAL ALIGN
SWITCH (21) (also labeled HEAD LIFT).. The optical head will rise to allow a complete view of
the mask and wafer.
The system must be in "separation" mode (SEPARATION switch (4) should be illuminated)
before any adjustments can be made; otherwise, damage to the wafer and mask will occur!

2. Visual Alignment: The first masking operation needs no particular alignment since there is no
pattern on the wafer with which to align, but it will help later on if you use the following procedures
to reasonably center the test area. It's also nice to have the rows of devices parallel to the wafer
flat. If you do have a patterned wafer, use the translation and rotation adjustments to get fairly
close to proper alignment of the test areas on the mask and wafer without spending much time.
 G.8
ECE344 Lab Manual
Appendix G

Rotational Adjustment

Turn the Rotation Adjustment (10) knob until satisfied with the angular relationship between mask
and wafer. For fine adjustment, it may be necessary to slightly overshoot in coarse mode. It will
then be in the fine adjust mode when you back up.
17A: For coarse alignment, unscrew the Coarse Rotation Lock (15) and pull the knob to the right
or push it to the left to rotate the assembly to the right or left. Tighten the Coarse Rotation Lock
(15) when finished with coarse alignment.

Rotate the Rotation Adjustment (10) for a fine alignment. There is no lock associated with the fine
rotation alignment.

X-Y Adjustment

To do a coarse alignment, press the Aligning Selector button (17) on the Aligning Disc (16) on
your right and move the Aligning Disc.

For fine adjustments, release the Aligning Selector button (17) and move the Aligning Disc.
1. After visually aligning the wafer, the microscope will be used to complete the alignment so
don't waste too much time striving for perfection on this step.
2. Press the VISUAL ALIGN switch (2) to lower the microscope.
3. If this is the first exposure, there is nothing further to align. Just center the centroid four point
and hot point probe test areas, roughly align the rows of devices with the flat and continue on to
step 11.
4. Select the ROW AND COLUMN microscope by turning the turret in the optical head until the
proper legend appears in the opening in the optical housing.
5. Roughly align the wafer and mask using the same controls as in the visual alignment. If the wafer
already has a pattern on it, check that the mask is properly oriented (i.e., not rotated 180 degrees)
and that the test patterns are aligned.
6. To look at several locations on the wafer, use the Scanning Disc (8) on the left to move the entire
stage (mask and wafer). Pressing the Scanning Disc Lock (7) button will allow the disk to be
moved. When the button is released, the disc will lock in place.
It is quite sufficient to continue after a portion of the proper alignment crosses on the wafer are
visible through their corresponding crosses on a darkfield mask in two device cells on either side
of the test area. Lightfield masks are even more forgiving.
Don't spend too much time on this step.
7. Use the Scanning Disc to move the entire stage so that the center of the wafer is in the center of
the field of view for the ROW AND COLUMN microscope. This insures that you will see wafer
beneath both microscope objectives after the next step.
8. Rotate the turret to SPLITFIELD LOW POWER. Use the Scanning Disc to locate alignment
crosses into both fields. Familiarity with the mask set will greatly enhance your navigation.
9. Align the mask using the fine adjustments described in step 2.
10. Once proper alignment is attained, press the CONTACT switch (5) to bring the wafer into contact
with the mask. The CONTACT switch should become illuminated. If the wafer is not aligned,
 G.9
ECE344 Lab Manual
Appendix G
press the SEPARATION switch (4) to separate the wafer from the mask and repeat the alignment
procedure.
11. If you are curious, you may wish to return to row and column microscope mode and look at the
device areas by slowly moving the left (scanning) disc.
Remember: When in CONTACT, do NOT move the aligning disc. It is safe, however, to
slowly move the scanning disc at any time.

Exposure

1. Slowly center the Scanning Disc (left paddle) within the circular plate on which it rests. The U.V.
light intensity and uniformity were optimized for this position. It's typically 20% less intense at the
edges of a wafer. It's possible to compensate for this somewhat during development by spraying
near the edges.
2. Kasper 17A only: Place a piece of filter paper in the wafer eject tray to catch the wafer when it is
automatically ejected after exposure.
3. Set the proper exposure time on the Timer (6). The average intensity should be posted near or on
the aligner and a dose in mW- sec/cm2 is called for in the "recipe". Calculate the time required
(hint: make the units work.)
3.1. If no dose is given in the recipe, then use 125mW-sec/cm2 for AZ 5214 PR and AZ 327
developer. (80mW-sec/cm2 will do fine with AZ 5214 PR and AZ 312 developer).
3.2. If no dose is given or the intensity is unkown, then use 20 seconds for a Kasper 2001 and 60
seconds for a 17A.
4. With the system in the CONTACT mode (CONTACT switch (5) should be illuminated), rotate the
turret in the optical head to EXPOSE.
Please notify everyone in the vicinity that you are about to expose your wafer so they can
avert their eyes and protect any undeveloped PR. Do not let the reflected UV light hit your
eyes - even from the side! Treat the light as if it were from arc-welding. Please check to
make sure the PR syringe is covered too.
5. Press the MANUAL EXPOSE switch (2).
6. Observe the U.V. light through the welding gogles provided near the aligners. Notify the instructor
if, for some reason, the U.V. light does not shine onto the mask/wafer area. Occasionally the
turret will not be in the proper position to trip an interlock switch. After the exposure, the wafer will
be ejected automatically.
7. After exposure, rotate the turret back to the ROW AND COLUMN microscope mode.
 G.10
ECE344 Lab Manual
Appendix G

Mask Unloading

If the aligner will not be used for a while or if a change of masks is needed, remove the mask as
follows:
NOTE: Do not turn off the vacuum or power if the mask is in the aligner. If either is turned
off, the mask will drop and may be scratched.
1. Press the VISUAL ALIGN switch (21) (also labeled HEAD LIFT).
2. Press the MASK LOAD switch (19).
3. Open the mask holder against the stop.
4. Remove the mask touching it only by the edges and place it back in the mask box.
5. Lower the mask holder to the closed position.
6. Again press the MASK LOAD switch (19).
7. Press the VISUAL ALIGN switch (21) (also labeled HEAD LIFT) to lower the optical head.
8. If nobody is going to use the aligner next, please turn the POWER SWITCH (18) off.

The U.V. lamp should only be turned off at the end of the day. The lamp's lifetime is a
strong function of how many times it's ignited.
 Appendix H
Ultratech 1000WF Stepper

The Ultratech 1000 Wide Field steppers are the latest addition to lithography in the ECE344 lab.
They are highly automated, extremely complex machines which will supplement the manual contact
aligners. There actually was a reluctance to install these machines due to their cost and the removal of
operator involvement with aligning.

The 1000WF is still in use by major semiconductor fabs (such as the former AC Delco) and were
in use by Intel until December of 1996. There are enough left to support third party parts suppliers and
reconditioners. They are ideal for today’s non-critical, lower resolution lithography steps, and have the
ability to mix-and-match with other steppers.

The steppers present in the lab have been modified by Intel, and their performance has been
enhanced from stock machines. Positioning resolution has been increased (closer alignment), and the
optics have been enhanced (possible to achieve submicron resolution).

System Information

The operation of the steppers is very exact (presently I have approximately 4 manuals, 14 hours
of setup video, and 15 VHS videos covering operation and maintenance). Therefore a short overview is
all that will be presented.

Positioning System

To provide for accurate positioning, the 1000WF consists of two stepper motors with feedback
from a Zeeman split HeNe laser interferometer. Laser interferometers work through the counting of
interference fringes created as a laser beam is reflected back onto itself. As the stage moves, the
distance the laser traverses changes, and the phase of the beam upon reflection changes, resulting in a
maxima and minima of brightness as the beam destructively and constructively interferes with itself. Each
fringe signifies a specific distance based on the operating wavelength of the laser. As the fringes move, a
counter determines the number which pass through an aperture, and can correlate that with a specific
distance. This distance is used to provide an absolute position of the mirrors mounted on the stage with
respect to a home position. The home position is determined by a limit switch.

By implementing two mirrors and splitting the laser beam, a very accurate position of the stage
can be determined for both the X and Y-axes.

The interferometric determination of stage position is used to drive two stepper motors for stage
placement. The stepper motors drive pinch rollers which propel the air bearing supported stage along
guide rods.
 H.2
ECE344 Lab Manual
Appendix H

Exposure System
The 1000WF consists of a very simple but effective 1:1 image projection system. A mercury arc
lamp is used for the UV source utilizing the g- and h-lines. The beam is projected through a light pipe, an
actinic filter (filters out the UV components for alignment), through a reticle (mask), is redirected by a
prism through a lens doublet, reflected back by a mirror, back through the doublet, and finally through
another prism to the wafer. See Figure H1.

Hg lamp PMT
Actinic
shutter
Light pipe Y-tilt mirror

Doublet Mirror

Dark field
image
Prism

Wafer

Figure H1. 1000WF light system.

The PMT and Y-tilt mirror are used for pattern recognition and alignment using the darkfield image
from the wafer.

Registration

One of the most important aspects of lithography is registration. The 1000WF determines
position of the mask in relation to the existing wafer pattern both mechanically and optically in a multistage
process.

The first mask of the process exposes the pattern onto the wafer in a blind step mode. Blind
stepping is a purely mechanical alignment, and relies on the interferometer for placement of the individual
die. This first mask level contains several alignment targets which will be used by subsequent mask
levels.
 H.3
ECE344 Lab Manual
Appendix H

There are four types of mechanical alignment used in the 1000WF

Flat find

• used for rough theta adjustment

Bash routine

• used to center the wafer on the chuck

Wafer edge detection

• used to center the wafer under the optics

Reticle guides

• used to locate the reticle in the y-axis

• must be <75µm misalignment - there is no y-axis adjustment

There are three types of targets/keys used in the 1000WF:

Reticle alignment fiducial

• used for absolute positioning of the mask to the optical system

Reticle

Reticle Fiducials

Optical alignment target (OAT)

• large target used for global positioning of the wafer in relation to the mask pattern
• aligns wafer to reticle to within 10µm

4µm wide cross hair

4000µm
 H.4
ECE344 Lab Manual
Appendix H

Horizontal Alignment Marks (HAMs)

• used for fine alignment and theta (rotational) adjustment

• aligns wafer to reticle to within <1µm

HAMS

OAT
Reticle Field

The Reticle
Contact aligners use a mask which covers the entire area to be exposed (Figure H2). This
method of exposure has several disadvantages as they become larger:

• large masks are cumbersome and are more prone to breakage

• difficult to clean
• larger area for particles to land, causing pattern defects

MASK WAFER

Figure H2. Contact aligner mask.

A stepper, on the other hand, utilizes a field instead of the entire mask pattern. The field is a
subset of the desired image to be transferred to the wafer. This field is stepped and repeated over the
wafer. Below is a diagram of the reticle (with 3 fields) used in the 1000WF:

RETICLE WAFER

Figure H3. Stepper reticle.

 H.5
ECE344 Lab Manual
Appendix H

The advantages of the reticle are:

• smaller, therefore easier to handle

• less area for particles to cause defects
• same image for every device on the wafer (can be a disadvantage)
• versatile - image pattern can be changed through software
• allows for drop-ins (test patterns, different devices) which can be temporary

Although there are several advantages to the reticle, there are also disadvantages:

• same image for every device on the wafer (propagation of faults)

• mechanical alignment of guide structures critical
• registration targets/keys critical
• more expensive (labor intensive)

Reticle Layout
A complete reticle is more complex than a contact mask. Below is a diagram of the features
explained above:

Reticle
Fiducial Field 2
HAM

OAT Field 1 Field 3

Reticle
Guide
 H.6
ECE344 Lab Manual
Appendix H

Operation
Although the steppers are complex to set up, they are very easy to run. The stepper will be
warmed up prior to class.

Load the Reticle

The reticle contains three fields, each corresponding to a mask level (see Figure H4.). This
requires the use of two reticles to obtain the entire mask set.

Reticle 1 Reticle 2

Mask 1 Mask 2 Mask 3 Mask 4 Mask 5

Figure H4. Mask locations.

The mask used is determined by the reticle data loaded into the stepper. The mask data is an
array of data that contains all the physical characteristics of the stepper, reticle, fields, and wafer.

The reticle must not be changed by students! If you require the use of a reticle not in the
stepper, contact your TA.

You will have to change reticle data to align and expose with the correct mask level.

Load Reticle Data

1. Press <K1> (Load/Unload Reticle)
1.1. If a Reticle is loaded, proceed to 1.2. If the reticle is not loaded, proceed to 1.3.
1.2. If a reticle is loaded, it will ask “Unload the reticle?”
1.2.1. press <y> (yes)
1.2.2. The reticle will unload.
1.2.3. After unloading, make sure that the reticle is seated properly in its guides by
pushing it gently to the right and tilting the left side up about ¼” and gently letting
it back down.
1.2.4. Press <K1> when the stepper returns to the main menu and proceed to 1.3.
1.3. If there is no reticle loaded, the stepper will ask “Load reticle data?”
1.3.1. Make sure that the reticle is seated properly in its guides by pushing it gently to
the right and tilting the left side up about ¼” and gently letting it back down.
1.3.2. Insert the reticle data disk
 H.7
ECE344 Lab Manual
Appendix H
1.3.3. press <y> (yes)
1.3.4. The stepper will ask “Input reticle data file name”
1.3.5. Type in the mask level name:

Step Mask level name

PR1 - layer1
PR2 - layer2
PR3 - layer3
PR4 - layer4
PR5 - layer5

1.3.6. press <ENTER>: the HP200 will load the data into memory
1.4. The stepper will ask “Load reticle?”
1.4.1. Place the frosty wafer (the unpolished side of an unused wafer) into the
autoloader.
1.4.2. press <y> (yes)
1.4.3. The reticle will go through a series of tests to line it up properly with the optics. If
it should fail reticle load, contact the TA.
1.4.4. Remove the frosty wafer from the autoloader after successful loading of the
reticle.

Align and Expose Wafer

1. After successful completion of reticle load, the HP200 will bring up the run mode screen.
Run mode determines the method of alignment and exposure.
1.1.1. For layer1, proceed to 1.1.2. For all other layers, proceed to 1.1.3.
1.1.2. For layer1, the stepper will perform a blind step. Blind stepping is the mechanical
alignment of the reticle to the wafer using only the interferometer as a means of
registration.
1.1.2.1. press <1> (run mode 1 - mechanically align and expose)
1.1.2.2. The stepper will ask “Input exposure intensity”
2
1.1.2.3. type in <150> (150mJ/cm )
1.1.2.4. press <ENTER>
1.1.2.5. The stepper will ask “Exposure is 150. Ok?”
1.1.2.6. type <y> (yes)
1.1.2.7. The stepper will say “waiting to load wafer”
1.1.2.8. Load your wafer into the autoloader by placing it with tweezers into the
left side of the autoloader. Place the wafer so that it rests both on the red
circle and the drive belts.
H.8
ECE344 Lab Manual
Appendix H
1.1.2.9. The wafer will automatically load onto the chuck after the flat find routine,
and will be aligned and exposed automatically.
1.1.2.10.After successful alignment and exposure, the wafer will be returned on
the right side of the autoloader. Remove it and place it back into your
wafer container with tweezers.
1.1.2.11.The stepper will say, “waiting to load wafer.” If there are others waiting
to expose the same mask, they may continue without reloading the
reticle.
1.1.3. For all layers other than layer1, the stepper will align wafer targets through
reticle keys optically.
1.1.3.1. press <2> (align and expose)
1.1.3.2. The stepper will ask “Input exposure intensity”
2
1.1.3.3. type in <150> (150mJ/cm )
1.1.3.4. press <ENTER>
1.1.3.5. The stepper will ask “Exposure is 150. Ok?”
1.1.3.6. type <y> (yes)
1.1.3.7. The stepper will say “waiting to load wafer”
1.1.3.8. Load your wafer into the autoloader by placing it with tweezers into the
left side of the autoloader. Place the wafer so that it rests both on the red
circle and the drive belts.
1.1.3.9. The wafer will automatically load onto the chuck after the flat find routine,
and will be aligned and exposed automatically.
1.1.3.10.After successful alignment and exposure, the wafer will be returned on
the right side of the autoloader. Remove it and place it back into your
wafer container with tweezers.
1.1.3.11.The stepper will say, “waiting to load wafer.” If there are others waiting
to expose the same mask, they may continue without reloading the
reticle.
 Appendix I
The Mask Set
The mask set currently used by ECE344 was the subject of a master’s thesis during the 1990-91
school year by Kevin Tsurutome and modified by Ron Stack in the summer of 1994. The present revision
occurred in the spring of 1998 by Dane Sievers to reflect the changes necessary to utilize it with the
steppers. Most of the information about the mask set can be found on the web pages for ECE344. Only
essential information about how to use the test areas and some transparencies of some of the devices are
included in the printed version of the manual..

Figure 1. Composite Layout of ECE344 Device Cell

I.2
ECE344 Lab Manual
Appendix I
 I.3
ECE344 Lab Manual
Appendix I
Using your test squares
Refer to the TEST SQUARES transparencies immediately following this section.

*Note: this is intended as a brief reference for your convenience and in no way replaces a
thorough understanding of the material elsewhere in the lab manual.

The test area on your wafer serves three useful functions:

• Process characterization
• A check for complete etching
• Aid in alignment for the contact aligners

Process Characterization

This consists of checking the initial conductivity of your wafer all the way through checking the
final sheet resistance of your diffused n and p type regions. This characterization is important for
many reasons but mainly it is to let you know that your processing is proceeding within defined limits.
It can also alert the instructor to potential problems with equipment, i.e. a contaminated furnace. This
allows immediate rectification of a problem without major setbacks to your or other students.

Here is a list of the process measurements you will be making in the order in which they are
made:

1. Initial bulk resistivity and raw V/I ratio using for point probe (FPP)
- use the FPP test area 1
2. Rough boron sheet resistance after boron predep using FPP.
- use the FPP test area 1
3. Boron sheet resistance after borosilicate glass removal using FPP.
- use the FPP test area 1
4. Boron sheet resistance after boron drive (an PR2) using FPP.
- use the FPP test area 1
5. Phosphorus sheet resistance after phosphorus predep using FPP.
- use the FPP test area 2
6. Phosphorus sheet resistance after phosphosilicate glass removal using FPP.
- use the FPP test area 2
7. Phosphorus and boron sheet resistance after PR4 using FPP.
- use the FPP test area 1 for boron and FPP test area 2 for phosphorus

The hot point probe is used in a process context in that it gives an accurate indication of
whether your wafer is n-type or p-type: this is a more reliable indication than the four point probe. The
hot point probe is used after PR sessions 1 through 4 for checking that the oxide has been completely
etched.
 I.4
ECE344 Lab Manual
Appendix I

A check for complete etching

Etching the oxide after a PR step is an essential part in completing the pattern transfer to the
wafer. Thus it is important that it is complete with no remaining oxide in the open windows. An easy
way to check this is with the hot point probe (HPP). The test area has regions set aside just for this
purpose. After each PR operation a new window in the test area is open so that it can be probed with
the HPP. This measurement gives an accurate reading (in the nA range) , with its polarity indicating
the type material.

If no current or an unstable current reading appears you should return the wafer to the
oxide etch (refer to the Processing Recipe).
 Appendix J
The Test Stations

The purpose of a prober is to make electrical connections from the micro-world of the wafer to the
macro-world we live in. The typical probe pad on the ECE344 mask set is 100µm on side, which would be
quite difficult to solder or otherwise make connections by eye. This is not easy considering that solder
does not wet aluminum, requiring a second metallization using a different metal.

Making contact to the wafer is therefore left to the micromanipulators with very fine tungsten
probe tips. The wafer is also magnified with a stereo microscope. Be careful with the probers! They are
precise instruments, as the cost proves it.

Do not

• lower the probes onto the wafer with too much force (this will curl or ‘fish hook’ the sharp points)
• overextend the micromanipulators (they will bind)
• lower the probe stage with the probes down (a good way to ‘fish hook’ the tips)
• open the chuck vacuum without a wafer (causes excessive blow-by on the house vacuum)
• move the micromanipulators (they have been setup for ease in probing)
• change the SMU leads to the probes
• leave the probe stage down when not in use

Use of the probes

1. Place your wafer on the wafer chuck

2. Turn on the chuck vacuum switch.
3. Raise each of the probes a couple of turns with their UP positioner.
4. Lower the probe stage slowly with the lever on the left hand side.
4.1. If any of the probe tips look like they will touch the wafer before the stage is completely
down, raise the tips and continue lowering the stage.
4.2. Repeat until the stage is fully lowered with none of the probes touching the wafer.
5. Turn on the microscope light
6. Move the first device to be tested to the center of the microscope field of view using the stage’s X
and Y controls (located at the front of the stage).
7. Carefully make contact to the device pads with the probes using the X, Y, and Z controls of the
micromanipulator - DO NOT MOVE THE PROBE BODIES!
 J.2
ECE344 Lab Manual
Appendix J

Electrical connectors

Probes 1, 2, 3, and 4 are connected to the first three switches on the side panel of the probe
station’s cover. These switches determine which connector will be connected to the probe tip:

• UP - HP parameter analyzer
• DOWN - HP LCR meter

Probe 4 also has provisions for a jumper so that the chuck may be connected to the SMU cables.
Please check to make sure that the jumper is connected to the appropriate contact device!

The most common mistake when testing devices is having the wrong instrument connected to
your probe. I-V measurements are performed by the Parameter Analyzer (switch UP), C-V
measurements are performed by the LCR Meter (switch DOWN).

Probing multiple devices

When probing several similar devices, the probe stage can be raised, allowing the next device to
be positioned, and then carefully lowering the stage to make contact with the new device.
 References

Electronics Materials Science: For Integrated Circuits in Si and GaAs, James W. Mayer, and S.S.
Lau, MacMillan Publishing Co., 1990

Semiconductor Integrated Circuit Processing Technology, W.R. Runyan, and K.E. Bean, Addison-
Wesley Publishing Co., 1990

Electronic Materials - Science and Technology, Shyam P. Murarka, and Martin C. Peckerar,
Academic Press, 1989

Introduction to Microelectronic Devices, David L. Pulfrey, and N. Garry Tarr, Prentice-Hall, 1989

Microelectronic Materials, C.R.M. Grovenor, Adam Hilger, Bristol and Philadelphia, 1989

Semiconductor Physics, Mauro Zambuto, McGraw-Hill, 1989

Introduction to Microelectronic Fabrication, Vol. V, Richard C. Jaeger, Addison-Wesley

Publishing Company, 1988

Introduction to Integrated Circuit Engineering, D.K. Reinhard, Houghton Mifflin, 1987

Microelectronic Processing - An Introduction to the Manufacture of Integrated Circuits, W. Scot

Ruska, McGraw-Hill, 1987

Silicon Processing for the VLSI Era, Vol. 1, Process Technology, S. Wolf, and R.N. Tauber, Lattice
Press, 1986

Semiconductor Devices - Physics and Technology, S.M. Sze, John Wiley and Sons, Inc., 1985

Modern MOS Technology - Processes, Devices, and Design, DeWitt G. Ong, McGraw-Hill, 1984

VLSI Fabrication Principles - Silicon and Galium Arsenide, Sorab K. Ghandhi, John Wiley and
Sons, Inc., 1980

VLSI Technology, S.M. Sze, McGraw Hill, 1983

Microelecronics Processing and Device Design, Roy A. Colclaser, John Wiley and Sons, Inc., 1980

Integrated Circuits Technology and Applications, F.F. Mazda, Cambridge University Press, 1978

Device Electronics for Integrated Circuits, 2nd Edition, Richard S. Muller, and Theodore I. Kamins,
John Wiley and Sons, Inc., 1977

Integrated Circuit Engineering - Design, Fabrication, and Applications, Arthur B. Glaser, and
Gerald E. Subak-Sharpe, Addison-Wesley Publishing Co., 1977

The Theory and Practice of Microelectronics, Sorab K. Ghandhi, John Wiley and Sons, Inc., 1968

Physics and Technology of Semiconductor Devices, A.S. Grove, John Wiley and Sons, Inc., 1967
Four Point Probe Area 2 for:
boron drive sheet resistance
phosphorus predep sheet resistance
final phosporus sheet resistance
Four Point Probe Area 1 for: Hot Point Probe area for Hot Point Probe area for
bulk resistivity &V/I ration oxide etch completeness PR3 oxide etch completeness PR 1
boron predep sheet resistance
final boron sheet resistance
Hot Point Probe area for Hot Point Probe area for
oxide etch completeness PR4 oxide etch completeness PR2
5
Four Point Probe Area 2 for:
boron drive sheet resistance
phosphorus predep sheet resistance
final phosporus sheet resistance
Four Point Probe Area 1 for:
bulk resistivity &V/I ration
boron predep sheet resistance
final boron sheet resistance
Hot Point Probe area for Hot Point Probe area for
oxide etch completeness PR3 oxide etch completeness PR 1
Hot Point Probe area for Hot Point Probe area for
oxide etch completeness PR4 oxide etch completeness PR2

4
Four Point Probe Area 2 for:
boron drive sheet resistance
phosphorus predep sheet resistance
final phosporus sheet resistance
3
Four Point Probe Area 1 for:
bulk resistivity &V/I ration
boron predep sheet resistance
final boron sheet resistance
Hot Point Probe area for Hot Point Probe area for
oxide etch completeness PR3 oxide etch completeness PR 1
Hot Point Probe area for
oxide etch completeness PR2
Four Point Probe Area 2 for:
boron drive sheet resistance
phosphorus predep sheet resistance
final phosporus sheet resistance
2
Four Point Probe Area 1 for:
bulk resistivity &V/I ration
boron predep sheet resistance
final boron sheet resistance
Hot Point Probe area for
oxide etch completeness PR 1
Hot Point Probe area for
oxide etch completeness PR2
Four Point Probe Area 2 for: Four Point Probe Area 1 for: Hot Point Probe area for
boron drive sheet resistance bulk resistivity &V/I ration oxide etch completeness PR 1
phosphorus predep sheet resistance boron predep sheet resistance
final phosporus sheet resistance final boron sheet resistance