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PRACTICAL: 12
3.0 INTRODUCTION
A basic NAND Gate SR flip flop circuit provides feedback from its outputs to its
inputs and is commonly used in memory circuits to store data bits.
The term "Flip-flop" relates to the actual operation of the device, as it can be
"Flipped" into one logic state or "Flopped" back into another.
The simplest way to make any basic one-bit Set/Reset SR flip-flop is to connect
together a pair of cross-coupled 2-input NAND Gates to form a Set-Reset
Bistable or a SR NAND Gate Latch, so that there is feedback from each output to
one of the other NAND Gate inputs.
48 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))
DIGITAL ELECTRONICS (331102)
This device consists of two inputs, one called the Reset, R and the other called
the Set, S with two corresponding outputs Q and its inverse or complement Q as
shown below.
This device consists of two inputs, one called the Reset, R and the other called
the Set, S with two corresponding outputs Q and its inverse or complement Q as
shown below.
Same circuit can be design using NOR gate. Its logic diagram and the excitation
diagram can be as shown :
S – R Flip Flop
using NOR gate
49 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))
DIGITAL ELECTRONICS (331102)
By connecting a 2-input NAND gate in series with each input terminal of the SR
Flip-flop a Gated SR Flip-flop can be created.
This extra conditional input is called an "Enable" input and is given the prefix of
"EN" as shown below.
When the enable input "EN" changes to logic level "1" the circuit responds as a
normal SR bistable flip-flop with the two AND gates becoming transparent to the
Set and Reset signals.
This enable input can also be connected to a clock timing signal adding clock
synchronisation to the flip-flop creating what is sometimes called a "Clocked SR
Flip-flop".
o Setup Time: Minimum time period during which data must be stable
before the clock makes a valid transition. For example, for a positive edge
triggered flip-flop, with a setup time of 2 ns, Input Data (i.e. R and S in
the case of RS flip-flop) should be stable for at least 2 ns before clock
makes transition from 0 to 1.
o Hold Time: Minimum time period during which data must be stable after
the clock has made a valid transition. For example, for a positive edge
triggered flip-flop, with a hold time of 1 ns. Input Data (i.e. R and S in the
case of RS flip-flop) should be stable for at least 1 ns after clock has made
transition from 0 to 1.
50 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))
DIGITAL ELECTRONICS (331102)
7.0 EXERCISE :
Ans :
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8.0 ASSIGNMENT :
51 | P a g e
SOHIL VOHRA (LECTURER - SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT))