Академический Документы
Профессиональный Документы
Культура Документы
! Introduction
! Inductive Fault Analysis
! Faults That Can Be Detected
! Circuit Constrains
! Design and Test Rules
! ATPG for IDDQ Testing
! Current Monitoring Methods
! Built-in Current Sensors
! QTAG Standard
! Deep Sub-micron Issues
! Some Specific Examples
! Conclusions
IDDQ testing.1
IDDQ Testing
IDD --- Current flow through VDD
Q --- Quiescent state
IDDQ Testing --- Detecting faults by monitoring IDDQ
VDD
IDD
Inputs
CMOS
circuit
Outputs
IDDQ testing.3
IDDQ testing.4
Technology
Analysis
Primitive Fault
Taxonomy
Circuit
Layout
Layout
Parsing
Layout Data
Structures
Defect
Statistics
Defect
Generation
Defects
Primitive Fault
Extraction
Primitive
Fault List
Circuit Fault
Translation
Ranked Circuit
Fault List
IDDQ testing.5
Extra conductance
Missing insulator
Results of IFA
D efect Type
Fault
pin- m iss. extra m iss. extra m iss. extra m iss. extra m iss. all % of
C ategories holes m etal m etal poly. poly. diff. diff. p-w el p-w el cont. def. fault
l
l
s
B ridges
42
61
52
8
31
35
229 48%
B reaks
82
78
1
10
9
180 38%
C om bin.
1
1
0.2%
N ew T
2
.1
2
0.4%
T-S O N
62
62
13%
T-S O P
0.5
.05
0%
E xcept.
1
1
0.2%
(5,5,4)C ounter
D efect Type
Fault
pin- m iss. extra m iss. extra m iss. extra m iss. extra m iss. all % of
C ategories holes m etal m etal poly. poly. diff. diff. p-w el p-w el cont. def. fault
l
l
s
B ridges
111
257
125
12
62
78
645 48%
B reaks
281
230
4
21
29
565 42%
C om bin.
134
134 10%
N ew T
3
.3
0.2%
T-S O N
3
<1
3
0.2%
T-S O P
<1
<1
0%
E xcept.
2
2
0.2%
4 x 4 M ultiplier
New Transistors
diffusion
IDDQ testing.10
0
logic
logic
0: 0V
1: 5V
2.5V
1
0 or 1?
5V
Induce large
current
IDDQ testing.12
Cdg
C1
Cgd
D
Cjd
C4
Cjs
Cgs
S
C3
Csg
C2
Csg0
Cgb
Cgb
S
S
IDDQ testing.13
D
B
C1
d2
C3
C4
In a gate
C2
large IDDQ
OV
Cgb
S
IDDQ testing.14
B
d3
C3
C3
C4
C4
d1
C2
C2
Cgb
In a gate
C1
Cgb
May drift to
intermediate
voltage
IDDQ testing.15
Stuck-open Faults
A B C D O
A
B
T1 = 1 1 1 1 0
T2 = 0 0 0 1 ?
O
A
B
D
IDDQ testing.16
IDDQ testing.17
Circuit Constraints
IDDQ testing.18
x=11?
z=x0?
large
current
Sel=0 if AB=10
Output
1
MUX
0
To detect (x,y)
A
w
B
z
O
C
x
Inputs
Transistor Group
Output
G3
G2
B
G1
C
E
IDDQ testing.24
IDDQ testing.26
Fault Simulation
1. Fault models --- Bridging, break, stuck-open,
stuck-at ?
2. Fault list generation --- need inductive fault
analysis
3. Fault coverage ?
4. Easy for bridging and stuck-on faults
5. Difficult for break and stuck-open faults
6. Stuck-at faults may or may not be modeled as
short to VDD or GND
IDDQ testing.27
IDDQ testing.28
Test Generation
1. Conventional test generation for stuck-at faults
can be modified to detect BFs.
2. No fault propagation.
3. Must make sure the faults result in a conducting
path between VDD and GND.
Switch level test generation may be necessary.
4. Break and stuck-open faults are difficult to detect.
IDDQ testing.29
No Fault propagation.
IDDQ testing.30
#faults
Logic Testing
99.96
c499
99.37
99.62
c1908
99.32
s386
350
93.1 96.78
s526
s832
Time(m)
4.04
50
79
11.4
99.73
9.15
184
87
30.5
99.59
99.75
21.4
138 84.8
28.6
98.00
98.74
99.07
7.51
288
75
28.6
98.15
98.63
98.95
11.9
192 18.8
56.1
97.23
98.15
98.54
18.8
967 75.7
3.08
IDDQ testing.32
Not Covered
c432
432
22
18
0.24
4.2
c499
546
82
0.57
c880
934
14
0.39
c1355
1482
83
5.4
0.2
c1908
1604
104
3.89
0.1
c2670
2253
23
17
4.59
1.2
c3540
3314
35
50
44.32
1.7
c5315
4955
24
6.13
0.1
c7552
6956
32
20
14.27
0.3
Average
2497
46
12
8.87
0.8
IDDQ testing.33
ATE
Current Supply
Monitor
BICS
DUT
DUT
CUT
External
monitoring
Test
Fixture
Built-In
Current Sensor
IDDQ testing.34
S (STROBE)
VDD
VDD pin
N
IDD
CN
DUT
Problems:
VSS pin
BICS
Pass
/Fail
Inputs
CUT
Outputs
OR
Inputs
CUT
Outputs
Test
BICS
Pass /Fail
IDDQ testing.36
CMOS
Pass/Fail
Flag
Module
VR
1
1
VR
+ -
CMOS
Module
V
Virtual
Ground
Switching
circuit
GND
VDD-GND Shorts
Shorts causing
struck-at faults
Shorts causing
bridging faults & oxide pinholes
Junction
leakages
NO defect
NO
defect
VR
Defect
IDDQ testing.37
VDD
Pullup
VDD
Pullup
inputs
Pullup
Normal : t = 1
Test
:t=0
tout = 1 if no fault
= 0 if fault exists
...
Pulldown
Pulldown
Pulldown
...
MT
MT
Gnd
MT
...
MTD
Gnd
tout
MTD
MTD
Gnd
IDDQ testing.38
Pullup
VDD
VDD
Pullup
inputs
Pullup
...
Pulldown
Pulldown
Pulldown
...
t
MT
tout
MTD
Gnd
IDDQ testing.39
Pullup
VDD
VDD
Pullup
inputs
Pullup
...
Pulldown
Pulldown
Pulldown
...
MT
tout
MTD
Gnd
IDDQ testing.40
TVDD
MP7
CMOS
Logic
Circuit
MP1
MP3
MP8
MP2
X
V
MN1
MN2
MP4
MN4
MN3
Y
MP5
MN4
Tout
MN8
MP6
MN6
Tmode
MN7
I
NGND
V-I Translator
GND
Level Translator
Integral Circuitry
SPC
Ts
T1
I2 A1 O1 M
+
IDD
I1
Io
CMP
VDD
Vref
In
CUT
O2
Iref
Vss
Virtual Short
Current Mirror
VDD' ~ VDD
IDD ~ I0
IDDQ testing.42
Virtual
Short
IRS
I+
I+
VoutIDD
VSS
Vin=3V
Vout+
VDD=3V
Threshold detector
CUT
Fault indication
Virtual short
VDD~Vin
Infinite input impedance of OP
I-=0 and IRS=IDD
IDDQ testing.43
V'DD=5V
Current Conveyor
Ix
VDD
Iy
Threshold
Detector
Fail/Pass
CUT
Virtual short
Current Conveying
VDD ~ VDD'
Iy ~ Ix
IDDQ testing.44
Disadvantages of BICS
Impact on circuit performance
Reliability of itself
Area overhead
Power consumption
IDDQ testing.46
QTAG Standard
Motivation :
ATE based IDDQ facilities are not flexible or
effective.
Circuit designers are reluctant to use BICS.
Goal : To provide a de-facto standard for IDDQ monitors
on test fixture for production test.
IDDQ testing.47
Partnership of QTAG
Semicoductor test department:
Users, must drive the standard
ATE Vendors:
must supply the software to operate the
monitors from ATE
Test Fixture Vendors:
must provide a small area close to CUT on all
test fixtures to mount the monitors.
Monitor Developers:
must supply the desired monitors.
IDDQ testing.48
ATE
VDD MON
Vref
VDD PSU
Ip
Bypass
Do
Di
IDDQ
MONITOR
VDD DUT
DUT
Vss
IDDQ testing.50
8
7
6
5
Power
QTAG Monitor
Power Ring
Control
Probe Nails
10 cm
IDDQ testing.51
VDD PSU
VDDmonitor
1 2
3
Threshold
Pass-Fail
On-Off
6
4
8
MONITOR
ATE
Sample
VDDdevice
DUT
PIN
VDDdevice
VDDpsu
VDDmonitor
VSS
Pass/fail
Sample
ON-OFF
V
s
s
Threshold
Function
to device under test
to power supply
to secondary power source for monitor
group pin
Logic output indicate result of sample
High-level: under threshold when last sampled
Low-level: above threshold when last sampled
Positive clock edge to indicate sampling point
On is the monitoring mode
OFF stops monitoring, but gives low Ohms pat
VDDpsu to VDDdevice
Sets threshold limit for P/F as input voltage lev
IDDQ testing.52
T8
T11
T9
T10
VREF
T2
T1
T3
T5 T6
+
A2
VSS
VDM
Iout
CUT
IDDQ testing.53
IREF
VDD_MON
KICK
VDD_PSU
12
BYPASS
VREF
Iref
Internal
Bypass
6
2
Output
Front
Back
10
DO
NC
11
100nF
VDD
VSS
IDDQ testing.54
VREF
+
-
p2
p1
op_1
+
-
p3
op_2
IREF
NIA
NIB
NIC
VSS
VDD_DUT
iddq/2
IDDQ testing.55
P2
P3
OP_3
aspass
iddq/2
N1
N7
N6
N2
N3
N8
+
-
N4
N5
VSS
IDDQ testing.56
Ericson
GEC
HP
Intel
ITT
LIRM
LTX
MCT
Megatest
Motorola
National Semicon.
NEC
Philips
Sandia Lab.
Schlumberger
Sequent
Siemens
Sun
Synopsys
Teradyne
TI
Vertex
IDDQ testing.57
Sub-threshold leakage
When VGS < VT, IDS =\ 0
IDDQ testing.58
Typically S=80
IDDQ testing.59
In deep-submicron region,
low voltage power supply
low threshold voltage
increased subthreshold current
Example:
IDS increase by
= times
5600
IDDQ testing.60
Technology solution
sharper sub-threshold
current slope
Ex:
IDDQ testing.62
!
!
!
IDDQ testing.63
VTCM
GTCM
V1
V2
V3
V4
V5
V6
V7
Vn-2
Vn-1
Vn
G1
G2
G3
G4
G5
G6
Gn-2
Gn-1
Gn
IDDQ testing.64
Defect Coverages(%)
Total
128
28.1 96.9
100
72.7
56
92.9
100
100
64.3
44
90.9
100
100
90.6
100
100
100
IDDQ testing.65
Conclusions
IDDQ testing.66