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UNIT I
THE 8085 MICROPROCESSOR
It is a 8 bit microprocessor.
It is manufactured with N-MOS technology.
It has 16 bit address bus
Can address upto 216 = 65536 bytes (64KB) memory locations through A0A15
The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0
AD7
Memory:
Program, data and stack memories occupy the same memory space. The total
addressable memory size is 64 KB.
Data memory - the processor always uses 16-bit addresses so that data can
be placed anywhere.
Stack memory is limited only by the size of memory.
Stack grows downward.
First 64 bytes in a zero memory page should be reserved for vectors used
by RST instructions.
D.Shiloah Elizabeth, DCSE/AU
8/5/2015
Signal Groups:
Address bus
A15-A8, AD7-AD0
Multiplexed address/data bus:
AD7-AD0
Control and status signals
ALE, RD, WR, IO/M, S1, S0
Power supply and clock frequency
VCC, VSS, X1, X2, CLK (OUT)
Externally initiated signals:
Input: TRAP, RST 7.5, RST 6.5, RST 5.5,
INTR, READY, HOLD
Output: INTA, HLDA
Reset: RESET IN, RESET OUT
Serial I/O ports:
SID, SOD
D.Shiloah Elizabeth, DCSE/AU
MOV C,A
Opcode: 4FH
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MOV C,A
Opcode: 4FH
D.Shiloah Elizabeth, DCSE/AU
At T1 ,
The high order 8 address bits (20H) are placed on the address lines
A8 A15 and the low order bits are placed on AD7AD0
The ALE signal goes high to indicate that AD0 AD8 are carrying
an address
The IO/M signal goes low to indicate a memory operation
At the beginning of the T2 cycle,
The low order 8 address bits are removed from AD7 AD0
The control unit sends the Read (RD) signal to the memory. The
signal remains low (active) for two clock periods to allow for slow
devices
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Demultiplexing
the bus AD7AD0
During T2 ,
Memory places the data from the memory location on the lines
AD7 AD0
During T3,
The RD signal is Disabled (goes high). This turns off the output Tristate buffers in the memory. That makes the AD7 AD0 lines go to
high impedence mode
During T4
The machine code or the byte is decoded by the instruction
decoder and the task is carried out based on the bit pattern
D.Shiloah Elizabeth, DCSE/AU
Schematic of
latching loworder address
bus
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14
D7
D6
D5
D4
D3
D2
Ac
D1
D0
CY
Flag Register
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16
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Hardware Model
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Programming Model
Instruction classification
One-byte instructions
Two-byte instructions
Three-byte instructions
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18
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Load accumulator
MOV Rd, Rs
MOV M, Rs
MOV Rd, M
MOV B,C
MOV B,M
MVI B, 57
MVI M, 57
LDA 4200H
LDAX B
21
LXI H, 2034
LHLD 2040
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22
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Arithmetic instructions
OUT 87
IN 82
ADI 45
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Arithmetic instructions
Add register pair to H and L
registers
DAD Reg. pair
DAD H
ACI 45
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Arithmetic instructions
Decimal adjust accumulator
DAA none
DAA
SUI 45
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Arithmetic instructions
Branching instructions
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Branching instructions
Unconditional subroutine call
Jump conditionally
Operand: 16-bit address
Opcode Description
Flag Status
JC
Jump on Carry
CY = 1
JNC
Jump on no Carry CY = 0
JP
Jump on positive
S=0
JM
Jump on minus
S=1
JZ
Jump on zero
Z=1
JNZ
Jump on no zero
Z=0
JPE
Jump on parity even P = 1
JPO
Jump on parity odd P = 0
Jump unconditionally
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Branching instructions
Call conditionally
Operand: 16-bit address
Opcode Description
Flag Status
CC
Call on Carry
CY = 1
CNC
Call on no Carry
CY = 0
CP
Call on positive
S=0
CM
Call on minus
S=1
CZ
Call on zero
Z=1
CNZ
Call on no zero
Z=0
CPE
Call on parity even P = 1
CPO
Call on parity odd P = 0
31
RET none
RET
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Branching instructions
Load program counter with HL
contents
PCHL none
PCHL
Restart
Interrupt Rst Addr
TRAP
0024H
these interrupts generate RST
RST 5.5 002CH instructions internally and
RST 6.5 0034H thus do not require any
RST 7.5 003CH external hardware.
Logical instructions
Restart
generally used in
conjunction
with
interrupts
and
inserted
using
external hardware.
can be used as
software instructions
in a program to
transfer
program
execution to one of
the eight locations.
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Logical instructions
34
Logical instructions
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Logical instructions
CONTROL INSTRUCTIONS
Complement accumulator
CMA none
CMA
Complement carry
CMC none
CMC
No operation
NOP none
Halt and enter wait state
HLT none
Disable interrupts
DI none
Enable interrupts
EI none
Set Carry
STC none
STC
37
RLC
D7
D6
D5
D4
D3
D2
D1
D0
CY
B7
B6
B5
B4
B3
B2
B1
B0
CY
D7
D6
D5
D4
D3
D2
D1
D0
B7
B6
B5
B4
B3
B2
B1
B0
B7
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RRC
D7
D6
D5
D4
D3
D2
D1
D0
CY
B7
B6
B5
B4
B3
B2
B1
B0
CY
D7
D6
D5
D4
D3
D2
D1
D0
CY
B0
B7
B6
B5
B4
B3
B2
B1
B0
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RAL
RAR
CY
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
CY
CY
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
CY
CY
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
CY
B7
B6
B5
B4
B3
B2
B1
B0
CY
CY
B7
B6
B5
B4
B3
B2
B1
B0
Each binary bit of the accumulator is rotated left by one position through
the Carry flag.
D7 is placed in CY, and CY is placed in D0.
CY is modified according to D7.
D.Shiloah Elizabeth, DCSE/AU
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The term addressing mode refers to the way in which the operand of
the instruction is specified.
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Timing Diagram
Timing diagram is the display of initiation of read/write and transfer of data
operations under the control of 3-status signals IO / M , S1, and S0.
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Operations
Opcode Fetch
Memory Read
Memory Write
I/O Read
I/O Write
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54
55
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58
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MVI A, 45H
STA 5000H
LHLD
SHLD
STA
STAX
LDA
LDAX
LXI
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Counters
Counters
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Counters
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LOOP
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LXI B, 1000H
DCX B
MOV A, C
ORA B
JNZ LOOP
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Delays
Delays
B be Number of Bytes
M be Number of Machine Cycles
T be Number of T-State.
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Delay loops
We can use a loop to produce a certain amount of time delay
in a program.
The following is an example of a delay loop:
MVI C, FFH
LOOP DCR C
JNZ LOOP
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In the last iteration of the loop, the JNZ instruction will fail and require only 7
T-States rather than the 10.
Therefore, we must deduct 3 T-States from the total delay to get an accurate
delay calculation.
To calculate the delay, we use the following formula:
Using these formulas, we can calculate the time delay for the previous
example:
TO= 7 T-States
Delay of the MVI instruction
Tdelay= TO+ TL
Tdelay= total delay
TO= delay outside the loop
TL= delay of the loop
TOis the sum of all delays outside the loop
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The following is an example of a delay loop set up with a register pair as the
loop counter.
LXI B, 1000H ;10 T-States
LOOP DCX B6
;T-States
MOV A, C
;4 T-States
ORA B ;4 T-States
JNZ LOOP
;10 T-States
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TO= 10 T-States
The delay for the LXI instruction
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The calculation remains the same except that it the formula must be
applied recursively to each loop.
Instead (or in conjunction with) Register Pairs, a nested loop structure can be
used to increase the total delay produced.
MVI B, 10H ;7 T-States
LOOP2 MVI C, FFH ;7 T-States
LOOP1 DCR C
;4 T-States
JNZ LOOP1
;10 T-States
DCR B
;4 T-States
JNZ LOOP2
;10 T-States
Start with the inner loop, then plug that delay in the calculation of the outer
loop.
TO1= 7 T-States
MVI C, FFH instruction
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The delay can be further increased by using register pairs for each of the loop
counters in the nested loops setup.
It can also be increased by adding dummy instructions (like NOP) in the body
of the loop.
TO2= 7 T-States
MVI B, 10H instruction
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Delay Subroutine
Delay Subroutine
The delay time is given by the total time taken to execute the delay
routine.
Eg. If the 8085 microprocessor has 5 MHz quartz crystal then, the
internal clock frequency = 5 /2 = 2.5 MHz
Solution:
use dedicated timer like 8253/8254 to produce time delays or
to maintain timings of various operations.
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Delay routine
MVI D, N
; N: count
Loop: DCR D
JNZ Loop
RET
Instruction
T-State required
for execution of
an instruction
Number of
times the
instruction is
executed
Total T-States
CALL addr16
18
18 x 1 = 18
MVI D, N
7x1=7
DCR D
4 x N = 4N
JNZ LOOP
10
N-1
10 x (N-1) = 10N
10
7x1=7
10
10 x 1 = 10
RET
83
14N + 32
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ALP for 8085 to count from AAH to 00H, with a time delay of 2ms for
each count. Assume the external frequency given to the processor is
2MHz.
Counters
Counters
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Counters
Delay Calculation
T D time delay in ms
Modulo-10 counter
START:
DISPLAY:
LOOP:
MOV A, B
LXI H, 16 BIT
Count
MVI B, 00H
OUT PORT1
DCX H
MOV A, L
ORA H
count
stored
in register
or register
pair
T D T O T L Count
JNZ LOOP
INR B
MOV A, B
T D T O T L Count
CPI 0AH
JNZ DISPLAY
JZ START
Count
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TD TO
TL
90
Stack
The stack is an area of memory identified by the programmer for
temporary storage of information.
The stack is a Last In First Out (LIFO) structure.
The stack normally grows backwards into memory.
the programmer defines the bottom of the stack and the stack grows up into
reducing address range.
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Stack
Stack
It is customary to place the bottom of the stack at the end of memory
to keep it as far away from user programs as possible.
In the 8085, the stack is defined by setting the SP (Stack Pointer)
register.
LXI SP, 6000H
This sets the Stack Pointer to location 6000H (end of memory for the 8085).
The Size of the stack is limited only by the available memory
Memory
Bottom of stack
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Stack - Operations
PUSH B
(1 Byte Instruction)
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34
Decrement SP
Copy the contents of register B to
the memory location pointed to by
SP
Decrement SP
Copy the contents of register C to
the memory location pointed to by
SP
PUSH and POP for storing information on the stack and retrieving it back.
Both PUSH and POP work with register pairs only.
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5FFC
5FFD
5FFE
34
5FFF
12
6000
SP (after Push)
SP (initially)
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Stack - Operations
12
34
5FFC
5FFD
5FFE
34
5FFF
12
6000
SP (initially)
The information is retrieved from the top of the stack and then the pointer is
incremented.
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Stack - Operations
Stack - Operations
The order of PUSHs and POPs must be opposite of each other in order
to retrieve information back into its original location.
The 8085 recognizes one additional register pair called the PSW
(Program Status Word).
PUSH B
PUSH D
...
POP D
POP B
This register pair is made up of the Accumulator and the Flags registers.
Reversing the order of the POP instructions will result in the exchange
of the contents of BC and DE.
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The result is that the contents of the Accumulator and the status of the Flags
are returned to what they were before the operations were executed.
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Stack - Operations
Stack - Operations
Decrement SP
Copy the contents of register A to the memory location pointed to by SP
Decrement SP
Copy the contents of Flag register to the memory location pointed to by SP
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Subroutines
AC
CY
LXI SP 5FFF
PUSH PSW
POP H
MOV A,L
ANI BFH (BFH= 1011 1111) ;Masking
MOV L,A
PUSH H
POP PSW
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Subroutines - Instructions
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Microprocessor
106
Reads the subroutine address from the next two memory location and stores
the higher order 8bit of the address in the W register and stores the lower
order 8bit of the address in the Z register
Pushes the address of the instruction immediately following the CALL onto
the stack [Return address]
Loads the program counter with the 16-bit address supplied with the CALL
instruction from WZ register.
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The CALL instruction places the return address at the two memory
locations immediately before where the Stack Pointer is pointing.
You must set the SP correctly BEFORE using the CALL instruction.
The RET instruction takes the contents of the two memory locations
at the top of the stack and uses these as the return address.
The data is stored in one of the registers by the calling program and the
subroutine uses the value from the register.
Do not modify the stack pointer in a subroutine. You will lose the return
address.
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Call by reference
110
If not, the RET statement will pick up the wrong information from the top of
the stack and the program will fail.
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