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Colour Television

Chassis

Q552.2E
LA

19100_000_110214.eps
110929

Contents
1.
2.
3.
4.
5.
6.
7.
8.
9.

Revision List
Technical Specs, Diversity, and Connections
Precautions, Notes, and Abbreviation List
Mechanical Instructions
Service Modes, Error Codes, and Fault Finding
Alignments
Circuit Descriptions
IC Data Sheets
Block Diagrams
Wiring diagram Berlinale 32"
Wiring diagram Berlinale 40" - 46"
Wiring diagram Blockbuster 37"
Wiring diagram Blockbuster 40" - 55"
Wiring diagram Sundance 32" - 37"
Wiring diagram Sundance 42" - 47" - 55"
Block Diagram Video
Block Diagram Audio
Block Diagram Control & Clock Signals
Block Diagram I2C
Supply Lines Overview
10. Circuit Diagrams and PWB Layouts
B01 313912364954
B02 313912364954
B03 313912364954
B04 313912364954
B05 313912364954
B06 313912364954
B07 313912364954
B08 313912364954
B09 313912364954
313912364954 SSB Layout
B01 393912364955
B02 393912364955
B03 393912364955
B04 393912364955
B05 393912364955
B06 393912364955
B07 393912364955
B08 393912364955

Page
2
2
11
15
44
64
73
79

93
93
96
97
100
101
102
103
104
105
106
Drawing

107
118
127
135
140
141
145
146
148
149
151
162
171
135
184
185
189
190

Contents

B09 393912364955
313912364955 SSB Layout
B01 313912365192
B02 313912365192
B03 313912365192
B04 313912365192
B05 313912365192
B06 313912365192
B07 313912365192
B08 313912365192
B09 313912365192
B10 313912365192
313912365192 SSB Layout
E 27221719026x IR/LED/Key Board
E 27221719027x IR/LED/Key Board
E 27221719028x IR/LED/Key Board
E 27221719029x IR/LED/Key Board
AL1 820400091254
AL3 820400091232
AL 310431364752 AmbiLight Layout
AL 310431364762 AmbiLight Layout
AL 310431364792 AmbiLight Layout
AL 310431364803 AmbiLight Layout
AL 310431364812 AmbiLight Layout
AL 310431365671 AmbiLight Layout
TS1 313912365252
11. Styling Sheets
Berlinale 32"
Berlinale 40" & 46"
Blockbuster 32"
Blockbuster 37"
Blockbuster 40" & 46"
Blockbuster 55"
Infinity 32"
Infinity 42"
Sundance 32" & 37"
Sundance 42", 47" & 55"

Page

192
193
195
206
215
223
228
229
233
234
236
237
238
287
288
289
291
296
302
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331

Copyright 2011 Koninklijke Philips Electronics N.V.


All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic, mechanical,
photocopying, or otherwise without the prior permission of Philips.

Published by MB/TY 1171 BU TV Consumer Care, the Netherlands

Subject to modification

EN 3122 785 19107


2011-Nov-04

EN 2

1.

Revision List

Q552.2E LA

1. Revision List

Manual xxxx xxx xxxx.0


First release.

Chapter 6: Added/changed alignment values; see section


6.3.1 White Point.
Chapter 7 + 10: Removed detailed Power Supply Unit
information for design protection reasons.

Manual xxxx xxx xxxx.1


Chapter 2: Table 2-1 updated (added CTNs).
Chapter 6: added Option codes at bit level;
see section 6.4.6 Option Bit Overview.
Chapter 11: added 55" styling sheet.

Manual xxxx xxx xxxx.5


Chapter 2: Table 2-1 updated (added CTNs).
Chapter 5: Added section 5.2.4 Hotel mode.
Chapter 10: Added Ambilight schematics and layouts
applicable for the added CTNs.

Manual xxxx xxx xxxx.2


Chapter 2: Table 2-1 updated (added CTNs).
Manual xxxx xxx xxxx.3
Chapter 2: added connection overview; see Figure 2-1.
Chapter 6: added White tone alignment values see Table
6-1 to Table 6-15.
Chapter 7 + 10: revelation of detailed Power Supply Unit
information to support component level repair;
see Table 2-1.

Manual xxxx xxx xxxx.6


Chapter 2: Table 2-1 updated (added CTNs).
Chapter 2: removed video/audio out from SCART
connector; see section 2.3.1.
Chapter 4: added section 4.7 Assy/Panel Removal
Berlinale styling (xxPFL5806K/xx).
Chapter 9: added figures 9-1 Wiring diagram Berlinale 32"
and 9-2 Wiring diagram Berlinale 40" - 46".

Manual xxxx xxx xxxx.4


Chapter 2: Table 2-1 updated (added CTNs).

Manual xxxx xxx xxxx.7


Chapter 2: Table 2-1 updated (added CTNs).

2. Technical Specs, Diversity, and Connections


2.1

Index of this chapter:


2.1 Technical Specifications
2.2 Directions for Use
2.3 Connections
2.4 Chassis Overview

Technical Specifications
For on-line product support please use the CTN links
in Table 2-1. Here is product information available, as well as
getting started, user manuals, frequently asked questions and
software & drivers.

Notes:
Figures can deviate due to the different set executions.
Specifications are indicative (subject to change).
Table 2-1 Described Model Numbers and Diversity
10

CTN

Styling

32PFL5806K/02

Berlinale
11-1

64955 2-2

4-1 4.7

4.7.9

9-1

32HFL7406D/10

Sundance
11-9

65192 2-1

4-9 4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

32PDL7906H/12

Infinity
11-7

65192 2-1

4-17 4.10 4.10.11 -

9-6

10-53 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-51 10-56

32PDL7906K/02

Infinity
11-7

65192 2-1

4-17 4.10 4.10.11 -

9-6

10-53 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-51 10-56

32PDL7906M/08

Infinity
11-7

65192 2-1

4-17 4.10 4.10.11 -

9-6

10-53 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-51 10-56

32PDL7906T/12

Infinity
11-7

65192 2-1

4-17 4.10 4.10.11 -

9-6

10-53 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-51 10-56

32PFL6606H/12

Blockbuster 64954 2-2


11-3
64955

4-4 4.8

4.8.7

7.2.2 -

9-3

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

32PFL6606H/60

Blockbuster 64954 2-2


11-3
64955

4-4 4.8

4.8.7

7.2.2 -

9-3

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-45 -

32PFL6606K/02

Blockbuster 64954 2-2


11-3
64955

4-4 4.8

4.8.7

7.2.2 -

9-3

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

32PFL6606M/08

Blockbuster 64954 2-2


11-3
64955

4-4 4.8

4.8.7

7.2.2 -

9-3

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

32PFL6606T/12

Blockbuster 65192 2-2


11-3

4-4 4.8

4.8.7

7.2.1 -

9-3

10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-44 -

32PFL6626H/12

Blockbuster 64954 2-2


11-3
64955

4-4 4.8

4.8.7

7.2.1 -

9-3

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

2011-Nov-04

back to
div. table

10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 -

10-44 -

10-44 -

TS (Temperature Sensor)

E (IR/LED/Key Board)

B10 (DVBT-2)

B09 (non-DVBS-conn.)

B08 (DVBS-Supp.)

B07 (DVBS-FE)

B06 (non-DVBS-LVDS)

B05 (DDR)

B04 (I/O)

B03 (DC/DC / Class D)

B02 (PNX85500)

B01 (Tuner)

A (PSU)

ALxx (Ambilight) LiteOn

Schematics

TCON

PSU

LCD Removal

Wiring Diagram

Descriptions

AmbiLight

Mechanics

Assembly Removal

Wire Dressing

Connection Overview

3139 123 xxxxx

SSB

Technical Specs, Diversity, and Connections

2.

EN 3

10

CTN

Styling

32PFL6626K/02

Blockbuster 64954 2-2


11-3
64955

4-4

4.8

4.8.7

7.2.1 -

9-3

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

32PFL6626M/08

Blockbuster 64954 2-2


64955
11-3

4-4

4.8

4.8.7

7.2.1 -

9-3

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

32PFL6626T/12

Blockbuster 65192 2-2


11-3

4-4

4.8

4.8.7

7.2.1 -

9-3

10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-44 -

32PFL6636H/12

Blockbuster 64954 2-2


64955
11-3

4-4

4.8

4.8.7

7.2.1 -

9-3

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

32PFL6636K/02

Blockbuster 64954 2-2


64955
11-3

4-4

4.8

4.8.7

7.2.1 -

9-3

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

32PFL6636M/08

Blockbuster 64954 2-2


64955
11-3

4-4

4.8

4.8.7

7.2.1 -

9-3

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

32PFL6636T/12

Blockbuster 65192 2-2


11-3

4-4

4.8

4.8.7

7.2.1 -

9-3

10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-44 -

32PFL7406H/12

Sundance
11-9

65192 2-1

4-9

4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

32PFL7406H/60

Sundance
11-9

65192 2-1

4-9

4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

32PFL7406K/02

Sundance
11-9

65192 2-1

4-9

4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

32PFL7406M/08

Sundance
11-9

65192 2-1

4-9

4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

32PFL7406T/12

Sundance
11-9

65192 2-1

4-9

4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

32PFL7476H/12

Sundance
11-9

65192 2-1

4-9

4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

32PFL7476K/02

Sundance
11-9

65192 2-1

4-9

4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

32PFL7486H/12

Sundance
11-9

65192 2-1

4-9

4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

32PFL7486K/02

Sundance
11-9

65192 2-1

4-9

4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

32PFL7486M/08

Sundance
11-9

65192 2-1

4-9

4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

32PFL7496H/12

Sundance
11-9

65192 2-1

4-9

4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

32PFL7496K/02

Sundance
11-9

65192 2-1

4-9

4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

32PFL7606H/12

Sundance
11-9

65192 2-1

4-9

4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

32PFL7606H/60

Sundance
11-9

65192 2-1

4-9

4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

32PFL7606K/02

Sundance
11-9

65192 2-1

4-9

4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

32PFL7606M/08

Sundance
11-9

65192 2-1

4-9

4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

32PFL7606T/12

Sundance
11-9

65192 2-1

4-9

4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-58

37PFL6606H/12

Blockbuster 64954 2-2


11-4
64955

4-5

4.8

4.8.7

7.2.1 -

9-4

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

37PFL6606H/60

Blockbuster 64954 2-2


11-4
64955

4-5

4.8

4.9.8

7.2.1 -

9-4

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-45 -

37PFL6606K/02

Blockbuster 64954 2-2


11-4
64955

4-5

4.8

4.8.7

7.2.1 -

9-4

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

37PFL6606M/08

Blockbuster 64954 2-2


11-4
64955

4-5

4.8

4.8.7

7.2.1 -

9-4

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

37PFL6606T/12

Blockbuster 65192 2-2


11-4

4-5

4.8

4.8.7

7.2.1 -

9-4

10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-44 -

37PFL7606H/12

Sundance
11-9

65192 2-1

4-10 4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

37PFL7606K/02

Sundance
11-9

65192 2-1

4-10 4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

37PFL7606M/08

Sundance
11-9

65192 2-1

4-10 4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

37PFL7606T/12

Sundance
11-9

65192 2-1

4-10 4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

37PFL7666H/12

Sundance
11-9

65192 2-1

4-10 4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

37PFL7666K/02

Sundance
11-9

65192 2-1

4-10 4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

37PFL7666T/12

Sundance
11-9

65192 2-1

4-10 4.9

4.9.8

9-8

10-55 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-60

back to
div. table

TS (Temperature Sensor)

E (IR/LED/Key Board)

B10 (DVBT-2)

B09 (non-DVBS-conn.)

B08 (DVBS-Supp.)

B07 (DVBS-FE)

B06 (non-DVBS-LVDS)

B05 (DDR)

B04 (I/O)

B03 (DC/DC / Class D)

B02 (PNX85500)

B01 (Tuner)

ALxx (Ambilight) LiteOn

A (PSU)

Wiring Diagram

Schematics

TCON

PSU

LCD Removal

AmbiLight

7
Descriptions

Assembly Removal

4
Mechanics

Wire Dressing

Connection Overview

3139 123 xxxxx

SSB

Q552.2E LA

2011-Nov-04

Technical Specs, Diversity, and Connections


10

CTN

Styling

37PFL7676H/12

Sundance
11-9

65192 2-1

4-10 4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

37PFL7676K/02

Sundance
11-9

65192 2-1

4-10 4.9

4.9.8

9-8

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

40PFL5806K/02

Berlinale
11-2

64955 2-2

4-2 4.7

4.7.9

9-2

10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-30 10-44 -

40PFL6606H/12

Blockbuster 64954 2-2


64955
11-5

4-6 4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

40PFL6606H/60

Blockbuster 64954 2-2


64955
11-5

4-6 4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

40PFL6606K/02

Blockbuster 64954 2-2


64955
11-5

4-6 4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

40PFL6606M/08

Blockbuster 64954 2-2


64955
11-5

4-6 4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

40PFL6606T/12

Blockbuster 65192 2-2


11-5

4-6 4.8

4.8.7

7.2.1 -

9-5

10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-44 -

40PFL6626H/12

Blockbuster 64954 2-2


64955
11-5

4-6 4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

40PFL6626K/02

Blockbuster 64954 2-2


11-5
64955

4-6 4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

40PFL6626M/08

Blockbuster 64954 2-2


11-5
64955

4-6 4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

40PFL6626T/12

Blockbuster 65192 2-2


11-5

4-6 4.8

4.8.7

7.2.1 -

9-5

10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-44 -

40PFL6636H/12

Blockbuster 64954 2-2


11-5
64955

4-6 4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

40PFL6636K/02

Blockbuster 64954 2-2


11-5
64955

4-6 4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

40PFL6636M/08

Blockbuster 64954 2-2


11-5
64955

4-6 4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-44 -

40PFL6636T/12

Blockbuster 65192 2-2


11-5

4-6 4.8

4.8.7

7.2.1 -

9-5

10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-44 -

42HFL7406D/10

Sundance
11-10

65192 2-1

4-11 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PDL7906H/12

Infinity
11-8

65192 2-1

4-18 4.10 4.10.11 -

9-7

10-53 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-51 10-57

42PDL7906K/02

Infinity
11-8

65192 2-1

4-18 4.10 4.10.11 -

9-7

10-53 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-51 10-57

42PDL7906M/08

Infinity
11-8

65192 2-1

4-18 4.10 4.10.11 -

9-7

10-53 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-51 10-57

42PDL7906T/12

Infinity
11-8

65192 2-1

4-18 4.10 4.10.11 -

9-7

10-53 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-51 10-57

42PFL7406H/12

Sundance
11-10

65192 2-1

4-11 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7406H/60

Sundance
11-10

65192 2-1

4-11 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7406T/12

Sundance
11-10

65192 2-1

4-11 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7406K/02

Sundance
11-10

65192 2-1

4-11 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7406M/08

Sundance
11-10

65192 2-1

4-11 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7456H/12

Sundance
11-10

65192 2-1

4-11 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7456K/02

Sundance
11-10

65192 2-1

4-11 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7456M/08

Sundance
11-10

65192 2-1

4-11 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7486H/12

Sundance
11-10

65192 2-1

4-11 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7486K/02

Sundance
11-10

65192 2-1

4-11 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7486M/08

Sundance
11-10

65192 2-1

4-11 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7606H/12

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7606H/60

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7606K/02

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7606M/08

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

2011-Nov-04

back to
div. table

TS (Temperature Sensor)

E (IR/LED/Key Board)

B10 (DVBT-2)

B09 (non-DVBS-conn.)

B08 (DVBS-Supp.)

B07 (DVBS-FE)

B06 (non-DVBS-LVDS)

B05 (DDR)

B04 (I/O)

B03 (DC/DC / Class D)

B02 (PNX85500)

B01 (Tuner)

Schematics

TCON

PSU

LCD Removal

ALxx (Ambilight) LiteOn

Descriptions

A (PSU)

Mechanics

AmbiLight

Assembly Removal

3139 123 xxxxx

SSB

Wiring Diagram

Q552.2E LA

Wire Dressing

2.

Connection Overview

EN 4

Technical Specs, Diversity, and Connections

2.

EN 5

10
TS (Temperature Sensor)

E (IR/LED/Key Board)

B10 (DVBT-2)

B09 (non-DVBS-conn.)

B08 (DVBS-Supp.)

B07 (DVBS-FE)

B06 (non-DVBS-LVDS)

B05 (DDR)

B04 (I/O)

B03 (DC/DC / Class D)

B02 (PNX85500)

B01 (Tuner)

ALxx (Ambilight) LiteOn

A (PSU)

Wiring Diagram

Schematics

TCON

PSU

LCD Removal

AmbiLight

7
Descriptions

Assembly Removal

4
Mechanics

Wire Dressing

Connection Overview

3139 123 xxxxx

SSB

Q552.2E LA

CTN

Styling

42PFL7606T/12

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7656H/12

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7656K/02

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7656M/08

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7656T/12

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7666H/12

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7666H/60

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-68
10-59

42PFL7666K/02

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7666T/12

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-55 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-60

42PFL7676H/12

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7676K/02

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7676T/12

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7696H/12

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7696K/02

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7696M/08

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

42PFL7696T/12

Sundance
11-10

65192 2-1

4-14 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-59

46PFL5806K/02

Berlinale
11-2

64955 2-2

4-3

4.7

4.7.9

9-2

10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-46 -

46PFL6606H/12

Blockbuster 64954 2-2


11-5
64955

4-7

4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-46 -

46PFL6606H/60

Blockbuster 64954 2-2


11-5
64955

4-7

4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-46 -

46PFL6606K/02

Blockbuster 64954 2-2


11-5
64955

4-7

4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-46 -

46PFL6606M/08

Blockbuster 64954 2-2


11-5
64955

4-7

4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-46 -

46PFL6606T/12

Blockbuster 65192 2-2


11-5

4-7

4.8

4.8.7

7.2.1 -

9-5

10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-46 -

46PFL6626H/12

Blockbuster 64954 2-2


11-5
64955

4-7

4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-46 -

46PFL6626K/02

Blockbuster 64954 2-2


11-5
64955

4-7

4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-46 -

46PFL6626T/12

Blockbuster 65192 2-2


11-5

4-7

4.8

4.8.7

7.2.1 -

9-5

10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-46 -

46PFL6806H/12

Blockbuster 65351 2-2


11-5

4-7

4.8

4.8.7

7.2.1 -

9-5

10-32 10-33 10-34 10-35 10-36 10-37 10-38 10-39 10-40 -

10-47 -

46PFL6806H/60

Blockbuster 65351 2-2


11-5

4-7

4.8

4.8.7

7.2.1 -

9-5

10-32 10-33 10-34 10-35 10-36 10-37 10-38 10-39 10-40 -

10-47 -

46PFL6806K/02

Blockbuster 65351 2-2


11-5

4-7

4.8

4.8.7

7.2.1 -

9-5

10-32 10-33 10-34 10-35 10-36 10-37 10-38 10-39 10-40 -

10-47 -

46PFL6806T/12

Blockbuster 65371 2-2


11-5

4-7

4.8

4.8.7

7.2.1 -

9-5

10-32 10-33 10-34 10-35 10-36 10-37 10-38 10-39 10-40 10-41 10-47 -

47PFL7456H/12

Sundance
11-10

65192 2-1

4-12 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

47PFL7456K/02

Sundance
11-10

65192 2-1

4-12 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

47PFL7606H/12

Sundance
11-10

65192 2-1

4-15 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

47PFL7606H/60

Sundance
11-10

65192 2-1

4-15 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

47PFL7606K/02

Sundance
11-10

65192 2-1

4-15 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

47PFL7606M/08

Sundance
11-10

65192 2-1

4-15 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

47PFL7606T/12

Sundance
11-10

65192 2-1

4-15 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

back to
div. table

2011-Nov-04

10
TS (Temperature Sensor)

E (IR/LED/Key Board)

B10 (DVBT-2)

B09 (non-DVBS-conn.)

B08 (DVBS-Supp.)

B07 (DVBS-FE)

B06 (non-DVBS-LVDS)

B05 (DDR)

B04 (I/O)

B03 (DC/DC / Class D)

B02 (PNX85500)

B01 (Tuner)

ALxx (Ambilight) LiteOn

Schematics

TCON

PSU

LCD Removal

A (PSU)

Descriptions

Wiring Diagram

Mechanics

AmbiLight

Assembly Removal

3139 123 xxxxx

SSB

2.2

Technical Specs, Diversity, and Connections

Q552.2E LA

Wire Dressing

2.

Connection Overview

EN 6

CTN

Styling

47PFL7656H/12

Sundance
11-10

65192 2-1

4-15 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

47PFL7656K/02

Sundance
11-10

65192 2-1

4-15 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

47PFL7656M/08

Sundance
11-10

65192 2-1

4-15 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

47PFL7656T/12

Sundance
11-10

65192 2-1

4-15 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

47PFL7666H/12

Sundance
11-10

65192 2-1

4-15 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

47PFL7666K/02

Sundance
11-10

65192 2-1

4-15 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

47PFL7666T/12

Sundance
11-10

65192 2-1

4-15 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

47PFL7696H/12

Sundance
11-10

65192 2-1

4-15 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

47PFL7696K/02

Sundance
11-10

65192 2-1

4-15 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

47PFL7696M/08

Sundance
11-10

65192 2-1

4-15 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

47PFL7696T/12

Sundance
11-10

65192 2-1

4-15 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-48 10-61

55PFL6606H/12

Blockbuster 64954 2-2


11-6
64955

4-8 4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-46 -

55PFL6606H/60

Blockbuster 64954 2-2


11-6
64955

4-8 4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-46 -

55PFL6606K/02

Blockbuster 64954 2-2


11-6
64955

4-8 4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-46 -

55PFL6606M/08

Blockbuster 64954 2-2


11-6
64955

4-8 4.8

4.8.7

7.2.1 -

9-5

10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19

10-46 -

55PFL6606T/12

Blockbuster 65192 2-2


11-5

4-8 4.8

4.8.7

7.2.1 -

9-5

10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-46 -

55PFL7606H/12

Sundance
11-10

65192 2-1

4-16 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-46 10-68
10-61

55PFL7606K/02

Sundance
11-10

65192 2-1

4-16 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-46 10-68
10-61

55PFL7606T/12

Sundance
11-10

65192 2-1

4-16 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-46 10-68
10-61

55PFL7606T/60

Sundance
11-10

65192 2-1

4-16 4.9

4.9.8

9-9

10-54 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-46 10-68
10-61

Directions for Use


You can download this information from the following websites:
http://www.philips.com/support
http://www.p4c.philips.com

2011-Nov-04

back to
div. table

Technical Specs, Diversity, and Connections


2.3

Q552.2E LA

2.

EN 7

Connections

SIDE CONNECTORS

REAR CONNECTORS

PFL7XX6K

15

Optional

1
2

EXT 1

(RGB/CVBS)

6
3

BOTTOM REAR CONNECTORS


7

10

10

11

12

13

16

14
17

17
19

19103_001_110525.eps
110525

Figure 2-1 Connection overview (Sundance + Infinity)

back to
div. table

2011-Nov-04

EN 8

2.

Q552.2E LA

Technical Specs, Diversity, and Connections

SIDE CONNECTORS

REAR CONNECTORS
5

15
1
2
4
3
16

BOTTOM REAR CONNECTORS


7

10

11

13

14

17
18
19

19100_043_110214.eps
110525

Figure 2-2 Connection overview (Berlinale + Blockbuster)


15 - Video Red
16 - Status/FBL

Note: The following connector colour abbreviations are used


(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy=
Grey, Rd= Red, Wh= White, Ye= Yellow.
2.3.1

17
18
19
20
21

Rear Connections
1 - EXT1: Video RGB - In, CVBS - In, Audio - In
20

21

- Ground Video
- Ground FBL
- n.c.
- Video CVBS
- Shield

j
H
H

1 VPP / 75 ohm
Gnd

j
H

2 - Service Connector (UART)


1 - Ground
Gnd
2 - UART_TX
Transmit
3 - UART_RX
Receive

10000_001_090121.eps
090121

0.7 VPP / 75 ohm


0 - 0.4 V: INT
1 - 3 V: EXT / 75 ohm
Gnd
Gnd

H
k
j

Figure 2-3 SCART connector


1
2
3
4
5
6
7
8

- n.c.
- Audio R
- n.c.
- Ground Audio
- Ground Blue
- Audio L
- Video Blue
- Function Select

9
10
11
12
13
14

- Ground Green
- n.c.
- Video Green
- n.c.
- Ground Red
- Ground P50

2011-Nov-04

0.5 VRMS / 10 kohm

Gnd
Gnd
0.5 VRMS / 10 kohm
0.7 VPP / 75 ohm
0 - 2 V: INT
4.5 - 7 V: EXT 16:9
9.5 - 12 V: EXT 4:3
Gnd

H
H
j
jk

0.7 VPP / 75 ohm


Gnd
Gnd

j
H

3 - EXT2: Cinch: Video YPbPr - In, Audio - In


Gn - Video Y
1 VPP / 75 ohm
Bu - Video Pb
0.7 VPP / 75 ohm
Rd - Video Pr
0.7 VPP / 75 ohm
Rd - Audio - R
0.5 VRMS / 10 kohm
Wh - Audio - L
0.5 VRMS / 10 kohm

jq
jq
jq
jq
jq

4 - Cinch: Audio - In (VGA/DVI)


Rd - Audio R
0.5 VRMS / 10 kohm
Wh - Audio L
0.5 VRMS / 10 kohm

jq
jq

5 - SAT - In
- - F-type

Coax, 75 ohm

6 - Head phone (Output)


Bk - Head phone
32 - 600 ohm / 10 mW

H
H
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div. table

ot

Technical Specs, Diversity, and Connections


2.3.2

10
11
12
13
14
15
16
17
18
19
20

Rear Connections - Bottom


7 - RJ45: Ethernet
12345678

10000_025_090121.eps
090121

Figure 2-4 Ethernet connector


1
2
3
4
5
6
7
8

- TD+
- TD- RD+
- CT
- CT
- RD- GND
- GND

Transmit signal
Transmit signal
Receive signal
Centre Tap: DC level fixation
Centre Tap: DC level fixation
Receive signal
Gnd
Gnd

k
k
j

Q552.2E LA

- CLK+
- Shield
- CLK- Easylink/CEC
- ARC
- DDC_SCL
- DDC_SDA
- Ground
- +5V
- HPD
- Ground

9 - Optical: S/PDIF - Out


Bk - Coaxial
Optical signal

Hot Plug Detect


Gnd

13 - Aerial - In
- - IEC-type (EU)

j
H
H

kq

Figure 2-7 VGA Connector


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

j
H
j
j
H
j
j
H
j
j
H
j
jk

DDC clock
DDC data
Gnd

j
jk
H
j
j
H

2.3.3

- Video Red
- Video Green
- Video Blue
- n.c.
- Ground
- Ground Red
- Ground Green
- Ground Blue
- +5VDC
- Ground Sync
- n.c.
- DDC_SDA
- H-sync
- V-sync
- DDC_SCL

H
H
H
H
j
H

DDC data
0-5V
0-5V
DDC clock

j
j
j
j

jk

14
GND

1
2

Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Data channel
Gnd
Data channel

Gnd
Gnd
Gnd
Gnd
+5 V
Gnd

16 - SD-Card: Secure Digital Card - In/Out (optional)

Figure 2-6 HDMI (type A) connector


- D2+
- Shield
- D2- D1+
- Shield
- D1- D0+
- Shield
- D0-

j
j
j

15 - Common Interface
68p - See diagram B01A B01 313912364954

10000_017_090121.eps
090428

1
2
3
4
5
6
7
8
9

0.7 VPP / 75 ohm


0.7 VPP / 75 ohm
0.7 VPP / 75 ohm

Side Connections

11 - HDMI 1: Digital Video - In, Digital Audio with ARC - In/


Out
19
18

10
15

10000_002_090121.eps
090127

1
2

Hot Plug Detect


Gnd

11

Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Control channel

Coax, 75 ohm

Figure 2-5 HDMI (type A) connector


- D2+
- Shield
- D2- D1+
- Shield
- D1- D0+
- Shield
- D0- CLK+
- Shield
- CLK- Easylink/CEC
- n.c.
- DDC_SCL
- DDC_SDA
- Ground
- +5V
- HPD
- Ground

jq
jq

14 - VGA: Video RGB - In

10000_017_090121.eps
090428

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

j
H
j
jk
k
j
jk
H
j
j
H

12 - Cinch: Audio - In (VGA/DVI)


Rd - Audio R
0.5 VRMS / 10 kohm
Wh - Audio L
0.5 VRMS / 10 kohm

10 - HDMI 2: Digital Video, Digital Audio - In


19
18

EN 9

Data channel
Gnd
Data channel
Control channel
Audio Return Channel
DDC clock
DDC data
Gnd

8 - Cinch: S/PDIF - Out


Bk - Coaxial
0.4 - 0.6VPP / 75 ohm

2.

WP

12

GND

11

CD

10

DAT1/IRQ

DAT0/D0

GND2

CLOCK

VDD

GND1

CMD/DI

DAT3/CS

DAT2/NC

GND
13

j
H
j
j
H
j
j
H
j

10000_049_100210.eps
100210

Figure 2-8 SD-Card connector


1
2
3
4
back to
div. table

- DAT3/CS
- CMD/DI
- GND1
- Vdd

Signal
Signal
Gnd
Supply

jk
k
H
k
2011-Nov-04

EN 10
5
6
7
8
9
10
11
12
13
14

2.

Q552.2E LA

- CLOCK
- GND2
- DAT0/D0
- DAT1/IRQ
- DAT2/NC
- CD
- GND
- WP
- GND
- GND

Technical Specs, Diversity, and Connections


k
H
jk
jk
jk
j
H
j
H
H

Signal
Gnd
Signal
Signal
Signal
Signal
Gnd
Signal
Gnd
Gnd

1
2
3
4

19 - HDMI : Digital Video, Digital Audio - In


See 10 - HDMI 2: Digital Video, Digital Audio - In

10000_022_090121.eps
090121

Figure 2-9 USB (type A)

2.4

Chassis Overview
Refer to chapter Block Diagrams for PWB/CBA locations.

2011-Nov-04

Gnd

18 - Head phone (Output)


Bk - Head phone
32 - 600 ohm / 10 mW

17 - USB2.0

- +5V
- Data (-)
- Data (+)
- Ground

back to
div. table

k
jk
jk
H

ot

Precautions, Notes, and Abbreviation List

Q552.2E LA

3.

EN 11

3. Precautions, Notes, and Abbreviation List

Index of this chapter:


3.1 Safety Instructions
3.2 Warnings
3.3 Notes
3.4 Abbreviation List

3.1

3.3.2

Safety Instructions

Safety regulations require that after a repair, the set must be


returned in its original condition. Pay in particular attention to
the following points:
Route the wire trees correctly and fix them with the
mounted cable clamps.
Check the insulation of the Mains/AC Power lead for
external damage.
Check the strain relief of the Mains/AC Power cord for
proper function.
Check the electrical DC resistance between the Mains/AC
Power plug and the secondary side (only for sets that have
a Mains/AC Power isolated power supply):
1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug.
2. Set the Mains/AC Power switch to the on position
(keep the Mains/AC Power cord unplugged!).
3. Measure the resistance value between the pins of the
Mains/AC Power plug and the metal shielding of the
tuner or the aerial connection on the set. The reading
should be between 4.5 M and 12 M.
4. Switch off the set, and remove the wire between the
two pins of the Mains/AC Power plug.
Check the cabinet for defects, to prevent touching of any
inner parts by the customer.

3.3.3

All resistor values are in ohms, and the value multiplier is


often used to indicate the decimal point location (e.g. 2K2
indicates 2.2 k).
Resistor values with no multiplier may be indicated with
either an E or an R (e.g. 220E or 220R indicates 220 ).
All capacitor values are given in micro-farads ( = 10-6),
nano-farads (n = 10-9), or pico-farads (p = 10-12).
Capacitor values may also use the value multiplier as the
decimal point indication (e.g. 2p2 indicates 2.2 pF).
An asterisk (*) indicates component usage varies. Refer
to the diversity tables for the correct values.
The correct component values are listed on the Philips
Spare Parts Web Portal.

Spare Parts
For the latest spare part overview, consult your Philips Spare
Part web portal.

3.3.4

BGA (Ball Grid Array) ICs


Introduction
For more information on how to handle BGA devices, visit this
URL: http://www.atyourservice-magazine.com. Select
Magazine, then go to Repair downloads. Here you will find
Information on how to deal with BGA-ICs.
BGA Temperature Profiles
For BGA-ICs, you must use the correct temperature-profile.
Where applicable and available, this profile is added to the IC
Data Sheet information section in this manual.

3.3.5

3.2

Schematic Notes

Safety regulations require the following during a repair:


Connect the set to the Mains/AC Power via an isolation
transformer (> 800 VA).
Replace safety components, indicated by the symbol h,
only by components identical to the original ones. Any
other component substitution (other than original type) may
increase risk of fire or electrical shock hazard.

Where necessary, measure the waveforms and voltages


with (D) and without (E) aerial signal. Measure the
voltages in the power supply section both in normal
operation (G) and in stand-by (F). These values are
indicated by means of the appropriate symbols.

Lead-free Soldering

Warnings

3.3

Notes

3.3.1

General

Due to lead-free technology some rules have to be respected


by the workshop during a repair:
Use only lead-free soldering tin. If lead-free solder paste is
required, please contact the manufacturer of your soldering
equipment. In general, use of solder paste within
workshops should be avoided because paste is not easy to
store and to handle.
Use only adequate solder tools applicable for lead-free
soldering tin. The solder tool must be able:
To reach a solder-tip temperature of at least 400C.
To stabilize the adjusted temperature at the solder-tip.
To exchange solder-tips for different applications.
Adjust your solder tool so that a temperature of around
360C - 380C is reached and stabilized at the solder joint.
Heating time of the solder-joint should not exceed ~ 4 sec.
Avoid temperatures above 400C, otherwise wear-out of
tips will increase drastically and flux-fluid will be destroyed.
To avoid wear-out of tips, switch off unused equipment or
reduce heat.
Mix of lead-free soldering tin/parts with leaded soldering
tin/parts is possible but PHILIPS recommends strongly to
avoid mixed regimes. If this cannot be avoided, carefully
clear the solder-joint from old tin and re-solder with new tin.

All ICs and many other semiconductors are susceptible to


electrostatic discharges (ESD w). Careless handling
during repair can reduce life drastically. Make sure that,
during repair, you are connected with the same potential as
the mass of the set by a wristband with resistance. Keep
components and tools also at this same potential.
Be careful during measurements in the high voltage
section.
Never replace modules or other components while the unit
is switched on.
When you align the set, use plastic rather than metal tools.
This will prevent any short circuits and the danger of a
circuit becoming unstable.

Measure the voltages and waveforms with regard to the


chassis (= tuner) ground (H), or hot ground (I), depending
on the tested area of circuitry. The voltages and waveforms
shown in the diagrams are indicative. Measure them in the
Service Default Mode with a colour bar signal and stereo
sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and
picture carrier at 475.25 MHz for PAL, or 61.25 MHz for
NTSC (channel 3).

3.3.6

Alternative BOM identification


It should be noted that on the European Service website,
Alternative BOM is referred to as Design variant.

back to
div. table

2011-Nov-04

EN 12

3.

Q552.2E LA

Precautions, Notes, and Abbreviation List


3.4

The third digit in the serial number (example:


AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the
specific TV set. In general, it is possible that the same TV
model on the market is produced with e.g. two different types
of displays, coming from two different suppliers. This will then
result in sets which have the same CTN (Commercial Type
Number; e.g. 28PW9515/12) but which have a different B.O.M.
number.
By looking at the third digit of the serial number, one can
identify which B.O.M. is used for the TV set he is working with.
If the third digit of the serial number contains the number 1
(example: AG1B033500001), then the TV set has been
manufactured according to B.O.M. number 1. If the third digit is
a 2 (example: AG2B0335000001), then the set has been
produced according to B.O.M. no. 2. This is important for
ordering the correct spare parts!
For the third digit, the numbers 1...9 and the characters A...Z
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be
indicated by the third digit of the serial number.

Abbreviation List
0/6/12

AARA

ACI

ADC
AFC

AGC

Identification: The bottom line of a type plate gives a 14-digit


serial number. Digits 1 and 2 refer to the production centre (e.g.
SN is Lysomice, RJ is Kobierzyce), digit 3 refers to the B.O.M.
code, digit 4 refers to the Service version change code, digits 5
and 6 refer to the production year, and digits 7 and 8 refer to
production week (in example below it is 2010 week 10 / 2010
week 17). The 6 last digits contain the serial number.

AM
AP
AR
ASF

ATSC

ATV
Auto TV

AV
AVC
AVIP
B/G
BDS
BLR
BTSC

B-TXT
C
CEC

10000_053_110228.eps
110228

Figure 3-1 Serial number (example)


3.3.7

CL

Board Level Repair (BLR) or Component Level Repair


(CLR)

CLR
ComPair
CP
CSM
CTI

If a board is defective, consult your repair procedure to decide


if the board has to be exchanged or if it should be repaired on
component level.
If your repair procedure says the board should be exchanged
completely, do not solder on the defective board. Otherwise, it
cannot be returned to the O.E.M. supplier for back charging!
3.3.8

CVBS

Practical Service Precautions

2011-Nov-04

DAC
DBE

It makes sense to avoid exposure to electrical shock.


While some sources are expected to have a possible
dangerous impact, others of quite high potential are of
limited current and are sometimes held in less regard.
Always respect voltages. While some may not be
dangerous in themselves, they can cause unexpected
reactions that are best avoided. Before reaching into a
powered TV set, it is best to test the high voltage insulation.
It is easy to do, and is a good service precaution.

DCM

DDC
D/K
DFI
back to
div. table

SCART switch control signal on A/V


board. 0 = loop through (AUX to TV),
6 = play 16 : 9 format, 12 = play 4 : 3
format
Automatic Aspect Ratio Adaptation:
algorithm that adapts aspect ratio to
remove horizontal black bars; keeps
the original aspect ratio
Automatic Channel Installation:
algorithm that installs TV channels
directly from a cable network by
means of a predefined TXT page
Analogue to Digital Converter
Automatic Frequency Control: control
signal used to tune to the correct
frequency
Automatic Gain Control: algorithm that
controls the video input of the feature
box
Amplitude Modulation
Asia Pacific
Aspect Ratio: 4 by 3 or 16 by 9
Auto Screen Fit: algorithm that adapts
aspect ratio to remove horizontal black
bars without discarding video
information
Advanced Television Systems
Committee, the digital TV standard in
the USA
See Auto TV
A hardware and software control
system that measures picture content,
and adapts image parameters in a
dynamic way
External Audio Video
Audio Video Controller
Audio Video Input Processor
Monochrome TV system. Sound
carrier distance is 5.5 MHz
Business Display Solutions (iTV)
Board-Level Repair
Broadcast Television Standard
Committee. Multiplex FM stereo sound
system, originating from the USA and
used e.g. in LATAM and AP-NTSC
countries
Blue TeleteXT
Centre channel (audio)
Consumer Electronics Control bus:
remote control bus on HDMI
connections
Constant Level: audio output to
connect with an external amplifier
Component Level Repair
Computer aided rePair
Connected Planet / Copy Protection
Customer Service Mode
Color Transient Improvement:
manipulates steepness of chroma
transients
Composite Video Blanking and
Synchronization
Digital to Analogue Converter
Dynamic Bass Enhancement: extra
low frequency amplification
Data Communication Module. Also
referred to as System Card or
Smartcard (for iTV).
See E-DDC
Monochrome TV system. Sound
carrier distance is 6.5 MHz
Dynamic Frame Insertion

Precautions, Notes, and Abbreviation List


DFU
DMR
DMSD
DNM
DNR
DRAM
DRM
DSP
DST

DTCP

DVB-C
DVB-T
DVD
DVI(-d)
E-DDC

EDID
EEPROM
EMI
EPG
EPLD
EU
EXT
FDS
FDW
FLASH
FM
FPGA
FTV
Gb/s
G-TXT
H
HD
HDD
HDCP

HDMI
HP
I
I2 C
I2 D
I2 S
IF
IR
IRQ
ITU-656

Directions For Use: owner's manual


Digital Media Reader: card reader
Digital Multi Standard Decoding
Digital Natural Motion
Digital Noise Reduction: noise
reduction feature of the set
Dynamic RAM
Digital Rights Management
Digital Signal Processing
Dealer Service Tool: special remote
control designed for service
technicians
Digital Transmission Content
Protection; A protocol for protecting
digital audio/video content that is
traversing a high speed serial bus,
such as IEEE-1394
Digital Video Broadcast - Cable
Digital Video Broadcast - Terrestrial
Digital Versatile Disc
Digital Visual Interface (d= digital only)
Enhanced Display Data Channel
(VESA standard for communication
channel and display). Using E-DDC,
the video source can read the EDID
information form the display.
Extended Display Identification Data
(VESA standard)
Electrically Erasable and
Programmable Read Only Memory
Electro Magnetic Interference
Electronic Program Guide
Erasable Programmable Logic Device
Europe
EXTernal (source), entering the set by
SCART or by cinches (jacks)
Full Dual Screen (same as FDW)
Full Dual Window (same as FDS)
FLASH memory
Field Memory or Frequency
Modulation
Field-Programmable Gate Array
Flat TeleVision
Giga bits per second
Green TeleteXT
H_sync to the module
High Definition
Hard Disk Drive
High-bandwidth Digital Content
Protection: A key encoded into the
HDMI/DVI signal that prevents video
data piracy. If a source is HDCP coded
and connected via HDMI/DVI without
the proper HDCP decoding, the
picture is put into a snow vision mode
or changed to a low resolution. For
normal content distribution the source
and the display device must be
enabled for HDCP software key
decoding.
High Definition Multimedia Interface
HeadPhone
Monochrome TV system. Sound
carrier distance is 6.0 MHz
Inter IC bus
Inter IC Data bus
Inter IC Sound bus
Intermediate Frequency
Infra Red
Interrupt Request
The ITU Radio communication Sector
(ITU-R) is a standards body
subcommittee of the International
Telecommunication Union relating to
radio communication. ITU-656 (a.k.a.

iTV
LS

LATAM
LCD
LED
L/L'

LPL
LS
LVDS
Mbps
M/N
MHEG

MIPS

MOP
MOSFET
MPEG
MPIF
MUTE
MTV
NC
NICAM

NTC
NTSC

NVM
O/C
OSD
OAD

OTC
P50
PAL

back to
div. table

Q552.2E LA

3.

EN 13

SDI), is a digitized video format used


for broadcast grade video.
Uncompressed digital component or
digital composite signals can be used.
The SDI signal is self-synchronizing,
uses 8 bit or 10 bit data words, and has
a maximum data rate of 270 Mbit/s,
with a minimum bandwidth of 135
MHz.
Institutional TeleVision; TV sets for
hotels, hospitals etc.
Last Status; The settings last chosen
by the customer and read and stored
in RAM or in the NVM. They are called
at start-up of the set to configure it
according to the customer's
preferences
Latin America
Liquid Crystal Display
Light Emitting Diode
Monochrome TV system. Sound
carrier distance is 6.5 MHz. L' is Band
I, L is all bands except for Band I
LG.Philips LCD (supplier)
Loudspeaker
Low Voltage Differential Signalling
Mega bits per second
Monochrome TV system. Sound
carrier distance is 4.5 MHz
Part of a set of international standards
related to the presentation of
multimedia information, standardised
by the Multimedia and Hypermedia
Experts Group. It is commonly used as
a language to describe interactive
television services
Microprocessor without Interlocked
Pipeline-Stages; A RISC-based
microprocessor
Matrix Output Processor
Metal Oxide Silicon Field Effect
Transistor, switching device
Motion Pictures Experts Group
Multi Platform InterFace
MUTE Line
Mainstream TV: TV-mode with
Consumer TV features enabled (iTV)
Not Connected
Near Instantaneous Compounded
Audio Multiplexing. This is a digital
sound system, mainly used in Europe.
Negative Temperature Coefficient,
non-linear resistor
National Television Standard
Committee. Color system mainly used
in North America and Japan. Color
carrier NTSC M/N= 3.579545 MHz,
NTSC 4.43= 4.433619 MHz (this is a
VCR norm, it is not transmitted off-air)
Non-Volatile Memory: IC containing
TV related data such as alignments
Open Circuit
On Screen Display
Over the Air Download. Method of
software upgrade via RF transmission.
Upgrade software is broadcasted in
TS with TV channels.
On screen display Teletext and
Control; also called Artistic (SAA5800)
Project 50: communication protocol
between TV and peripherals
Phase Alternating Line. Color system
mainly used in West Europe (colour
carrier = 4.433619 MHz) and South
America (colour carrier
2011-Nov-04

EN 14

3.

PCB
PCM
PDP
PFC
PIP
PLL

POD

POR
PSDL
PSL
PSLS

PTC
PWB
PWM
QRC
QTNR
QVCP
RAM
RGB

RC
RC5 / RC6
RESET
ROM
RSDS
R-TXT
SAM
S/C
SCART

SCL
SCL-F
SD
SDA
SDA-F
SDI
SDRAM
SECAM

SIF
SMPS
SoC
SOG
SOPS
SPI

S/PDIF
SRAM
SRP
SSB
SSC
STB
STBY
2011-Nov-04

Q552.2E LA

Precautions, Notes, and Abbreviation List


SVGA
SVHS
SW
SWAN

PAL M = 3.575612 MHz and


PAL N = 3.582056 MHz)
Printed Circuit Board (same as PWB)
Pulse Code Modulation
Plasma Display Panel
Power Factor Corrector (or Preconditioner)
Picture In Picture
Phase Locked Loop. Used for e.g.
FST tuning systems. The customer
can give directly the desired frequency
Point Of Deployment: a removable
CAM module, implementing the CA
system for a host (e.g. a TV-set)
Power On Reset, signal to reset the uP
Power Supply for Direct view LED
backlight with 2D-dimming
Power Supply with integrated LED
drivers
Power Supply with integrated LED
drivers with added Scanning
functionality
Positive Temperature Coefficient,
non-linear resistor
Printed Wiring Board (same as PCB)
Pulse Width Modulation
Quasi Resonant Converter
Quality Temporal Noise Reduction
Quality Video Composition Processor
Random Access Memory
Red, Green, and Blue. The primary
color signals for TV. By mixing levels
of R, G, and B, all colors (Y/C) are
reproduced.
Remote Control
Signal protocol from the remote
control receiver
RESET signal
Read Only Memory
Reduced Swing Differential Signalling
data interface
Red TeleteXT
Service Alignment Mode
Short Circuit
Syndicat des Constructeurs
d'Appareils Radiorcepteurs et
Tlviseurs
Serial Clock I2C
CLock Signal on Fast I2C bus
Standard Definition
Serial Data I2C
DAta Signal on Fast I2C bus
Serial Digital Interface, see ITU-656
Synchronous DRAM
SEequence Couleur Avec Mmoire.
Colour system mainly used in France
and East Europe. Colour
carriers = 4.406250 MHz and
4.250000 MHz
Sound Intermediate Frequency
Switched Mode Power Supply
System on Chip
Sync On Green
Self Oscillating Power Supply
Serial Peripheral Interface bus; a 4wire synchronous serial data link
standard
Sony Philips Digital InterFace
Static RAM
Service Reference Protocol
Small Signal Board
Spread Spectrum Clocking, used to
reduce the effects of EMI
Set Top Box
STand-BY

SXGA
TFT
THD
TMDS
TS
TXT
TXT-DW
UI
uP
UXGA
V
VESA
VGA
VL
VSB
WYSIWYR

WXGA
XTAL
XGA
Y
Y/C
YPbPr

YUV

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800 600 (4:3)


Super Video Home System
Software
Spatial temporal Weighted Averaging
Noise reduction
1280 1024
Thin Film Transistor
Total Harmonic Distortion
Transmission Minimized Differential
Signalling
Transport Stream
TeleteXT
Dual Window with TeleteXT
User Interface
Microprocessor
1600 1200 (4:3)
V-sync to the module
Video Electronics Standards
Association
640 480 (4:3)
Variable Level out: processed audio
output toward external amplifier
Vestigial Side Band; modulation
method
What You See Is What You Record:
record selection that follows main
picture and sound
1280 768 (15:9)
Quartz crystal
1024 768 (4:3)
Luminance signal
Luminance (Y) and Chrominance (C)
signal
Component video. Luminance and
scaled color difference signals (B-Y
and R-Y)
Component video

Mechanical Instructions

Q552.2E LA

4.

EN 15

4. Mechanical Instructions
Index of this chapter:
4.1 Cable Dressing Berlinale Styling (xxPFL58x6x/xx series)
4.2 Cable Dressing Blockbuster Styling (xxPFL66x6x/xx series)
4.3 Cable Dressing Sundance Styling (xxPFL74x6x/xx series)
4.4 Cable Dressing Sundance Styling (xxPFL76x6x/xx series; WiFi)
4.5 Cable Dressing Infinity Styling (xxPDL79x6x/xx series)
4.6 Service Positions
4.7 Assy/Panel Removal Berlinale styling (xxPFL5806K/xx)
4.8 Assy/Panel Removal Blockbuster Styling (xxPFL6xxx/xx series)
4.9 Assy/Panel Removal Sundance Styling (xxPFL7xxx/xx series)
4.10 Assy/Panel Removal Infinity Styling (xxPDL79xx/xx series)
4.11 Set Re-assembly
Notes:
Figures below can deviate slightly from the actual situation,
due to the different set executions.

4.1

Cable Dressing Berlinale Styling (xxPFL58x6x/xx series)

1 tape (150 m.m.)


10 tapes (80 m.m.)
1 tape (50 m.m.)
1 tape (25 m.m.)
2 11 m.m. clamp
19106_049_110928.eps
110928

Figure 4-1 Cable dressing 32PFL58x6x/xx (Berlinale)

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2011-Nov-04

EN 16

4.

Mechanical Instructions

Q552.2E LA

3 tape (100 m.m.)


5 tapes (80 m.m.)
3 tapes (50 m.m.)
1 tape (25 m.m.)
2 11 m.m. clamp
1 stick-on clamp
19106_050_110928.eps
110928

Figure 4-2 Cable dressing 40PFL58x6x/xx (Berlinale)

2011-Nov-04

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Mechanical Instructions

Q552.2E LA

4.

EN 17

3 tape (100 m.m.)


9 tapes (80 m.m.)
1 tape (25 m.m.)
2 11 m.m. clamp
1 stick-on clamp
19106_051_110928.eps
110928

Figure 4-3 Cable dressing 46PFL58x6x/xx (Berlinale)

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2011-Nov-04

EN 18
4.2

4.

Q552.2E LA

Mechanical Instructions

Cable Dressing Blockbuster Styling (xxPFL66x6x/xx series)

19100_044_110214.eps
110214

Figure 4-4 Cable dressing 32PFL66x6x/xx (Blockbuster)

2011-Nov-04

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Mechanical Instructions

Q552.2E LA

4.

EN 19

19100_045_110214.eps
111103

Figure 4-5 Cable dressing 37PFL66x6x/xx (Blockbuster)

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2011-Nov-04

EN 20

4.

Q552.2E LA

Mechanical Instructions

19100_046_110214.eps
111103

Figure 4-6 Cable dressing 40PFL66x6x/xx (Blockbuster)

2011-Nov-04

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Mechanical Instructions

Q552.2E LA

4.

EN 21

19101_001_110407.eps
111103

Figure 4-7 Cable dressing 46PFL6xx6x/xx (Blockbuster)

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2011-Nov-04

EN 22

4.

Q552.2E LA

Mechanical Instructions

19101_002_110407.eps
111103

Figure 4-8 Cable dressing 55PFL66x6x/xx (Blockbuster)

2011-Nov-04

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Mechanical Instructions
4.3

Q552.2E LA

4.

EN 23

Cable Dressing Sundance Styling (xxPFL74x6x/xx series)

19104_057_110701.eps
110701

Figure 4-9 Cable dressing 32PFL74x6x/xx & 32PFL76x6x/xx (Sundance)

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2011-Nov-04

EN 24

4.

Q552.2E LA

Mechanical Instructions

19104_058_110701.eps
110701

Figure 4-10 Cable dressing 37PFL76x6x/xx (Sundance)

2011-Nov-04

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Mechanical Instructions

Q552.2E LA

4.

EN 25

19104_059_110701.eps
110701

Figure 4-11 Cable dressing 42PFL74x6x/xx (Sundance)

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2011-Nov-04

EN 26

4.

Q552.2E LA

Mechanical Instructions

10000_000fullwide_090515.eps
091118

Figure 4-12 Cable dressing 47PFL74x6x/xx (Sundance)

2011-Nov-04

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Mechanical Instructions
4.4

Q552.2E LA

4.

EN 27

Cable Dressing Sundance Styling (xxPFL76x6x/xx series; WiFi)

19104_061_110701.eps
110701

Figure 4-13 Cable dressing 37PFL76x6x/xx (Sundance)

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2011-Nov-04

EN 28

4.

Q552.2E LA

Mechanical Instructions

19104_062_110701.eps
110701

Figure 4-14 Cable dressing 42PFL76x6x/xx (Sundance)

2011-Nov-04

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Mechanical Instructions

Q552.2E LA

4.

EN 29

19104_063_110701.eps
110701

Figure 4-15 Cable dressing 47PFL76x6x/xx (Sundance)

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2011-Nov-04

EN 30

4.

Q552.2E LA

Mechanical Instructions

19104_064_110701.eps
110701

Figure 4-16 Cable dressing 55PFL76x6x/xx (Sundance)

2011-Nov-04

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Mechanical Instructions
4.5

Q552.2E LA

4.

EN 31

Cable Dressing Infinity Styling (xxPDL79x6x/xx series)

19104_065_110701.eps
110701

Figure 4-17 Cable dressing 32PDL79x6x/xx (Infinity)

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2011-Nov-04

EN 32

4.

Q552.2E LA

Mechanical Instructions

19104_066_110701.eps
110701

Figure 4-18 Cable dressing 42PDL79x6x/xx (Infinity)

4.6

Service Positions
For easy servicing of a TV set, the set should be put face down
on a soft flat surface, foam buffers or other specific workshop
tools. Ensure that a stable situation is created to perform
measurements and alignments. When using foam bars take
care that these always support the cabinet and never only the
display. Caution: Failure to follow these guidelines can
seriously damage the display!
Ensure that ESD safe measures are taken.

2011-Nov-04

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Mechanical Instructions
4.7

Assy/Panel Removal Berlinale styling


(xxPFL5806K/xx)

4.

EN 33

Warning: Disconnect the mains power cord before removing


the rear cover.
1. Remove screw caps [1] that cover VESA screw holes.
2. Remove all fixation screws [2] that secure the rear cover.
3. At the indicated areas [3] the cover is secured by clips. Be
very careful with releasing those.
4. Lift the rear cover from the TV. Make sure that wires and
flat foils are not damaged while lifting the rear cover from
the set.

Instructions below apply to the 32PFL5606H/12, but will be


similar for other models.
4.7.1

Q552.2E LA

Rear Cover
Refer to Figure 4-19 for details.

2
1

3
3
2

19080_107_110401.eps
110407

Figure 4-19 Rear cover removal


4.7.2

4.7.3

Small Signal Board (SSB)

Power Supply Unit (PSU)


Caution: it is mandatory to remount all different screws at their
original position during re-assembly. Failure to do so may result
in damaging the PSU.
1. Release the tape from the Power board cables.
2. Unplug power connectors from the SSB, as it is not unplugable at the PSU itself (soldered connector).
3. Unplug both other connectors from the PSU.
4. Remove all fixation screws from the PSU.
5. The PSU can be taken out of the set now.
When defective, replace the whole unit.

Caution: it is mandatory to remount all different screws at their


original position during re-assembly. Failure to do so may result
in damaging the SSB.
1. Release the clips from both the LVDS Flat Foil connectors
that connect with the SSB.
Caution: be careful, as these are very fragile connectors!
Take the flat foils out of their connectors.
2. Unplug all other connectors.
3. Remove all fixation screws from the SSB. Note that one
screw is located below the upper flat foil cable.
4. Take out the SSB together with side and bottom I/O
bracket.
5. Remove the screws between the bottom Y-Pb and L-R
audio connectors.
6. Remove the side and bottom I/O bracket from the SSB.
Note that these parts are kept in place by very fragile clips.
Release those clips gently!

4.7.4

Stand removal
1. Remove the four fixation screws.
2. Take the stand out in a downwards direction.

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2011-Nov-04

EN 34
4.7.5

4.

Mechanical Instructions

Q552.2E LA

4.7.8

Stand bracket removal

Refer to Figure 4-22 for details.


1. Remove the stand bracket as described earlier.
2. Release the connectors [1] from the IR/LED/Keyboard.
3. Caution: The board is fitted to the bezel by double sided
tape!
4. Use the slot type screw driver to detach the IR/LED/
Keyboard from the bezel. Be careful not to damage the
bezel. Refer to Figure 4-22 for details.
5. Carefully remove any of the tape residue from the bezel.
When defective, replace the whole unit.

Refer to Figure 4-20 for details.


Caution: it is mandatory to remount all different screws at their
original position during re-assembly. Be sure to put the set in
the Service Position.
1. Remove the fixation screws [1], [2].
2. Take the Stand bracket out.
3. Take Cover leading edge out, be careful of the clips.

Stand bracket

IR/LED/Keyboard

19080_113_110402.eps
111103

Cover leading edge

Figure 4-22 IR/LED/Keyboard removal


Caution: The touch control function needs to be checked when
it is replaced.
1. Use test finger with a 8 mm diameter to touch centre of key
icon on front cover.
2. Press touch key sensitivity test hot key 0 6 2 5 9 0 MENU,
check the sensitivity count value of each key (CH +/-,
HOME, VOL +/-), when touching key icon on front cover.
Refer to Figure 4-23 for details.
3. The value count of each key should be over 100.

19080_108_110402.eps
110407

Figure 4-20 Stand bracket removal


4.7.6

Power switch and mains plug


Refer to Figure 4-21 for details.
1. Unplug the connector from the PSU.
2. The switch and mains inlet can be remove by simply lifting
them upwards out of their brackets.
3. The brackets can be removed by removing the fixation
screws [1] and take them out of the set.
When defective, replace the power switch and mains plug
assembly.

AC inlet cover

19080_116_110406.eps
111103

AC hand switch

Figure 4-23 Check touch control

19080_109_110402.eps
111103

Figure 4-21 Power switch and mains plug removal


4.7.7

Speakers
1. Unplug the left and right speaker connectors from the SSB.
2. Remove the Stand bracket as described earlier.
3. Remove the Power switch and mains plug as described
earlier.
4. Release tapes from the speaker cables.
5. Take the left and right speakers out.
When defective, replace the both units.

2011-Nov-04

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Mechanical Instructions
4.7.9

Q552.2E LA

4.

EN 35

LCD Panel
Refer to Figure 4-24 for details.
1. Remove the SSB as described earlier.
2. Remove the PSU as described earlier.
3. Remove the stand as described earlier.
4. Remove the stand bracket as described earlier.
5. Remove the Power switch and mains plug as described
earlier.
6. Remove the speakers as described earlier.
7. Release the tapes from the cables of the IR/KEY board.
8. Release the clips from both the LVDS flat
foil connectors [1].
Caution: be careful, as these are very fragile cables and
connectors! Take the flat foils out of their connectors.
9. Remove the fixation screws [2] at the top, sides and bottom
of the panel that secure the LCD panel with the bezel.
Remove all metal clips from their position. Be careful not to
break the clicks that secure by metal brackets to keep
those in position.
10. Lift the LCD Panel from the bezel.
When defective, replace the whole unit.

1
19100_048_110216.eps
110216

Figure 4-25 Bottom catches 40" and 46" Blockbuster sets -1-

2
2

2
2
2

19100_049_110216.eps
110216

Figure 4-26 Bottom catches 40" and 46" Blockbuster sets -2-

2
It is advised to lay the set with front facing down before
executing this operation.
1. Remove all screws from the rear cover.
2. Use a round rod (diameter 2 mm) and insert it in one of the
holes [1].
3. Push the catch located inside the rear cover away by
inserting the rod [2] through the hole and lifting the rear
cover at the same time.
4. Repeat the same procedure on the other hole.

19080_115_110402.eps
111103

Figure 4-24 LCD panel removal

4.8

Assy/Panel Removal Blockbuster Styling


(xxPFL6xxx/xx series)
4.8.2
For the 40" and 46" Blockbuster sets, additional instructions
(rear cover removal) apply. Refer to subsection Additional
instructions for Blockbuster 40-/46PFL6x06x/xx.

Speakers
Tweeters
Each tweeter unit is mounted with two screws.
When defective, replace the whole unit.

The instructions apply to the 37PFL6606H/12.


4.8.1

Subwoofer
The central subwoofer is located in the centre of the set and is
secured by two bosses.
When defective, replace the whole unit.

Rear Cover
Warning: Disconnect the mains power cord before you remove
the rear cover.
Note: it is not necessary to remove the stand while removing
the rear cover.

4.8.3

Mains Switch
Refer to Figure 4-35 for details.

1. Remove all screws of the rear cover.


2. Lift the rear cover from the TV. Make sure that wires and
flat coils are not damaged while lifting the rear cover from
the set.
Additional instructions for Blockbuster 40-/46PFL6x06x/xx
40"and 46"Blockbuster (40-/46PFL6606x/xx) sets have a
dedicated method to open the bottom catches when removing
the rear cover.
Refer to Figure 4-25 and Figure 4-26 for details.

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2011-Nov-04

EN 36

4.

Q552.2E LA

Mechanical Instructions

1
2

19100_047_110216.eps
110216

Figure 4-27 Mains switch


The mains switch is mounted on a plastic subframe and can be
removed without removing the subframe.
1. Use a screwdriver and push the switch out of its casing [1].
2. Unplug the connectors.
When defective, replace the whole unit.
4.8.4

19101_007_110407.eps
110407

Main Power Supply

Figure 4-29 SSB


1. Unplug all connectors [1].
2. Remove the fixation screws [2].
3. Take the board out.
When remounting, ensure that the side shielding is positioned
correctly.

Refer to Figure 4-36 for details.

2
19101_008_110407.eps
110407

Figure 4-28 Main Power Supply


1. Unplug all connectors [1].
2. Remove the fixation screws [2].
3. Take the board out.
When defective, replace the whole unit.
4.8.5

Small Signal Board (SSB)


Refer to Figure 4-37 for details.

2011-Nov-04

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Mechanical Instructions
4.8.6

Q552.2E LA

4.

EN 37

Keyboard Control, IR & LED Board


Refer to Figure 4-38 and Figure 4-39 for details.

1
2

19101_009_110407.eps
110407

Figure 4-30 Keyboard control, IR & LED board [1/2]

19101_006_110407.eps
110407

Figure 4-31 Keyboard control, IR & LED board [2/2]


1. Remove the stand [1].
2. Remove the stand subframe [2].
3. Remove the screws [3], unplug the connector and take the
board out.
When defective, replace the whole unit.

19101_005_110407.eps
110407

Figure 4-32 LCD panel [1/3]


6. Remove the mains switch subframe [2].
7. Remove the keyboard control-, and IR & LED board as
described earlier.
8. Remove all remaining cables and subframes.
9. Use a screwdriver to release the catches [3] that secure the
panel.

1. Remove the SSB as described earlier.


2. Remove the PSU as described earlier.
3. Remove the tweeters with their subframes and subwoofer
as described earlier.
4. Remove the stand and -subframe as described earlier.
5. Remove the cables [1].
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2011-Nov-04

EN 38

4.

Q552.2E LA

Mechanical Instructions
4.9.2

10. Use a screwdriver to release the catches and remove the


sidewings [4] that secure the panel.
11. Take the panel out.
Remove the clamps from the panel before sending the panel in
for Service.

Speakers
Tweeters
Each tweeter unit is mounted with one screw.
When defective, replace the whole unit.
Subwoofer
The central subwoofer is located in the centre of the set and is
secured by two bosses.
When defective, replace the whole unit.

3
4.9.3

Mains Switch
Refer to Figure 4-35 for details.

19101_004_110407.eps
110407

1
Figure 4-33 LCD panel [2/3]

19100_047_110216.eps
110216

Figure 4-35 Mains switch


The mains switch is mounted on a plastic subframe and can be
removed without removing the subframe.
1. Use a screwdriver and push the switch out of its casing [1].
2. Unplug the connectors.
When defective, replace the whole unit.

4.9.4

Main Power Supply


Refer to Figure 4-36 for details.

19101_003_110407.eps
110407

Figure 4-34 LCD panel [3/3]

4.9

Assy/Panel Removal Sundance Styling


(xxPFL7xxx/xx series)
The instructions apply to the 32PFL7406K/02.

2
4.9.1

Rear Cover

Warning: Disconnect the mains power cord before you remove


the rear cover.
Note: it is not necessary to remove the stand while removing
the rear cover.

19100_050_110216.eps
110216

Figure 4-36 Main Power Supply

1. Remove all screws of the rear cover.


2. Lift the rear cover from the TV. Make sure that wires and
flat coils are not damaged while lifting the rear cover from
the set.

2011-Nov-04

1. Unplug all connectors [1].


2. Remove the fixation screws [2].
3. Take the board out.
When defective, replace the whole unit.

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Mechanical Instructions
4.9.5

4.

EN 39

1. Remove the stand and the plastic support [1].


2. Unplug the connector [2].
3. Remove the screws [3] and take the board out.
When defective, replace the whole unit.

Small Signal Board (SSB)


Refer to Figure 4-37 for details.

4.9.7

Q552.2E LA

The Ambilight units can be lifted from the subframes without


the use of tools.
Refer to Figure 4-40 for details.

Ambilight Units

2
1
2

2
19100_051_110216.eps
110216

Figure 4-37 SSB


19100_054_110216.eps
110216

1. Unplug all connectors [1].


2. Remove the fixation screws [2].
3. Take the board out.
When remounting, ensure that the side shielding is positioned
correctly.
4.9.6

Figure 4-40 Ambilight units


1. Unplug the connector [1].
2. Carefully lift the board [2] and take the board out.
When defective, replace the whole unit.

Keyboard Control, IR & LED Board


Refer to Figure 4-38 and Figure 4-39 for details.

1
1

1
1

19100_052_110216.eps
110216

Figure 4-38 Keyboard control, IR & LED board [1/2]

19100_053_110216.eps
110216

Figure 4-39 Keyboard control, IR & LED board [2/2]


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2011-Nov-04

EN 40
4.9.8

4.

Q552.2E LA

Mechanical Instructions

LCD Panel
Refer to Figure 4-41 and Figure 4-42 for details.

2
2

1
4

19100_055_110216.eps
110216

Figure 4-41 LCD panel [1/2]


1. Remove the SSB as described earlier.
2. Remove the PSU as described earlier.
3. Remove the tweeters with their subframes and subwoofer
as described earlier.
4. Remove the stand and -support as described earlier.
5. Remove the cables [1].
6. Remove the stand subframe [2].
7. Remove the mains switch subframe [3].
8. Remove the Ambilight units together with their subframes
as described earlier.
9. Unplug the connector from the keyboard control-, and IR &
LED board as described earlier.
10. Remove all remaining cables and subframes.
11. Use a screwdriver to release the clamps [4] that secure the
panel and take the panel out.
Remove the clamps from the panel before sending the panel in
for Service.

4
19100_056_110217.eps
110217

Figure 4-42 LCD panel [2/2]

4.10 Assy/Panel Removal Infinity Styling


(xxPDL79xx/xx series)
The instructions apply to the 32PDL7906K/02.
4.10.1 Rear Cover
Warning: Disconnect the mains power cord before you remove
the rear cover.

2011-Nov-04

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Mechanical Instructions

Q552.2E LA

1. Remove all screws of the rear cover.


2. Lift the rear cover from the TV. Make sure that wires and
flat coils are not damaged while lifting the rear cover from
the set.

4.

EN 41

1
2

4.10.2 Speakers

Tweeters
Each tweeter unit is mounted with one screw.
When defective, replace the whole unit.

Subwoofer
The central subwoofer is located in the centre of the set and is
secured by two bosses.
When defective, replace the whole unit.

4.10.3 Mains Switch

Refer to Figure 4-43 for details.


19104_068_110701.eps
110701

Figure 4-44 Main Power Supply


1. Unplug all connectors [1].
2. Remove the fixation screws [2].
3. Take the board out.
When defective, replace the whole unit.
4.10.5 Small Signal Board (SSB)

Refer to Figure 4-45 for details.

19104_067_110701.eps
110701

Figure 4-43 Mains switch


The mains switch is mounted on a plastic subframe and can be
removed without removing the subframe.
1. Use a screwdriver and push the switch out of its casing [1].
2. Unplug the connectors.
When defective, replace the whole unit.

19104_069_110701.eps
110701

4.10.4 Main Power Supply


Refer to Figure 4-44 for details.

Figure 4-45 SSB


1. Unplug all connectors [1].
2. Remove the fixation screws [2].
3. Take the board out.
When remounting, ensure that the side shielding is positioned
correctly.

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2011-Nov-04

EN 42

4.

Q552.2E LA

Mechanical Instructions
4.10.9 Temperature Sensor Board

4.10.6 IR/LED Board

Refer to Figure 4-49 for details.

Refer to Figure 4-46 for details.

1
2
2
1
19104_070_110701.eps
110701

19104_074_110708.eps
110708

Figure 4-46 IR/LED board

Figure 4-49 Temperature Sensor board


1. Unplug the connector [1].
2. Remove the screw [2].
3. Take the board out together with the subframe.
When defective, replace the whole unit.

1. Remove the screw [1].


2. Unplug the connector [2].
3. Take the board out.
When defective, replace the whole unit.

4.10.7 Keyboard Control Board


4.10.10 Ambilight Units
Refer to Figure 4-47 for details.
The Ambilight units can be lifted from the subframes without
the use of tools.
Refer to Figure 4-50 for details.

2
1
19104_071_110701.eps
110701

Figure 4-47 Keyboard control board

1. Unplug the connector [1] from the IR/LED board, as


described earlier.
2. Release the tapes of the IR/LED cables.
3. Unplug the connector [1].
4. Remove the screws [2].
5. Take the board out together with the subframe.
When defective, replace the whole unit.

19100_054_110216.eps
110216

4.10.8 WiFi Board

Figure 4-50 Ambilight units

Refer to Figure 4-48 for details.

1. Unplug the connector [1].


2. Carefully lift the board [2] and take the board out.
When defective, replace the whole unit.

19104_072_110704.eps
110704

Figure 4-48 WiFi board


1. Remove the screw [1].
2. Unplug the connector [2].
3. Take the board out together with the subframe.
When defective, replace the whole unit.
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Mechanical Instructions

Q552.2E LA

4.

EN 43

4.10.11 LCD Panel


Refer to Figure 4-51 for details.

19104_073_110704.eps
110704

Figure 4-51 LCD panel

4.11 Set Re-assembly

1. Remove the SSB as described earlier.


2. Remove the PSU as described earlier.
3. Remove the tweeters with their subframes and subwoofer
as described earlier.
4. Remove all remaining cables.
5. Remove the stand support [1].
6. Remove the Ambilight units.
7. Remove the WiFi board as described earlier.
8. Remove the keyboard control-, and IR & LED board as
described earlier.
9. Remove all remaining cables and subframes.
10. Remove the adhesive tape on each corner [2].
11. Remove the clamps [3] that secure the panel and take the
panel out.

To re-assemble the whole set, execute all processes in reverse


order.
Notes:
While re-assembling, make sure that all cables are placed
and connected in their original position.
Pay special attention not to damage the EMC foams in the
set. Ensure that EMC foams are mounted correctly.

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2011-Nov-04

EN 44

5.

Q552.2E LA

Service Modes, Error Codes, and Fault Finding

5. Service Modes, Error Codes, and Fault Finding

Index of this chapter:


5.1 Test Points
5.2 Service Modes
5.3 Stepwise Start-up
5.4 Service Tools
5.5 Error Codes
5.6 The Blinking LED Procedure
5.7 Protections
5.8 Fault Finding and Repair Tips
5.9 Software Upgrading

5.1

How to Activate SDM


For this chassis there are two kinds of SDM: an analogue SDM
and a digital SDM. Tuning will happen according Table 5-1.
Analogue SDM: use the standard RC-transmitter and key
in the code 062596, directly followed by the MENU (or
HOME) button.
Note: It is possible that, together with the SDM, the main
menu will appear. To switch it off, push the MENU (or
"HOME") button again.
Analogue SDM can also be activated by grounding for a
moment the solder path on the SSB, with the indication
SDM (see Service mode pad).
Digital SDM: use the standard RC-transmitter and key in
the code 062593, directly followed by the MENU (or
"HOME") button.
Note: It is possible that, together with the SDM, the main
menu will appear. To switch it off, push the MENU (or
"HOME") button again.

Test Points
As most signals are digital, it will be difficult to measure
waveforms with a standard oscilloscope. However, several key
ICs are capable of generating test patterns, which can be
controlled via ComPair. In this way it is possible to determine
which part is defective.
Perform measurements under the following conditions:
Service Default Mode.
Video: Colour bar signal.
Audio: 3 kHz left, 1 kHz right.

5.2

All picture settings at 50% (brightness, colour, contrast).


Sound volume at 25%.
All service-unfriendly modes (if present) are disabled, like:
(Sleep) timer.
Child/parental lock.
Picture mute (blue mute or black mute).
Automatic volume levelling (AVL).
Skip/blank of non-favourite pre-sets.

Service Modes
Service Default mode (SDM) and Service Alignment Mode
(SAM) offers several features for the service technician, while
the Customer Service Mode (CSM) is used for communication
between the call centre and the customer.
This chassis also offers the option of using ComPair, a
hardware interface between a computer and the TV chassis. It
offers the abilities of structured troubleshooting, error code
reading, and software version read-out for all chassis.
(see also section 5.4.1 ComPair).

SDM

Note: For the new model range, a new remote control (RC) is
used with some renamed buttons. This has an impact on the
activation of the Service modes. For instance the old MENU
button is now called HOME (or is indicated by a house icon).
5.2.1

19100_057_110217.eps
110217

Figure 5-1 Service mode pad

Service Default Mode (SDM)

After activating this mode, SDM will appear in the upper right
corner of the screen (when a picture is available).

Purpose
To create a pre-defined setting, to get the same
measurement results as given in this manual.
To override software protections detected by stand-by
processor and make the TV start up to the step just before
protection (a sort of automatic stepwise start-up). See
section 5.3 Stepwise Start-up.
To start the blinking LED procedure where only LAYER 2
errors are displayed. (see also section 5.5 Error Codes).

How to Navigate
When the MENU (or HOME) button is pressed on the RC
transmitter, the TV set will toggle between the SDM and the
normal user menu.
How to Exit SDM
Use one of the following methods:
Switch the set to STAND-BY via the RC-transmitter.
Via a standard customer RC-transmitter: key in 00sequence.

Specifications
Table 5-1 SDM default settings
Region

Freq. (MHz)

Europe, AP(PAL/Multi) 475.25


Europe, AP DVB-T

5.2.2
Default system

Service Alignment Mode (SAM)


Purpose
To perform (software) alignments.
To change option settings.
To easily identify the used software version.
To view operation hours.
To display (or clear) the error code buffer.

PAL B/G

DVB-T
546.00 PID
Video: 0B 06 PID
PCR: 0B 06 PID
Audio: 0B 07

How to Activate SAM


Via a standard RC transmitter: Key in the code 062596
directly followed by the INFO or OK button. After activating
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Service Modes, Error Codes, and Fault Finding

Q552.2E LA

5.

EN 45

SAM with this method a service warning will appear on the


screen, continue by pressing the OK button on the RC.
Contents of SAM
Hardware Info.
A. SW Version. Displays the software version of the
main software (example: Q555X-1.2.3.4 =
AAAAB_X.Y.W.Z).
AAAA= the chassis name.
B= the software branch version. This is a
sequential number (this is no longer the region
indication, as the software is now multi-region).
X.Y.W.Z= the software version, where X is the
main version number (different numbers are not
compatible with one another) and Y.W.Z is the sub
version number (a higher number is always
compatible with a lower number).
B. STBY PROC Version. Displays the software
version of the stand-by processor.
C. Production Code. Displays the production code of
the TV, this is the serial number as printed on the back
of the TV set. Note that if an NVM is replaced or is
initialized after corruption, this production code has to
be re-written to NVM. ComPair will foresee in a
possibility to do this.
Operation Hours. Displays the accumulated total of
operation hours (not the stand-by hours). Every time the
TV is switched on/off, 0.5 hours is added to this number.
Errors (followed by maximum 10 errors). The most recent
error is displayed at the upper left (for an error explanation
see section 5.5 Error Codes).
Reset Error Buffer. When cursor right (or OK button)
pressed here, followed by the OK button, the error buffer
is reset.
Alignments. This will activate the ALIGNMENTS submenu. See Chapter 6. Alignments.
Dealer Options. Extra features for the dealers.
Options. Extra features for Service. For more info
regarding option codes, see chapter 6. Alignments.
Note that if the option code numbers are changed, these
have to be confirmed with pressing the OK button before
the options are stored, otherwise changes will be lost.
Initialize NVM. The moment the processor recognizes a
corrupted NVM, the initialize NVM line will be highlighted.
Now, two things can be done (dependent of the service
instructions at that moment):
Save the content of the NVM via ComPair for
development analysis, before initializing. This will give
the Service department an extra possibility for
diagnosis (e.g. when Development asks for this).
Initialize the NVM.

Display Option
Code

39mm

27mm

PHILIPS

040

MODEL:
32PF9968/10
PROD.SERIAL NO:
AG 1A0620 000001

(CTN Sticker)

10000_038_090121.eps
090819

Figure 5-2 Location of Display Option Code sticker

Note: When the NVM is corrupted, or replaced, there is a high


possibility that no picture appears because the display code is
not correct. So, before initializing the NVM via the SAM, a
picture is necessary and therefore the correct display option
has to be entered. Refer to Chapter 6. Alignments for details.
To adapt this option, its advised to use ComPair (the correct
values for the options can be found in Chapter 6. Alignments)
or a method via a standard RC (described below).
Changing the display option via a standard RC: Key in the
code 062598 directly followed by the MENU (or "HOME")
button and XXX (where XXX is the 3 digit decimal display
code as mentioned on the sticker in the set). Make sure to key
in all three digits, also the leading zeros. If the above action is
successful, the front LED will go out as an indication that the
RC sequence was correct. After the display option is changed
in the NVM, the TV will go to the Stand-by mode. If the NVM
was corrupted or empty before this action, it will be initialized
first (loaded with default values). This initializing can take up to
20 seconds.

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Store - go right. All options and alignments are stored


when pressing cursor right (or the OK button) and then
the OK-button.
Operation hours display. Displays the accumulated total
of operation hours of the screen itself. In case of a display
replacement, reset to 0 or to the consumed operation
hours of the spare display.
SW Maintenance.
SW Events. In case of specific software problems, the
development department can ask for this info.
HW Events. In case of specific software problems, the
development department can ask for this info :
- Event 26: refers to a power dip, this is logged after
the TV set reboots due to a power dip.
- Event 17: refers to the power OK status, sensed even
before the 3 x retry to generate the error code.
Test settings. For development purposes only.
Development file versions. Not useful for Service
purposes, this information is only used by the development
department.
Upload to USB. To upload several settings from the TV to
an USB stick, which is connected to the SSB. The items are
Channel list, Personal settings, Option codes,
Alignments, Identification data (includes the set type
and prod code + all 12NC like SSB, display, boards),
History list. The All item supports to upload all several
items at once.
First a directory repair\ has to be created in the root
of the USB stick.
To upload the settings, select each item separately, press
cursor right (or the OK button), confirm with OK and
wait until the message Done appears. In case the
download to the USB stick was not successful, Failure will
be displayed. In this case, check if the USB stick is
connected properly and if the directory repair is present in
the root of the USB stick. Now the settings are stored onto
the USB stick and can be used to download into another TV
or other SSB. Uploading is of course only possible if the
software is running and preferably a picture is available.
This method is created to be able to save the customers
TV settings and to store them into another SSB.
Download from USB. To download several settings from
the USB stick to the TV, same way of working needs to be
followed as described in Upload to USB. To make sure
that the download of the channel list from USB to the TV is
executed properly, it is necessary to restart the TV and
tune to a valid preset if necessary. The All item supports
to download all several items at once.
NVM editor. For NET TV the set type number must be
entered correctly.
Also the production code (AG code) can be entered here
via the RC-transmitter.
Correct data can be found on the side/rear sticker.

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5.

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Service Modes, Error Codes, and Fault Finding


How to Navigate
By means of the CURSOR-DOWN/UP knob on the RCtransmitter, can be navigated through the menus.

How to Navigate
In SAM, the menu items can be selected with the
CURSOR UP/DOWN key on the RC-transmitter. The
selected item will be highlighted. When not all menu items
fit on the screen, move the CURSOR UP/DOWN key to
display the next/previous menu items.
With the CURSOR LEFT/RIGHT keys, it is possible to:
(De) activate the selected menu item.
(De) activate the selected sub menu.
With the OK key, it is possible to activate the selected
action.

Contents of CSM
The contents are reduced to 3 pages: General, Software
versions and Quality items. The group names itself are not
shown anywhere in the CSM menu.
General
Set Type. This information is very helpful for a helpdesk/
workshop as reference for further diagnosis. In this way, it
is not necessary for the customer to look at the rear of the
TV-set. Note that if an NVM is replaced or is initialized after
corruption, this set type has to be re-written to NVM.
ComPair will foresee in a possibility to do this. The update
can also be done via the NVM editor available in SAM.
Production Code. Displays the production code (the serial
number) of the TV. Note that if an NVM is replaced or is
initialized after corruption, this production code has to be
re-written to NVM. ComPair will foresee in a possibility to
do this. The update can also be done via the NVM editor
available in SAM.
Installed date. Indicates the date of the first installation of
the TV. This date is acquired via time extraction.
Options 1. Gives the option codes of option group 1 as set
in SAM (Service Alignment Mode).
Options 2. Gives the option codes of option group 2 as set
in SAM (Service Alignment Mode).
12NC SSB. Gives an identification of the SSB as stored in
NVM. Note that if an NVM is replaced or is initialized after
corruption, this identification number has to be re-written to
NVM. ComPair will foresee in a possibility to do this. This
identification number is the 12nc number of the SSB.
12NC display. Shows the 12NC of the display.
12NC supply. Shows the 12NC of the power supply.
12NC 200Hz board. Shows the 12NC of the 200Hz Panel
(when present).
12NC AV PIP. Shows the 12NC of the AV PIP board
(when present).

How to Exit SAM


Use one of the following methods:
Switch the TV set to STAND-BY via the RC-transmitter.
Via a standard RC-transmitter, key in 00 sequence, or
select the BACK key.
5.2.3

Customer Service Mode (CSM)


Purpose
When a customer is having problems with his TV-set, he can
call his dealer or the Customer Helpdesk. The service
technician can then ask the customer to activate the CSM, in
order to identify the status of the set. Now, the service
technician can judge the severity of the complaint. In many
cases, he can advise the customer how to solve the problem,
or he can decide if it is necessary to visit the customer.
The CSM is a read only mode; therefore, modifications in this
mode are not possible.
When in this chassis CSM is activated, a test pattern will be
displayed during 5 seconds (1 second Blue, 1 second Green
and 1 second Red, then again 1 second Blue and 1 second
Green). This test pattern is generated by the PNX51X0
(located on the 200Hz board as part of the display). So if this
test pattern is shown, it could be determined that the back end
video chain (PNX51X0 and display) is working.For TV sets
without the PNX51X0 inside, every menu from CSM will be
used as check for the back end chain video.

Software versions
Current main SW. Displays the build-in main software
version. In case of field problems related to software,
software can be upgraded. As this software is consumer
upgradeable, it will also be published on the Internet.
Example: Q55xx1.2.3.4
Stand-by SW. Displays the build-in stand-by processor
software version. Upgrading this software will be possible
via ComPair or via USB (see section 5.9 Software
Upgrading).
Example: STDBY_83.84.0.0.
e-UM version. Displays the electronic user manual
software-version (12NC version number). Most significant
number here is the last digit.
AV PIP software.
3D dongle software version.

When CSM is activated and there is a USB stick connected to


the TV set, the software will dump the CSM content to the USB
stick. The file (CSM_model number_serial number.txt) will be
saved in the root of the USB stick. This info can be handy if no
information is displayed.
When in CSM mode (and a USB stick connected), pressing
OK will create an extended CSM dump file on the USB stick.
This file (Extended_CSM_model number_serial number.txt)
contains:
The normal CSM dump information,
All items (from SAM load to USB, but in readable format),
Operating hours,
Error codes,
Software/Hardware event logs.
To have fast feedback from the field, a flashdump can be
requested by development. When in CSM, push the red
button and key in serial digits 2679 (same keys to form the
word COPY with a cellphone). A file Dump_model
number_serial number.bin will be written on the connected
USB device. This can take 1/2 minute, depending on the
quantity of data that needs to be dumped.

Quality items
Signal quality. Bad / average /good (not for DVB-S).
Ethernet MAC address. Displays the MAC address
present in the SSB.
Wireless MAC address. Displays the wireless MAC
address to support the Wi-Fi functionality.
BDS key. Indicates if the set is in the BDS status.
CI module. Displays status if the common interface
module is detected.
CI + protected service. Yes/No.
Event counter :
S : 000X 0000(number of software recoveries : SW
EVENT-LOG #(reboots)

Also when CSM is activated, the LAYER 1 error is displayed via


blinking LED. Only the latest error is displayed (see also
section 5.5 Error Codes).
How to Activate CSM
Key in the code 123654 via the standard RC transmitter.
Note: Activation of the CSM is only possible if there is no (user)
menu on the screen!
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Service Modes, Error Codes, and Fault Finding


5.3

S : 0000 000X (number of software events : SW EVENTLOG #(events)


H : 000X 0000(number of hardware errors)
H : 0000 000X (number of hardware events : SW EVENTLOG #(events).

EN 47

When the TV is in a protection state due to an error detected by


stand-by software (error blinking is displayed) and SDM is
activated via shortcutting the SDM solder path on the SSB, the
TV starts up until it reaches the situation just before protection.
So, this is a kind of automatic stepwise start-up. In combination
with the start-up diagrams below, you can see which supplies
are present at a certain moment. Caution: in case the start-up
in this mode with a faulty FET 7U0X is done, you can destroy
all ICs supplied by the +1V8 and +1v1, due to overvoltage (12V
on XVX-line). It is recommended to measure first the FET
7U0X or others FETs on shortcircuit before activating SDM via
the service pads.

Hotel mode
Notes: (only applicable to xxHFLxxxxX/nn)
Refer to the user manual for more information on the hotel
mode.
When in the hotel mode, the service modes CSM, SDM,
SAM and ComPair are automatically disabled (this is to
prevent hotel guests entering Philips service modes).
In order to use the service modes and ComPair, hotel
mode must be disabled.
To enable the hotel mode, Press the following key
sequence on the remote control transmitter: 3 1 9 7 5 3
MUTE.

The abbreviations SP and MP in the figures stand for:


SP: protection or error detected by the Stand-by
Processor.
MP: protection or error detected by the MIPS Main
Processor.

Mains
off

Mains
on

- WakeUp requested
- Acquisition needed
- Tact switch pushed

St by

5.

Stepwise Start-up

How to Exit CSM


Press MENU (or "HOME") / Back key on the RC-transmitter.
5.2.4

Q552.2E LA

WakeUp
requested

Semi
St by

- stby requested and


no data Acquisition
required

Active
- St by requested
- tact SW pushed

Tact switch
pushed

Hibernate

WakeUp
requested
(SDM)

- Tact switch pushed


- last status is hibernate
after mains ON

GoToProtection
GoToProtection

Protection

18770_250_100216.eps
100402

Figure 5-3 Transition diagram


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2011-Nov-04

EN 48

5.

Service Modes, Error Codes, and Fault Finding

Q552.2E LA

Off
Stand by or
Protection

Mains is applied

Standby Supply starts running.


All standby supply voltages become available.

st-by P resets

If the protection state was left by short circuiting the


SDM pins, detection of a protection condition during
startup will stall the startup. Protection conditions in a
playing set will be ignored. The protection mode will
not be entered.

Initialise I/O pins of the st-by P:


- Switch reset-AVC LOW (reset state)
- Switch reset-system LOW (reset state)
- Switch reset-Ethernet LOW (reset state)
- Switch reset-USB LOW (reset state)
- Switch reset-DVBs LOW (reset state)
- keep Audio-reset and Audio-Mute-Up HIGH

- Switch Audio-Reset high.


It is low in the standby mode if the standby
mode lasted longer than 10s.

start keyboard scanning, RC detection. Wake up reasons are


off.

Switch ON Platform and display supply by switching


LOW the Standby line.

+12V, +24Vs, AL and Bolt-on power


is switched on, followed by the +1V2 DCDC converter
Detect2 is moved to an interrupt. To be checked if
the detection on interrupt base is feasible or not or if
we should stick to the standard 40ms interval.

Detect2 high received


within 2 seconds?

Yes

12V error:
Layer1: 3
Layer2: 16

No

Enter protection

Enable the DCDC converters


(ENABLE-3V3n LOW)

Wait 50ms

Enable the supply detection algorithm

Set IC slave address


of Standby P to (A0h)

Detect EJTAG debug probe


(pulling pin of the probe interface to
ground by inserting EJTAG probe)

An EJTAG probe (e.g. WindPower ICE probe) can be


connected for Linux Kernel debugging purposes.

EJTAG probe
connected ?

Yes

No
No

No

Cold boot?

Yes
Release AVC system reset
Feed warm boot script

Release AVC system reset


Feed cold boot script

Release AVC system reset


Feed initializing boot script
disable alive mechanism

18770_251_100216.eps
100216

Figure 5-4 Off to Semi Stand-by flowchart (part 1)

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Service Modes, Error Codes, and Fault Finding

Q552.2E LA

5.

Reset-system is switched HIGH by the


AVC at the end of the bootscript

Reset-system is switched HIGH by the


AVC at the end of the bootscript

AVC releases Reset-Ethernet, Reset-USB and


Reset-DVBs when the end of the AVC bootscript is detected

AVC releases Reset-Ethernet, Reset-USB and


Reset-DVBs when the end of the AVC bootscript is detected

Reset-Audio and Audio-Mute-Up are


switched by MIPS code later on in the
startup process

Reset-Audio and Audio-Mute-Up are


switched by MIPS code later on in the
startup process

EN 49

No

This cannot be done through the bootscript,


the I/O is on the standby P

Timing need to be updated if


more mature info is available.

Bootscript ready
in 1250 ms?

No

Yes
Set IC slave address
of Standby P to (60h)

RPC start (comm. protocol)


Timing needs to
be updated if more
mature info is
available.

Flash to Ram
image transfer succeeded
within 30s?

No
Code =
Layer1: 2
Layer2: 15

Yes

Switch AVC PNX85500 in


reset (active low)

Code =
Layer1: 2
Layer2: 53

No

SW initialization
succeeded
within 20s?

Wait 10ms

Timing needs to be
updated if more
mature info is
available.

Yes

Enable Alive check mechanism


Disable all supply related protections and
switch off the +3V3 +5V DC/DC converter.
MIPS reads the wake up reason
from standby P.

Wait until AVC starts to


communicate

Wait 5ms

switch off the remaining DC/DC


converters

3-th try?

Startup screen shall only be visible when there is a coldboot to


an active state end situation. The startup screen shall not be
visible when waking up for reboot reasons or waking up to semistandby conditions or waking up to enter Hibernate mode..

Wake up reason
coldboot & not semistandby?
yes

Switch Standby I/O line high


and wait 4 seconds

The first time after the option turn on of the startup screen or
when the set is virgin, the cfg file is not present and hence
the startup screen will not be shown.

Startup screen cfg file


present?

Yes

yes

Blink Code as
error code

200Hz set?

yes

No

Enter protection

85500 sends out startup screen

85500 sends out startup screen

85500 starts up the display.

200Hz Tcon has started up the


display.

Startup screen visible

85500 requests Lamp on

No

No
To keep this flowchart readable, the exact
display turn on description is not copied
here. Please see the Semi-standby to On
description for the detailed display startup
During the complete display time of the
Startup screen, the preheat condition of
sequence.
100% PWM is valid.

Startup screen visible

Initialize audio
initialize tuner and channel decoders
Initialize source selection
Initialize video processing ICs

initialize AutoTV by triggering CHS AutoTV Init interface


Initialize Ambilight with Lights off.

Semi-Standby
18770_252_100216.eps
100216

Figure 5-5 Off to Semi Stand-by flowchart (part 2)

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Service Modes, Error Codes, and Fault Finding

Constraints taken into account:


- Display may only be started when valid LVDS output clock can be delivered by the AVC.
- To have a reliable operation of the EEFL backlight, the backlight should be driven with a maximum PWM duty
cycle during the first seconds. Only after this first one or two seconds, the PWM may be set to the required output
level (Note that the PWM output should be present before the backlight is switched on). To minimize the artefacts,
the picture should only be unblanked after these first seconds.

Semi Standby

The assumption here is that a fast toggle (<2s) can


only happen during ON->SEMI ->ON. In these states,
the AVC is still active and can provide the 2s delay. A
transition ON->SEMI->STBY->SEMI->ON cannot be
made in less than 2s, because the standby state will
be maintained for at least 4s.

Wait until previous on-state is left more than 2


seconds ago. (to prevent LCD display problems)

Assert RGB video blanking


and audio mute

CPipe already generates a valid output


clock in the semi-standby state: display
startup can start immediately when leaving
the semi-standby state.

Display already on?


(splash screen)
No

Switch on the display power by


switching LCD-PWR-ON low

The exact timings to


switch on the
display (LVDS
delay, lamp delay)
are defined in the
display file.

Yes
Wait x ms
Initialize audio and video
processing IC's and functions
according needed use case.

Switch on LVDS output in the 85500


Delay Lamp-on with the sum of the LVDS delay and
the Lamp delay indicated in the display file

Switch off the dimming backlight feature, set


the BOOST control to nominal and make sure
PWM output is set to maximum allowed PWM

Switch on LCD backlight (Lamp-ON)

Start POK line


detection algorithm

Wait until valid and stable audio and video, corresponding to the
requested output is delivered by the AVC
AND
the backlight has been switched on for at least the time which is
indicated in the display file as preheat time.

return

Switch Audio-Reset low and wait 5ms


A LED set does not normally need a
preheat time. The preheat remains present
but is set to zero in the display file.

Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)

Restore dimming backlight feature, PWM and BOOST output


and unblank the video.

The higher level requirement is that audio and video


should be demuted without transient effects and that
the audio should be demuted maximum 1s before or
at the same time as the unblanking of the video.

Switch on the Ambilight functionality according the last status


settings.

Startup screen Option


and Installation setting
Photoscreen ON?
Yes
Display cfg file present
and up to date, according
correct display option?
No
No
Yes
Prepare Start screen Display config
file and copy to Flash

Active
18770_253_100216.eps
100216

Figure 5-6 Semi Stand-by to Active flowchart (EEFL or LED backlight 50/100 Hz only)

2011-Nov-04

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div. table

Service Modes, Error Codes, and Fault Finding

The assumption here is that a fast toggle (<2s)


can only happen during ON->SEMI ->ON. In
these states, the AVC is still active and can
provide the 2s delay. If the transition ON->SEMI>STBY->SEMI->ON can be made in less than 2s,
we have to delay the semi -> stby transition until
the requirement is met.

Q552.2E LA

5.

EN 51

Semi Standby
Wait until previous on-state is left more than 2
seconds ago. (to prevent LCD display problems)

Assert RGB video blanking


and audio mute

There is no need to define the


display timings since the timing
implementation is part of the Tcon.

Backlight already on?


(splash screen)
Yes
Initialize audio and video
processing IC's and functions
according needed use case.

No
Request Tcon to Switch on the backlight in a
direct LED or
set Lamp-on I/O line in case of a side LED

Start POK line


detection algorithm
Wait until valid and stable audio and video, corresponding to
the requested output is delivered by the AVC.
return
Switch Audio-Reset low and wait 5ms

The higher level requirement is that audio and


video should be demuted without transient
effects and that the audio should be demuted
maximum 1s before or at the same time as the
unblanking of the video.

Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)

unblank the video.

Switch on the Ambilight functionality according the last status


settings.

Startup screen Option


and Installation setting
Photoscreen ON?
Yes
Display cfg file present
and up to date, according
correct display option?
No
No
Yes
Prepare Start screen Display config
file and copy to Flash

Active
18770_254_100216.eps
100216

Figure 5-7 Semi Stand-by to Active flowchart (LED backlight 200 Hz)

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div. table

2011-Nov-04

EN 52

5.

Q552.2E LA

Service Modes, Error Codes, and Fault Finding

Active
Mute all sound outputs via softmute

Wait 100ms

Set main amplifier mute (I/O: audio-mute)

Force ext audio outputs to ground


(I/O: audio reset)
And wait 5ms

switch off Ambilight

Wait until Ambilight has faded out: Output power


Observer should be zero

Switch off POK line


detection algorithm

switch off LCD backlight


(I/O or IC)

Mute all video outputs

Yes

200Hz set?

No

Wait x ms (display file)


Instruct 200Hz
Tcon to turn off
the display

Switch off LVDS output in 85500

Wait x ms

The exact timings to


switch off the
display (LVDS
delay, lamp delay)
are defined in the
display file.

Switch off the display power by


switching LCD-PWR-ON high

Semi Standby
18770_255_100216.eps
100216

Figure 5-8 Active to Semi Stand-by flowchart

2011-Nov-04

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div. table

Service Modes, Error Codes, and Fault Finding

Q552.2E LA

5.

EN 53

Semi Stand by

If ambientlight functionality was used in semi-standby


(lampadaire mode), switch off ambient light (see CHS
ambilight)

Delay transition until ramping down of ambient light is


finished. *)

*) If this is not performed and the set is


switched to standby when the switch off of
the ambilights is still ongoing, the lights will
switch off abruptly when the supply is cut.

transfer Wake up reasons to the Stand by P.

Switch Memories to self-refresh (this creates a more


stable condition when switching off the power).

Switch AVC system in reset state (reset-system and


reset-AVC lines)
Switch reset-USB, Reset-Ethernet and Reset-DVBs
LOW

Wait 10ms

Disable all supply related protections and switch off


the DC/DC converters (ENABLE-3V3n)

Wait 5ms

Switch OFF all supplies by switching HIGH the


Standby I/O line

Important remarks:
release reset audio 10 sec after entering
standby to save power
Also here, the standby state has to be
maintained for at least 4s before starting
another state transition.

Stand by
18770_256_100216.eps
100216

Figure 5-9 Semi Stand-by to Stand-by flowchart

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div. table

2011-Nov-04

EN 54

5.

Service Modes, Error Codes, and Fault Finding

Q552.2E LA

5.4

Service Tools

5.5

Error Codes

5.4.1

ComPair

5.5.1

Introduction

Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips
Consumer Electronics products. and offers the following:
1. ComPair helps to quickly get an understanding on how to
repair the chassis in a short and effective way.
2. ComPair allows very detailed diagnostics and is therefore
capable of accurately indicating problem areas. No
knowledge on I2C or UART commands is necessary,
because ComPair takes care of this.
3. ComPair speeds up the repair time since it can
automatically communicate with the chassis (when the P
is working) and all repair information is directly available.
4. ComPair features TV software up possibilities.

The error code buffer contains all detected errors since the last
time the buffer was erased. The buffer is written from left to
right, new errors are logged at the left side, and all other errors
shift one position to the right.
When an error occurs, it is added to the list of errors, provided
the list is not full. When an error occurs and the error buffer is
full, then the new error is not added, and the error buffer stays
intact (history is maintained).
To prevent that an occasional error stays in the list forever, the
error is removed from the list after more than 50 hrs. of
operation.
When multiple errors occur (errors occurred within a short time
span), there is a high probability that there is some relation
between them.

Specifications
ComPair consists of a Windows based fault finding program
and an interface box between PC and the (defective) product.
The ComPair II interface box is connected to the PC via an
USB cable. For the TV chassis, the ComPair interface box and
the TV communicate via a bi-directional cable via the service
connector(s).
The ComPair fault finding program is able to determine the
problem of the defective television, by a combination of
automatic diagnostics and an interactive question/answer
procedure.

New in this chassis is the way errors can be displayed:

How to Connect
This is described in the chassis fault finding database in
ComPair.

TO TV
TO
UART SERVICE
CONNECTOR

ComPair II
RC in

RC out

TO
I2C SERVICE
CONNECTOR

TO
UART SERVICE
CONNECTOR

Multi
function

Optional Power Link/ Mode


Switch
Activity

I2C

RS232 /UART

If no errors are there, the LED should not blink at all in


CSM or SDM. No spacer must be displayed as well.
There is a simple blinking LED procedure for board
level repair (home repair) so called LAYER 1 errors
next to the existing errors which are LAYER 2 errors (see
Table 5-2).
LAYER 1 errors are one digit errors.
LAYER 2 errors are 2 digit errors.
In protection mode.
From consumer mode: LAYER 1.
From SDM mode: LAYER 2.
Fatal errors, if I2C bus is blocked and the set reboots,
CSM and SAM are not selectable.
From consumer mode: LAYER 1.
From SDM mode: LAYER 2.
In CSM mode.
When entering CSM: error LAYER 1 will be displayed
by blinking LED. Only the latest error is shown.
In SDM mode.
When SDM is entered via Remote Control code or the
hardware pins, LAYER 2 is displayed via blinking LED.
Error display on screen.
In CSM no error codes are displayed on screen.
In SAM the complete error list is shown.

PC

Basically there are three kinds of errors:


Errors detected by the Stand-by software which lead to
protection. These errors will always lead to protection and
an automatic start of the blinking LED LAYER 1 error.
(see section 5.6 The Blinking LED Procedure).
Errors detected by the Stand-by software which not
lead to protection. In this case the front LED should blink
the involved error. See also section 5.5 Error Codes, 5.5.4
Error Buffer. Note that it can take up several minutes
before the TV starts blinking the error (e.g. LAYER 1
error = 2, LAYER 2 error = 15 or 53).
Errors detected by main software (MIPS). In this case
the error will be logged into the error buffer and can be read
out via ComPair, via blinking LED method LAYER 1-2
error, or in case picture is visible, via SAM.

ComPair II Developed by Philips Brugge

HDMI
I2C only

Optional power
5V DC

10000_036_090121.eps
091118

Figure 5-10 ComPair II interface connection


Caution: It is compulsory to connect the TV to the PC as
shown in the picture above (with the ComPair interface in
between), as the ComPair interface acts as a level shifter. If
one connects the TV directly to the PC (via UART), ICs can be
blown!

5.5.2

Use one of the following methods:


On screen via the SAM (only when a picture is visible).
E.g.:
00 00 00 00 00: No errors detected
23 00 00 00 00: Error code 23 is the last and only
detected error.
37 23 00 00 00: Error code 23 was first detected and
error code 37 is the last detected error.
Note that no protection errors can be logged in the
error buffer.

How to Order
ComPair II order codes:
ComPair II interface: 3122 785 91020.
Software is available via the Philips Service web portal.
ComPair UART interface cable for Q55x.x.
(using 3.5 mm Mini Jack connector): 3138 188 75051.
Note: When you encounter problems, contact your local
support desk.
2011-Nov-04

How to Read the Error Buffer

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Service Modes, Error Codes, and Fault Finding

5.5.3

5.

EN 55

content, as this history can give significant information). This to


ensure that old error codes are no longer present.
If possible, check the entire contents of the error buffer. In
some situations, an error code is only the result of another error
code and not the actual cause (e.g. a fault in the protection
detection circuitry can also lead to a protection).
There are several mechanisms of error detection:
Via error bits in the status registers of ICs.
Via polling on I/O pins going to the stand-by processor.
Via sensing of analog values on the stand-by processor or
the PNX8550.
Via a not acknowledge of an I2C communication.

Via the blinking LED procedure. See section 5.5.3 How to


Clear the Error Buffer.
Via ComPair.

How to Clear the Error Buffer


Use one of the following methods:
By activation of the RESET ERROR BUFFER command
in the SAM menu.
If the content of the error buffer has not changed for 50+
hours, it resets automatically.

5.5.4

Q552.2E LA

Error Buffer

Take notice that some errors need several minutes before they
start blinking or before they will be logged. So in case of
problems wait 2 minutes from start-up onwards, and then
check if the front LED is blinking or if an error is logged.

In case of non-intermittent faults, clear the error buffer before


starting to repair (before clearing the buffer, write down the
Table 5-2 Error code overview

Description

Monitored Error/ Error Buffer/


Layer 1 Layer 2 by
Prot Blinking LED Device

Defective Board

I2C3

13

MIPS

BL / EB

SSB

SSB

I2C2

14

MIPS

BL / EB

SSB

SSB

I2C4

18

MIPS

BL / EB

SSB

SSB

PNX doesnt boot (HW cause) 2

15

Stby P

BL

PNX8550

SSB

12V

16

Stby P

BL

Supply

Inverter or display supply

17

MIPS

EB

Supply

PNX51X0

2/9

21

MIPS

EB

PNX51X0

200 Hz board

HDMI mux

23

MIPS

EB

Sil9x87A

SSB

I2C switch

24

MIPS

EB

PCA9540

SSB

Channel dec DVB-S

28

MIPS

EB

STV0903

SSB

Lnb controller

31

MIPS

EB

LNBH23

SSB

Tuner

34

MIPS

EB

DTT 71300

SSB

Main nvm

35

MIPS

EB

STM24C64

SSB

Tuner DVB-S

36

MIPS

EB

STV6110

SSB

T sensor SSB/set

42

MIPS

EB

LM 75

T sensor

T sensor LED driver/Tcon

42

MIPS

EB

LM 75

T sensor

PNX doesnt boot (SW cause) 2

53

Stby P

BL

PNX8550

SSB

Display

64

MIPS

BL / EB

Altera

Display

Extra Info
Rebooting. When a TV is constantly rebooting due to
internal problems, most of the time no errors will be logged
or blinked. This rebooting can be recognized via a ComPair
interface and Hyperterminal (for Hyperterminal settings,
see section 5.8 Fault Finding and Repair Tips, 5.8.7
Logging). Its shown that the loggings which are generated
by the main software keep continuing. In this case
diagnose has to be done via ComPair.
Error 13 (I2C bus 3, SSB bus blocked). Current situation:
when this error occurs, the TV will constantly reboot due to
the blocked bus. The best way for further diagnosis here, is
to use ComPair.
Error 14 (I2C bus 2, TV set bus blocked). Current
situation: when this error occurs, the TV will constantly
reboot due to the blocked bus. The best way for further
diagnosis here, is to use ComPair.
Error 18 (I2C bus 4, Tuner bus blocked). In case this bus
is blocked, short the SDM solder paths on the SSB during
startup, LAYER error 2 = 18 will be blinked.
Error 15 (PNX8550 doesnt boot). Indicates that the main
processor was not able to read his bootscript. This error will
point to a hardware problem around the PNX8550
(supplies not OK, PNX 8550 completely dead, I2C link
between PNX and Stand-by Processor broken, etc...).
When error 15 occurs it is also possible that I2C1 bus is
blocked (NVM). I2C1 can be indicated in the schematics as
follows: SCL-UP-MIPS, SDA-UP-MIPS.
LAYER 2 error = 28 will be logged and displayed via the

back to
div. table

Other root causes for this error can be due to hardware


problems regarding the DDRs and the bootscript reading
from the PNX8550.
Error 16 (12V). This voltage is made in the power supply
and results in protection (LAYER 1 error = 3) in case of
absence. When SDM is activated we see blinking LED
LAYER 2 error = 16.
Error 17 (Invertor or Display Supply). Here the status of
the Power OK is checked by software, no protection will
occur during failure of the invertor or display supply (no
picture), only error logging. LED blinking of LAYER 1
error = 3 in CSM, in SDM this gives LAYER 2 error = 17.
Error 21 (PNX51X0). When there is no I2C communication
towards the PNX51X0 after start-up, LAYER 2 error = 21
will be logged and displayed via the blinking LED
procedure if SDM is switched on. This device is located on
the 200 Hz panel from the display.
Error 23 (HDMI). When there is no I2C communication
towards the HDMI mux after start-up, LAYER 2 error = 23
will be logged and displayed via the blinking LED
procedure if SDM is switched on.
Error 24 (I2C switch). When there is no I2C
communication towards the I2C switch, LAYER 2
error = 24 will be logged and displayed via the blinking LED
procedure when SDM is switched on. Remark: this only
works for TV sets with an I2C controlled screen included.
Error 28 (Channel dec DVB-S). When there is no I2C
communication towards the DVB-S channel decoder,
blinking LED procedure if SDM is switched on.
2011-Nov-04

EN 56

5.

Q552.2E LA

Service Modes, Error Codes, and Fault Finding

Error 31 (Lnb controller). When there is no I2C


communication towards this device, LAYER 2 error = 31
will be logged and displayed via the blinking LED
procedure if SDM is activated.
Error 34 (Tuner). When there is no I2C communication
towards the tuner during start-up, LAYER 2 error = 34 will
be logged and displayed via the blinking LED procedure
when SDM is switched on.
Error 35 (main NVM). When there is no I2C
communication towards the main NVM during start-up,
LAYER 2 error = 35 will be displayed via the blinking LED
procedure when SDM is switched on. All service modes
(CSM, SAM and SDM) are accessible during this failure,
observed in the Uart logging as follows: "<< ERRO >>>
PFPOW_.C: First Error (id19, Layer_1= 2 Layer_= 35)".
Error 36 (Tuner DVB-S). When there is no I2C
communication towards the DVB-S tuner during start-up,
LAYER 2 error = 36 will be logged and displayed via the
blinking LED procedure when SDM is switched on.
Error 42 (Temp sensor). Only applicable for TV sets
equipped with temperature devices.
Error 53. This error will indicate that the PNX8550 has
read his bootscript (when this would have failed, error 15
would blink) but initialization was never completed because
of hardware problems (NAND flash, ...) or software
initialization problems. Possible cause could be that there
is no valid software loaded (try to upgrade to the latest main
software version). Note that it can take a few minutes
before the TV starts blinking LAYER 1 error = 2 or in SDM,
LAYER 2 error = 53.
Error 64. Only applicable for TV sets with an I2C controlled
screen.

5.6

The Blinking LED Procedure

5.6.1

Introduction

4. Six short blinks followed by a pause of 3 s


5. One long blink of 3 s to finish the sequence (spacer).
6. The sequence starts again.
5.6.2

Use one of the following methods:


Activate the CSM. The blinking front LED will show only
the latest layer 1 error, this works in normal operation
mode or automatically when the error/protection is
monitored by the Stand-by processor.
In case no picture is shown and there is no LED blinking,
read the logging to detect whether error devices are
mentioned. (see section 5.8 Fault Finding and Repair
Tips, 5.8.7 Logging).
Activate the SDM. The blinking front LED will show the
entire content of the LAYER 2 error buffer, this works in
normal operation mode or when SDM (via hardware pins)
is activated when the tv set is in protection.

5.7

Protections

5.7.1

Software Protections
Most of the protections and errors use either the stand-by
microprocessor or the MIPS controller as detection device.
Since in these cases, checking of observers, polling of ADCs,
and filtering of input values are all heavily software based,
these protections are referred to as software protections.
There are several types of software related protections, solving
a variety of fault conditions:
Related to supplies: presence of the +5V, +3V3 and 1V2
needs to be measured, no protection triggered here.
Protections related to breakdown of the safety check
mechanism. E.g. since the protection detections are done
by means of software, failing of the software will have to
initiate a protection mode since safety cannot be
guaranteed any more.

The blinking LED procedure can be split up into two situations:


Blinking LED procedure LAYER 1 error. In this case the
error is automatically blinked when the TV is put in CSM.
This will be only one digit error, namely the one that is
referring to the defective board (see table 5-2 Error code
overview) which causes the failure of the TV. This
approach will especially be used for home repair and call
centres. The aim here is to have service diagnosis from a
distance.
Blinking LED procedure LAYER 2 error. Via this
procedure, the contents of the error buffer can be made
visible via the front LED. In this case the error contains
2 digits (see table 5-2 Error code overview) and will be
displayed when SDM (hardware pins) is activated. This is
especially useful for fault finding and gives more details
regarding the failure of the defective board.
Important remark:
For an empty error buffer, the LED should not blink at all in
CSM or SDM. No spacer will be displayed.

Remark on the Supply Errors


The detection of a supply dip or supply loss during the normal
playing of the set does not lead to a protection, but to a cold
reboot of the set. If the supply is still missing after the reboot,
the TV will go to protection.
Protections during Start-up
During TV start-up, some voltages and IC observers are
actively monitored to be able to optimise the start-up speed,
and to assure good operation of all components. If these
monitors do not respond in a defined way, this indicates a
malfunction of the system and leads to a protection. As the
observers are only used during start-up, they are described in
the start-up flow in detail (see section 5.3 Stepwise Start-up).
5.7.2

When one of the blinking LED procedures is activated, the front


LED will show (blink) the contents of the error buffer. Error
codes greater then 10 are shown as follows:
1. n long blinks (where n = 1 to 9) indicating decimal digit
2. A pause of 1.5 s
3. n short blinks (where n= 1 to 9)
4. A pause of approximately 3 s,
5. When all the error codes are displayed, the sequence
finishes with a LED blink of 3 s (spacer).
6. The sequence starts again.

Hardware Protections
The only real hardware protection in this chassis appears in
case of an audio problem e.g. DC voltage on the speakers. This
protection will only affect the Class D audio amplifier (item
7D10; see diagram B03A) and puts the amplifier in a
continuous burst mode (cyclus approximately 2 seconds).
Repair Tip
There still will be a picture available but no sound. While
the Class D amplifier tries to start-up again, the cone of the
loudspeakers will move slowly in one or the other direction
until the initial failure shuts the amplifier down, this cyclus
starts over and over again. The headphone amplifier will
also behaves similar.

Example: Error 12 8 6 0 0.
After activation of the SDM, the front LED will show:
1. One long blink of 750 ms (which is an indication of the
decimal digit) followed by a pause of 1.5 s
2. Two short blinks of 250 ms followed by a pause of 3 s
3. Eight short blinks followed by a pause of 3 s
2011-Nov-04

How to Activate

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Service Modes, Error Codes, and Fault Finding


5.8

Fault Finding and Repair Tips

Read also section 5.5 Error Codes, 5.5.4 Error Buffer, Extra
Info.
5.8.1

Ambilight

Audio Amplifier

Description DVB-S2:
LNB-RF1 (0V = disabled, 14V or 18V in normal operation)
LNB supply generated via the second conversion channel
of 7T03 followed by 7T50 LNB supply control IC. It provides
supply voltage that feeds the outdoor satellite reception
equipment.
+3V3-DVBS (3V3 nominal), +2V5-DVBS (2V5 nominal)
and +1V-DVBS (1.03V nominal) power supply for the
silicon tuner and channel decoder. +1V-DVBS is generated
via a 5V to 1V DC-DC converter and is stabilized at the
point of load (channel decoder) by means of feedback
signal SENSE+1V0-DVBS. +3V3-DVBS and +2V5-DVBS
are generated via linear stabilizers from +5V-DVBS that by
itself is generated via the first conversion channel of 7T03.

AV PIP

CSM

At start-up, +24V becomes available when STANDBY signal is


"low" (together with +12V for the basic board), when +3V3 from
the basic board is present the two DC-DC converters channels
inside 7T03 are activated. Initially only the 24V to 5V converter
(channel 1 of 7T03 generating +5V-DVBS) will effectively work,
while +V-LNB is held at a level around 11V7 via diode 6T55.
After 7T05 is initialized, the second channel of 7T03 will start
and generates a voltage higher then LNB-RF1 with 0V8. +5VDVBS start-up will imply +3V3-DVBS start-up, with a small
delay of a few milliseconds => +2V5-DVBS and +1V-DVBS will
be enabled.

When CSM is activated and there is a USB stick connected to


the TV, the software will dump the complete CSM content to the
USB stick. The file (Csm.txt) will be saved in the root of the USB
stick. If this mechanism works it can be concluded that a large
part of the operating system is already working (MIPS, USB...)
5.8.5

+5V-TUN supply voltage (5V nominal) for tuner and IF


amplifier.

+12V is considered OK (=> DETECT2 signal becomes "high",


+12V to +1V8, +12V to +3V3, +12V to +5V DC-DC converter
can be started up) if it rises above 10V and doesnt drop below
9V5. A small delay of a few milliseconds is introduced between
the start-up of 12V to +1V8 DC-DC converter and the two other
DC-DC converters via 7U48 and associated components.

To check the AV PIP board (if present) functionality, a


dedicated tespattern can be invoke as follows: select the
multiview icon in the User Interface and press the OK
button. Apply for the main picture an extended source, e.g.
HDMI input. Proceed by entering CSM (push 123654 on the
remote control) and press the yellow button. A coloured
testpattern should appear now, generated by the AV PIP board
(this can take a few seconds).
5.8.4

EN 57

Supply voltage +1V1 is started immediately when +12V voltage


becomes available (+12V is enabled by STANDBY signal when
"low"). Supply voltages +3V3, +2V5, +1V8, +1V2 and +5V-TUN
are switched "on" by signal ENABLE-3V3 when "low", provided
that +12V (detected via 7U40 and 7U41) is present.

The Class D-IC 7D10 has a powerpad for cooling. When the IC
is replaced it must be ensured that the powerpad is very well
pushed to the PWB while the solder is still liquid. This is needed
to insure that the cooling is guaranteed, otherwise the Class DIC could break down in short time.
5.8.3

5.

+3V3-STANDY (3V3 nominal) is the permanent voltage,


supplying the Stand-by microprocessor inside PNX855xx.

Due to degeneration process of the LEDs fitted on the ambi


module, there can be a difference in the colour and/or light
output of the spare ambilight modules in comparison with the
originals ones contained in the TV set. Via SAM => alignments
=> ambilight, the spare module can be adjusted.
5.8.2

Q552.2E LA

DC/DC Converter
Description basic board

If +24V drops below +15V level then the DVB-S2 supply will
stop, even if +3V3 is still present.

The basic board power supply consists of 4 DC/DC converters


and 5 linear stabilizers. All DC/DC converters have +12V input
voltage and deliver:
+1V1 supply voltage (1.15V nominal), for the core voltage
of PNX855xx, stabilized close to the point of load;
SENSE+1V1 signal provides the DC-DC converter the
needed feedback to achieve this.
+1V8 supply voltage, for the DDR2 memories and DDR2
interface of PNX855xx.
+3V3 supply voltage (3.30V nominal), overall 3.3 V for
onboard ICs, for non-5000 series SSB diversities only.
+5V (5.15V nominal) for USB, WIFI and Conditional
Access Module and +5V5-TUN for +5V-TUN tuner
stabilizer.

Debugging
The best way to find a failure in the DC/DC converters is to
check their start-up sequence at power on via the mains cord,
presuming that the stand-by microprocessor and the external
supply are operational. Take STANDBY signal "high"-to-"low"
transition as time reference.
When +12V becomes available (maximum 1 second after
STANDBY signal goes "low") then +1V1 is started immediately.
After ENABLE-3V3 goes "low", all the other supply voltages
should rise within a few milliseconds.
Tips
Behaviour comparison with a reference TV550 platform
can be a fast way to locate failures.
If +12V stays "low", check the integrity of fuse 1U40.
Check the integrity (at least no short circuit between drain
and source) of the power MOS-FETs before starting up the
platform in SDM, otherwise many components might be
damaged. Using a ohmmeter can detect short circuits
between any power rail and ground or between +12V and
any other power rail.
Short circuit at the output of an integrated linear stabilizer
(7UC0, 7UD2 or 7UD3) will heat up this device strongly.
Switching frequencies should be 500 kHz ...600 kHz for
12 V to 1.1 V and 12 V to 1.8 V DC-DC converters,

The linear stabilizers are providing:


+1V2 supply voltage (1.2V nominal), stabilized close to
PNX855xx device, for various other internal blocks of
PNX855xx; SENSE+1V2 signal provides the needed
feedback to achieve this.
+2V5 supply voltage (2.5V nominal) for LVDS interface and
various other internal blocks of PNX855xx; for 5000 series
SSB diversities the stabilizer is 7UD2 while for the other
diversities 7UC0 is used.
+3V3 supply voltage (3V3 nominal) for 5000 series SSB
diversities, provided by 7UD3; in this case the 12V to 3V3
DC-DC converter is not present.

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2011-Nov-04

EN 58

5.

Q552.2E LA

Service Modes, Error Codes, and Fault Finding


Uart loggings reporting fault conditions, error messages, error
codes, fatal errors:
Failure messages should be checked and investigated.For
instance fatal error on the PNX51x0: check startup of the
back-end processor, supplies..reset, I2C bus. => error
mentioned in the logging as: *51x0 failed to start by itself*.
Some failures are indicated by error codes in the logging,
check with error codes table (see Table 5-2 Error code
overview).e.g. => <<<ERROR>>>PLFPOW_MERR.C :
First Error (id=10,Layer_1=2,Layer_2=23).

I2C bus error mentioned as e.g.: I2C bus 4 blocked.


Not all failures or error messages should be interpreted as
fault.For instance root cause can be due to wrong option
codes settings => e.g. DVBS2Suppoprted : False/True.
In the Uart log startup script we can observe and check the
enabled loaded option codes.

900 kHz for 12 V to 3.3 V and 12 V to 5 V DC-DC


converters. The DVB-S2 supply 24 V to 5 V and 24 V to +V
LNB DC-DC converters operates at 300 kHz while for 5 V
to 1.1 V DC-DC converter 900 kHz is used.
5.8.6

Exit Factory Mode


When an F is displayed in the screens right corner, this
means the set is in Factory mode, and it normally
happens after a new SSB is mounted. To exit this mode, push
the VOLUME minus button on the TVs local keyboard for 10
seconds (this disables the continuous mode).
Then push the SOURCE button for 10 seconds until the F
disappears from the screen.

5.8.7

Logging

Defective sectors (bad blocks) in the Nand Flash can also be


reported in the logging.

When something is wrong with the TV set (f.i. the set is


rebooting) you can check for more information via the logging
in Hyperterminal. The Hyperterminal is available in every
Windows application via Programs, Accessories,
Communications, Hyperterminal. Connect a ComPair UARTcable (3138 188 75051) from the service connector in the TV to
the multi function jack at the front of ComPair II box.
Required settings in ComPair before starting to log:
- Start up the ComPair application.
- Select the correct database (open file Q55X.X, this will set
the ComPair interface in the appropriate mode).
- Close ComPair
After start-up of the Hyperterminal, fill in a name (f.i. logging)
in the Connection Description box, then apply the following
settings:
1. COMx
2. Bits per second = 115200
3. Data bits = 8
4. Parity = none
5. Stop bits = 1
6. Flow control = none
During the start-up of the TV set, the logging will be displayed.
This is also the case during rebooting of the TV set (the same
logging appears time after time). Also available in the logging
is the Display Option Code (useful when there is no picture),
look for item DisplayRawNumber in the beginning of the
logging. Tip: when there is no picture available during rebooting
you are able to check for error devices in the logging (LAYER
2 error) which can be very helpful to determine the failure cause
of the reboot. For protection state, there is no logging.
5.8.8

Startup in the software upgrade application and observe the


Uart logging:
Starting up the TV set in the Manual Software Upgrade mode
will show access to USB, meant to copy software content from
USB to the DRAM.Progress is shown in the logging as follows:
cosupgstdcmds_mcmdwritepart: Programming 102400 bytes,
40505344 of 40607744 bytes programmed.
Startup in Jett Mode:
Check Uart logging in Jet mode mentioned as : JETT UART
READY.
Uart logging changing preset:
=> COMMAND: calling DFB source = RC6, system=0, key = 4.

5.8.9

Make sure that the volume is set to minimum during


disconnecting the speakers in the ON-state of the TV. The
audio amplifier can be damaged by disconnecting the speakers
during ON-state of the set!
5.8.10 PSL
In case of no picture when CSM (test pattern) is activated and
backlight doesnt light up, its recommended first to check the
inverter on the PSL + wiring (LAYER 2 error = 17 is displayed
in SDM).

Guidelines Uart logging

5.8.11 Tuner

Description possible cases:


Uart loggings are displayed:
When Uart loggings are coming out, the first conclusion we
can make is that the TV set is starting up and
communication with the flash RAM seems to be supported.
The PNX855xx is able to read and write in the DRAMs.
We can not yet conclude : Flash RAM and DRAMs are fully
operational/reliable.There still can be errors in the data
transfers, DRAM erros, read/write speed and timing
control.

Attention: In case the tuner is replaced, always check the tuner


options!
5.8.12 Display option code
Attention: In case the SSB is replaced, always check the
display option code in SAM, even when picture is available.
Performance with the incorrect display option code can lead to
unwanted side-effects for certain conditions.

No Uart logging at all:


In case there is no Uart logging coming out, check if the
startup script can be send over the I2C bus (3 trials to
startup) + power supplies are switched on and stable.
No startup will end up in a blinking LED status : error
LAYER 1 = 2, error LAYER 2 = 53 (startup with SDM
solder paths short).
Error LAYER 2 = 15 (hardware cause) is more related to
a supply issue while error LAYER 2 = 53 (software cause)
refers more to boot issues.

2011-Nov-04

Loudspeakers

New in this chassis:


While in the download application (start up in TV mode + OK
button pressed), the display option code can be changed via
062598 HOME XXX special SAM command (XXX=display
option in 3 digits).

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Service Modes, Error Codes, and Fault Finding


5.8.13 SSB Replacement

Q552.2E LA

5.

EN 59

For a more general overview of steps to follow, refer to figure


5-13 SSB replacement flowchart.

Follow the instructions in the flowchart in case a SSB has to be


exchanged. See table 5-3 SSB replacement instructions.

Table 5-3 SSB replacement instructions

Step #

Action to do

Advise / Attention points / Remarks

Ensure ESD protection by using a wristband

If SSB is still functional: Go via SAM to upload to USB and copy Personal
settings - Option codes - Alignments (Presets) - Set Identification.
Advice: because of differences in memory allocation, it is advised to upgrade
main SW before copying data from existing SSB. Copy of Preset list is
possible from normal user interface.

Upload to USB: A directory repair will be created on the USB, and all data will be copied in this
directory. On sets with software before Q552-xx-140-x-x, there was an issue by copying the
program map table, so it is advised to reinstall the programs from Virgin mode instead of using
copy via USB.

Disconnect set from mains and from antenna.

Safety and ESD!

Open the set and disconnect LVDS flat cable. Disconnect other cables /
connections.

Always take care for ESD! Be extra careful when removing connectors!

Dismount the (defective) SSB from the set.

Do not damage SSB copper tracks with your tools! Do not scratch bottom of SSB (be very careful
by moving SSB over SSB supports). See Figure 5-11 and Figure 5-12.

Place new SSB in the set, and fixate/mount carefully.

Do not damage SSB copper tracks with your tools! Do not scratch bottom of SSB (be very careful
by moving SSB over SSB supports). See Figure 5-11 and Figure 5-12.

Connect PSU and other connectors. Insert the optional WiFi module.

Make sure that the connectors are correctly plugged-in and locked (click). Special attention for the
optional WiFi module: a defective WiFi module can give reboots or no start-up of the SSB. In this
case do a trial without WiFi module.

Connect LVDS connector(s).

Be very careful: wrong or bad connection can damage the TCON part on the SSB and damage
the LCD display. Check if flat cables are fitted correctly before closing the connector lock.

Connect set to mains and switch TV On.

Check start-up of the set, backlight switch On

10

If the set does not start (or reboots) check:


- The connectors from the power supply,
- The power supply cable and connection pins,
- LVDS cable connection.

Power supply connector must snap into the socket.

11

Before programming the new SSB, upgrade to latest software. If set is starting Some SSBs will start-up in software upgrade mode, and software needs to be installed before you
up in software upgrade mode, then first install new software via software
can program the Display Option codes. Its adviced to use an autorun.upg file for software
Upgrade Menu or via the autorun.upg file.
upgrade, this in case you have no OSD on the screen.

12

If set is starting up without picture or menu (OSD), first program the correct
Display Option codes.

13

Go to SAM and program Set type and Serial number. This is possible via Programming Set type and Serial number is mandatory to have all functionality of the set, like
the NVM editor and virtual keyboard. In case personal settings were
DLNA, Net TV For certain sets you may need to use ComPair for this.
recovered from the defective SSB, you can use an Upload from USB.

14

Check if option codes are correct, and keys are present. SSBs with integrated Validity of HDCP, CI+, Marlin, and WDRM keys can be checked via ComPair.
TCON needs TCON alignment in SAM.

15

Update to latest software (Standby and main software). This step is necessary Even when the SSB already has the latest software, it is mandatory to upgrade again the software
to make sure that the (optional) 200 Hz T-CON board has the latest software. to update the 200 Hz T-CON part. At the end of the main software update process, a dedicated
software is loaded, from the main processor via the LVDS connection, to upgrade the
200 Hz T-CON part. For certain LCD displays, a dedicated Display software patch (autoscript) is
available. See General Service info GSC_85590.

16

Once the set is playing, check cable connection between PSU and SSB, by
moving the cable if there are no bad connections.

17

Fill in the Electronic DDF (Defect Description Form): Fault symptom, TV type It is mandatory to fill in the E-DDF form (see the At Your Service web portal).
and TV serial number.

18

Install presets or check if all presets are OK. Check in CSM if Type number,
Serial number, Main and Standby software are correct.

19

Check connectivity to Net TV and DLNA. Check AmbiLight functionality.

Only for sets having these functionalities.

20

Inform customer about Memory Card, USB, or Hard drive PVR (Personal
Video Recording) recordings.

Inform customer that previous recordings made on Memory Card (movie download), USB, or Hard
drive will be lost. USB or Hard drive needs to be re-formatted and matched with new SSB (WDRM
Keys!).

Use blind service mode 062598 + Home button, directly followed by the
Display Option code (3 digits). Set will switch to Standby after Display Option code is entered.

Check the two power connectors 1M95 and 1M99. Bad contact or bad connection here can give
reboots.

Special attention for Standby software: check if Standby software ID is matching with the D-RAMs
mounted on the SSB (2 Elpida = 73, 4 Elpida = 64, 2 Hynix = 72, 4 Hynix = 63).

SSB fixation points

Significant risk of damaging the board


by the fixation point
Blue arrows: traces of friction
Red arrows: damaged components

19070_201_110728.eps
110804

19070_202_110728.eps
110804

Figure 5-11 Mounting attention points [1/2]

Figure 5-12 Mounting attention points [2/2]

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2011-Nov-04

EN 60

5.

Service Modes, Error Codes, and Fault Finding

Q552.2E LA

In st ru ct io n n o t e SSB rep lacem en t Q55x.x

ST AR T

Before starting:
- prepare a USB memory stick with the latest software
- download the latest Main Software (Fus) from www.p4c.philips.com
- unzip this file
- create a folder upgrades in the root of a USB stick (size > 50 MB) and
save the autorun.upg file in this "upgrades" folder.
Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this in
case there are more than one "autorun.upg" files on the USB stick.

Set is still oper ating?


No
Yes

C onnect the U SB stick to the set,


go to SAM and save the current TV settings via Upload to USB

1. D ismount the defective SSB.


2. Replace the SSB by a Service SSB.

Start-up the set


Due to a possible wrong display option code in the received Service
SSB (NVM), its possible that no picture is displayed. Due to this
the download application will not be shown either. This tree enables you
to load the main software step-by-step via the UART logging on the PC
(this for visual feedback).
No pictur e displayed

1) Start up the TV set, equiped with the Service SSB,


and enable the UART logging on the PC.

Set behaviour?

Pictur e displayed
Set is starting up without software
upgrade menu appearing on screen

Pictur e displayed
Set is starting up with software
upgrade menu appearing on screen

2) The TV set will start-up automatically in the


download application if main TV software is not loaded.
1) Plug the USB stick into the TV set and select
the autorun .upg file in the displayed browser.

3) Plug the prepared USB stick into the TV set. Follow the
instructions in the UART log file, press Right cursor key to enter
the list. Navigate to the autorun.upg file in the UART logging
printout via the cursor keys on the remote control. When the
correct file is selected, press Ok.

2) Now the main software will be loaded automatically,


supported by a progress bar.
4) Press "Down" cursor and Ok to start flashing the main
TV software. Printouts like: L: 1-100%, V: 1-100% and
P: 1-100% should be visible now in the UART logging.
3) Wait until the message Operation successful ! is displayed
and remove all inserted media. Restart the TV set.

5) Wait until the message Operation successful ! is logged in


the UART log and remove all inserted media. Restart the TV set.

Set the correct Display code via 062598 -HOME- xxx where
xxx is the 3 digit display panel code (see sticker on the side
or bottom of the cabinet)

After entering the Display Option code, the set is going to


Standby
(= validation of code)
Restart the set

No

Connect PC via the ComPair interface to Service connector.

Saved settings
on USB stick?

Yes

Start TV in Jett mode (DVD I + (OSD))


Open ComPair browser Q54x

Go to SAM and reload settings


via Download from USB function.

In case of settings reloaded from USB, the set type,


serial number, display 12 NC, are automatically stored
when entering display options.

Program set type number, serial number, and display 12 NC


Program E - DFU if needed.
If not already done:
Check latest software on Service website.
Update main and Stand-by software via USB.

Attention point for Net TV: If the set type and serial number are not
filled in, the Net TV functionality will not work. It will not be possible
to connect to the internet.

- Check if correct display option code is programmed.


- Verify option codes according to sticker inside the set.
- Default settings for white drive > see Service Manual.

Check and perform alignments in SAM according to the


Service Manual. Option codes, colour temperature, etc.

Final check of all menus in CSM.


Special attention for HDMI Keys and Mac address.
Check if E - D F U is present.

End

Q55x.E SSB Board swap ER on behalf of VDS


Updated 28-07-2011

19070_200_110728.eps
111103

Figure 5-13 SSB replacement flowchart

2011-Nov-04

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Service Modes, Error Codes, and Fault Finding

Q552.2E LA

5.

EN 61

Set is st art in g u p in F act o ry m o d e

Set is starting up in F actory m ode?

Noisy picture with bands/lines is visible and the


RED LED is continuous on.

An F is displayed (and the HDMI 1


input is displayed).

- Press the volume minus button on the TVs local keyboard for 5 ~10
seconds
- Press the SOURCE button for 10 seconds until the F disappears
from the screen or the noise on the screen is replaced by blue mute

The noise on the screen is replaced


with the blue mute or the F is disappeared!

Unplug the mains cord to verify the correct


disabling of the Factory mode.

Program display option code


via 062598 MENU, followed by
the 3 digits code of the display
(this code can be found
on a sticker on - or inside - the set).

After entering display option code, the set is


going in stand-by mode (= validation of code)

R estart the set

H_16771_007b.eps
100322

Figure 5-14 SSB replacement flowchart - Factory mode

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2011-Nov-04

EN 62

5.

Q552.2E LA

Service Modes, Error Codes, and Fault Finding

18753_211_100811.eps
110810

Figure 5-15 SSB start-up


description on how to upgrade the main software can be found
in the electronic User Manual.

5.8.14 Swapping SSBs in Sundance sets (series xxPFL7xxx)


Earlier sets in the Sundance range have an additional
Temperature sensor board located near the SSB. Later
(service-) SSBs lack the presence of the dedicated connector
on the SSB (no. 1M71).

Important: When the NAND-Flash must be replaced, a new


SSB must be ordered, due to the presence of the security keys!
(CI +, MAC address, ...).
Perform the following actions after SSB replacement:
1. Set the correct option codes (see sticker inside the TV).
2. Update the TV software => see the eUM (electronic User
Manual) for instructions.
3. Perform the alignments as described in chapter 6 (section
6.5 Reset of Repaired SSB).
4. Check in CSM if the CI + key, MAC address.. are valid.
For the correct order number of a new SSB, always refer to the
Spare Parts list!

Upon mounting of such an SSB, remove the entire


Temperature sensor board and set option code Temp. sensor
in Option no. 7 to 00. Refer to table 6-21 Option codes at bit
level (Option 1 - Option 8).

5.9

Software Upgrading
Attention!
Software version numbers for 2011 sets are all defined below
number 0.40.x.x. This might confuse servicers who store
software versions for more than one set and/or platform on the
same storage device (USB stick).

5.9.2

Introduction
The set software and security keys are stored in a NANDFlash, which is connected to the PNX855xx.
It is possible for the user to upgrade the main software via the
USB port. This allows replacement of a software image in a
stand alone set, without the need of an E-JTAG debugger. A

2011-Nov-04

The UpgradeAll.upg file is only used in the factory.

Automatic Software Upgrade


In normal conditions, so when there is no major problem with
the TV, the main software and the default software upgrade
application can be upgraded with the AUTORUN.UPG
(FUS part of the one-zip file: e.g. 3104 337 05661 _FUS
_Q555X_ x.x.x.x_prod.zip). This can also be done by the
consumers themselves, but they will have to get their software
from the commercial Philips website or via the Software Update
Assistant in the user menu (see eUM). The autorun.upg file
must be placed in the root of the USB stick.
How to upgrade:
1. Copy AUTORUN.UPG to the root of the USB stick.

Always check the latest software version on the servicer


website in relation to the actual CTN!!!
5.9.1

Main Software Upgrade

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Service Modes, Error Codes, and Fault Finding

2. Insert USB stick in the set while the set is operational. The
set will restart and the upgrading will start automatically. As
soon as the programming is finished, a message is shown
to remove the USB stick and restart the set.

Manual Software Upgrade


In case that the software upgrade application does not start
automatically, it can also be started manually.
How to start the software upgrade application manually:
1. Disconnect the TV from the Mains/AC Power.
2. Press the OK button on a Philips TV remote control or a
Philips DVD RC-6 remote control (it is also possible to use
a TV remote in DVD mode). Keep the OK button
pressed while reconnecting the TV to the Mains/AC Power.
3. The software upgrade application will start.

5.9.5

Q552.2E LA

5.

EN 63

StandbySW_Q555X_x.x.x.x_prod.zip. Contains the


StandbyFactory software in upg format.
ProcessNVM_Q55XX_x.x.x.x_prod.zip. Default NVM
content. Must be programmed via ComPair or can be
loaded via USB, be aware that all alignments stored in
NVM are overwritten here.

UART logging 2K10 (see section 5.8 Fault Finding and


Repair Tips, 5.8.7 Logging)

Attention!
In case the download application has been started manually,
the autorun.upg will maybe not be recognized.
What to do in this case:
1. Create a directory UPGRADES on the USB stick.
2. Rename the autorun.upg to something else, e.g. to
software.upg. Do not use long or complicated names,
keep it simple. Make sure that AUTORUN.UPG is no
longer present in the root of the USB stick.
3. Copy the renamed upg file into this directory.
4. Insert USB stick into the TV.
5. The renamed upg file will be visible and selectable in the
upgrade application.
Back-up Software Upgrade Application
If the default software upgrade application does not start (could
be due to a corrupted boot sector) via the above described
method, try activating the back-up software upgrade
application.
How to start the back-up software upgrade application
manually:
1. Disconnect the TV from the Mains/AC Power.
2. Press the CURSOR DOWN-button on a Philips TV
remote control while reconnecting the TV to the Mains/AC
Power.
3. The back-up software upgrade application will start.
5.9.3

Stand-by Software Upgrade via USB


In this chassis it is possible to upgrade the Stand-by software
via a USB stick. The method is similar to upgrading the main
software via USB.
Use the following steps:
1. Create a directory UPGRADES on the USB stick.
2. Copy the Stand-by software (part of the one-zip file, e.g.
StandbyFactory_88.0.0.0.upg) into this directory.
3. Insert the USB stick into the TV.
4. Start the download application manually (see section
Manual Software Upgrade.
5. Select the appropriate file and press the OK button to
upgrade.

5.9.4

Content and Usage of the One-Zip Software File


Below the content of the One-Zip file is explained, and
instructions on how and when to use it.
AmbiCpld_Q55XX_x.x.x.x_prod.zip. Contains the
program instruction and software content, needed to
upgrade the ambilight CPLD on the TV550 platform.
BalanceFPGA_Q555X_x.x.x.x_prod.zip. Contains the
BalanceFPGA software in upg format.
FUS_Q555X_x.x.x.x_prod.zip. Contains the
autorun.upg which is needed to upgrade the TV main
software and the software download application.
PNX5130UPG_Q555X_x.x.x.x_prod.zip. Contains the
PNX5130 software in upg format.

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2011-Nov-04

EN 64

6.

Q552.2E LA

Alignments

6. Alignments

Index of this chapter:


6.1 General Alignment Conditions
6.2 Hardware Alignments
6.3 Software Alignments
6.4 Option Settings
6.5 Reset of Repaired SSB
6.6 Total Overview SAM modes

6.1

General Alignment Conditions

6.3.1

Perform all electrical adjustments under the following


conditions:
Power supply voltage (depends on region):
AP-NTSC: 120 VAC or 230 VAC / 50 Hz ( 10%).
AP-PAL-multi: 120 - 230 VAC / 50 Hz ( 10%).
EU: 230 VAC / 50 Hz ( 10%).
LATAM-NTSC: 120 - 230 VAC / 50 Hz ( 10%).
US: 120 VAC / 60 Hz ( 10%).
Connect the set to the mains via an isolation transformer
with low internal resistance.
Allow the set to warm up for approximately 15 minutes.
Measure voltages and waveforms in relation to correct
ground (e.g. measure audio signals in relation to
AUDIO_GND).
Caution: It is not allowed to use heat sinks as ground.
Test probe: Ri > 10 M, Ci < 20 pF.
Use an isolated trimmer/screwdriver to perform
alignments.

White Point

Contrast

50

Colour

Light Sensor

Off

Picture format

Unscaled

In menu Picture, choose Pixel Plus HD and set picture


settings as follows:

Picture Setting
Dynamic Contrast

Off

Dynamic Backlight

Off

Colour Enhancement

Off

Gamma

Go to the SAM and select Alignments-> White point.

White point alignment LCD screens:


Use a 100% white screen (format: 720p50) to the HDMI
input and set the following values:
Colour temperature: Cool.
All White point values to: 127.

First, set the correct options:


In SAM, select Option numbers.
Fill in the option settings for Group 1 and Group 2
according to the set sticker (see also paragraph 6.4
Option Settings).
Press OK on the remote control before the cursor is
moved to the left.
In submenu Option numbers select Store and press
OK on the RC.
OR:
In main menu, select Store again and press OK on
the RC.
Switch the set to Stand-by.
Warming up (>15 minutes).

In case you have a colour analyser:


Measure, in a dark environment, with a calibrated
contactless colour analyser (Minolta CA-210 or Minolta
CS-200) in the centre of the screen and note the x, y value.
Change the pattern to 90% white screen. If a Quantum
Data generator is used, select the GreyAll test pattern at
level = 230.
Adjust the correct x, y coordinates (while holding one of the
White point registers R, G or B on 127) by means of
decreasing the value of one or two other white points to the
correct x, y coordinates (see Table 6-1 White D alignment
values - LED - Minolta CA-210, or 6-2 White D alignment
values - LED - Minolta CS-200). Tolerance: dx: 0.002, dy:
0.002.
Repeat this step for the other colour temperatures that
need to be aligned.
When finished press OK on the RC and then press STORE
(in the SAM root menu) to store the aligned values to the
NVM.
Restore the initial picture settings after the alignments.

Hardware Alignments
Not applicable.

6.3

100

Brightness

Alignment Sequence

6.2

Choose TV menu, Setup, More TV Settings and then


Picture and set picture settings as follows:

Picture Setting

6.1.1

EU/AP-PAL models: a PAL B/G TV-signal with a signal


strength of at least 1 mV and a frequency of 475.25 MHz
US/AP-NTSC models: an NTSC M/N TV-signal with a
signal strength of at least 1 mV and a frequency of 61.25
MHz (channel 3).
LATAM models: an NTSC M TV-signal with a signal
strength of at least 1 mV and a frequency of 61.25 MHz
(channel 3).

Software Alignments
Put the set in SAM mode (see Chapter 5. Service Modes, Error
Codes, and Fault Finding). The SAM menu will now appear on
the screen. Select ALIGNMENTS and go to one of the sub
menus. The alignments are explained below.
The following items can be aligned:
White point
Ambilight.

Table 6-1 White D alignment values - LED - Minolta CA-210

To store the data:


Press OK on the RC before the cursor is moved to the
left
In main menu select Store and press OK on the RC
Switch the set to stand-by mode.

Cool (9420K)

Normal (8120K)

Warm (6080K)

0.282

0.292

0.320

0.298

0.311

0.345

Table 6-2 White D alignment values - LED - Minolta CS-200

For the next alignments, supply the following test signals via a
video generator to the RF input:

2011-Nov-04

Value

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Value

Cool (11000K)

Normal (9000K)

Warm (6500K)

0.276

0.287

0.313

0.282

0.296

0.329

Alignments

White Tone

e.g. 32PFL66x6x
R

Normal

127

125

104

Cool

123

127

119

Warm

127

116

62

e.g. 37PFL66x6x

Colour Temp

Normal

122

104

127

Cool

103

91

127

Warm

127

98

84

e.g. 40PFL66x6x

Colour Temp

Normal

124

126

109

Cool

118

126

123

Warm

127

120

69

e.g. 46PFL6xx6x

Colour Temp

Normal

127

123

96

Cool

126

126

113

Warm

127

120

54

e.g. 55PFL66x6x
R

Normal

127

107

117

Cool

121

102

127

Warm

127

95

72

e.g. 32PFL74x6x

Colour Temp

Normal

126

115

127

Cool

108

102

127

Warm

127

104

83

e.g. 42PFL74x6x

Colour Temp

Normal

126

120

110

Cool

122

123

127

Warm

127

107

66

123

112

126

Warm

127

104

74

e.g. 32PFL76x6x

Colour Temp

Normal

127

114

124

Cool

112

102

127

Warm

127

102

79

e.g. 37PFL76x6x

Colour Temp

Normal

126

125

127

Cool

112

112

127

Warm

127

113

86

e.g. 42PFL76x6x

Colour Temp

Normal

126

118

121

Cool

112

109

127

Warm

127

105

77

White Tone

e.g. 47PFL76x6x

Colour Temp

Normal

127

116

118

Cool

119

111

127

Warm

127

105

76

Table 6-15 White tone default setting 55" (Sundance 3D)


White Tone

e.g. 55PFL76x6x

Colour Temp

Normal

124

115

126

Cool

110

101

127

Warm

127

104

84

Table 6-16 White tone default setting 32" (Infinity)


White Tone

e.g. 32PDL7906x

Colour Temp

Normal

127

112

123

Cool

113

102

127

Warm

127

102

79

Table 6-17 White tone default setting 42" (Infinity)


White Tone

Table 6-9 White tone default setting 42" (Sundance)


White Tone

Cool

Table 6-14 White tone default setting 47" (Sundance 3D)

Table 6-8 White tone default setting 32" (Sundance)


White Tone

115

White Tone

Table 6-7 White tone default setting 55" (Blockbuster)

Colour Temp

115

Table 6-13 White tone default setting 42" (Sundance 3D)

White Tone

127

White Tone

Table 6-6 White tone default setting 46" (Blockbuster)


White Tone

Normal

Table 6-12 White tone default setting 37" (Sundance 3D)

Table 6-5 White tone default setting 40" (Blockbuster)


White Tone

e.g. 47PFL74x6x

Colour Temp

White Tone

Table 6-4 White tone default setting 37" (Blockbuster)


White Tone

EN 65

Table 6-11 White tone default setting 32" (Sundance 3D)

Table 6-3 White tone default setting 32" (Blockbuster)

Colour Temp

6.

Table 6-10 White tone default setting 47" (Sundance)

If you do not have a colour analyser, you can use the default
values. This is the next best solution. The default values are
average values coming from production.
Select a COLOUR TEMPERATURE (e.g. COOL,
NORMAL, or WARM).
Set the RED, GREEN and BLUE default values according
to the values in Table 6-3 to Table 6-20.
When finished press OK on the RC, then press STORE (in
the SAM root menu) to store the aligned values to the NVM.
Restore the initial picture settings after the alignments.

White Tone

Q552.2E LA

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e.g. 42PDL7906x

Colour Temp

Normal

127

120

110

Cool

122

119

125

Warm

127

106

66

2011-Nov-04

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6.

Alignments

Q552.2E LA

all at once by using the option codes as described in section


6.4.4.

Table 6-18 White tone default setting 32" (Berlinale)


White Tone

e.g. 32PFL5806x

Colour Temp

Normal

125

127

104

Cool

123

127

120

Warm

127

119

63

6.4.4

Select this sub menu to set all options at once (expressed in


two long strings of numbers).
An option number (or option byte) represents a number of
different options. When you change these numbers directly,
you can set all options very quickly. All options are controlled
via eight option numbers.
When the NVM is replaced, all options will require resetting. To
be certain that the factory settings are reproduced exactly, you
must set both option number lines. You can find the correct
option numbers on a sticker inside the TV set.
Example: The options sticker gives the following option
numbers:
32776 00001 15421 02235
43847 36615 33024 00012
The first line (group 1) indicates hardware options 1 to 4, the
second line (group 2) indicate software options 5 to 8.
Every 5-digit number represents 16 bits (so the maximum value
will be 65536 if all options are set).
When all the correct options are set, the sum of the decimal
values of each Option Byte (OB) will give the option number.

Table 6-19 White tone default setting 40" (Berlinale)


White Tone

e.g. 40PFL5806x

Colour Temp

Normal

127

115

97

Cool

127

117

114

Warm

127

108

56

Table 6-20 White tone default setting 46" (Berlinale)


White Tone

e.g. 46PFL5806x

Colour Temp

Normal

127

117

89

Cool

127

119

107

Warm

127

109

49

6.4

Option Settings

6.4.1

Introduction

Diversity
Not all sets with the same Commercial Type Number (CTN)
necessarily have the same option code!
Use of Alternative BOM => an alternative BOM number usually
indicates the use of an alternative display or power supply. This
results in another display code thus in another Option code.
Refer to Chapter 2. Technical Specs, Diversity, and
Connections.

The microprocessor communicates with a large number of I2C


ICs in the set. To ensure good communication and to make
digital diagnosis possible, the microprocessor has to know
which ICs to address. The presence / absence of these
PNX51XX ICs (back-end advanced video picture improvement
IC which offers motion estimation and compensation features
(commercially called HDNM) plus integrated Ambilight control)
is made known by the option codes.

6.4.5

6.4.6

Option Bit Overview


For test purposes, please find below an overview of the Option
Codes on bit level. With a bin/dec converter, you can calculate
the Option Code.

Dealer Options

Caution
When manipulating option codes, know what youre doing.
Wrong option codes could damage the set.
Prescribed option codes below are an example, not valid for all
sets and are subject to modification.
The correct option codes are always present on a sticker inside
the set!

For dealer options, in SAM select Dealer options.


See Table 6-22 SAM mode overview.
6.4.3

Option Code Overview


Refer to the sticker in the set for the correct option codes.
Important: after having edited the option numbers as
described above, you must press OK on the remote control
before the cursor is moved to the left!

Notes:
After changing the option(s), save them by pressing the OK
button on the RC before the cursor is moved to the left,
select STORE in the SAM root menu and press OK on the
RC.
The new option setting is only active after the TV is
switched off / stand-by and on again with the mains
switch (the NVM is then read again).
6.4.2

Opt. No. (Option numbers)

(Service) Options
From 2011 onwards, it is not longer possible to change
individual option settings in SAM. Options can only be changed
Table 6-21 Option codes at bit level (Option 1 - Option 8)
Option & Bit
Option 1 (prescribed value

Dec. Value

Option Name

Prescribed Value1)

Description

327761))

Bit 15 (MSB)

32768

Video Store Streaming

11)

0 = OFF
1 = ON

Bit 14

16384

Multi App

001)

Bit 13

8192

00 = none
01 = multi app (Multiview BASIC)
10 = AVPIP + multi app (Multiview ENHANCED)
11 = future use

Bit 12

4096

Perfect Pixel

001)

Bit 11

2048

00 = Pixel Plus HD
01 = Pixel Precise HD
10 = Perfect Pixel HD
11 = future use

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Alignments
Option & Bit

Dec. Value

Bit 10

1024

Bit 9

512

Bit 8

256

Bit 7

128

Bit 6

64

Bit 5

32

Bit 4

16

Bit 3

Q552.2E LA

Option Name

Prescribed Value1)

Description

Tuner Type

0001)

000 = TH2603 (Europe/AP)


001 = FA2307 (Brazil)
010 = VA1E1ED2411
011 = future use
100 = future use
101 = future use
110 = future use
111 = future use

PQ Profiles

0001)

000 = profile 0
001 = profile 1
010 = profile 2
011 = profile 3
100 = profile 4
101 = profile 5
110 = profile 6
111 = profile 7

DNM

011)

00 = Perfect Natural Motion


01 = HD Natural Motion
10 = future use
11 = future use

Bit 2

MOP AL

01)

CPLD, not used in 2011

Bit 1

AL Optical Syst

001)

Bit 0 (LSB)

00 = 140 nit
01 = 200 nit
10 = future use
11 = future use

6.

EN 67

Option 2 (prescribed value 000011))


Bit 15 (MSB)

32768

AL Shop Mode

01)

0 = boost mode in shop is OFF


1 = boost mode in shop is ON

Bit 14

16384

AL settings storage location

01)

0 = stored in AL modules
1 = stored in SSB

Bit 13

8192

Wall Adaptive AL

1)

0 = OFF
1 = ON

1)

4096

Sunset

0 = OFF
1 = ON

Bit 11

2048

Ambient Light

00001)

Bit 10

1024

Bit 9

512

Bit 8

256

0000 = none
0001 = 2-sided (3/3)
0010 = 2-sided (4/4)
0011 = 2-sided (5/5)
0100 = 2-sided (6/6)
0101 = 2-sided (7/7)
0110 = 3-sided (5/5/5)
0111 = 3-sided (6/6/6)
1000 = 3-sided (3/6/3)
1001 = 3-sided (6/9/6)
1010 = 2-sided (8/8)
1011 = 3-sided (4/4/4)
1100 = 2-sided (1/1)
1101 = 2-sided (2/2)
1110 = future use
1111 = future use

Bit 7

128

FPGA3Dact/1Ddimm

01)

0 = OFF
1 = ON

Bit 6

64

AL Select

01)

0 = AL2k10
1 = AL2k11

Bit 5

32

3D Passive

01)

0 = 2D
1 = 3D passive

Bit 12

Bit 4

16

1)

Smart Bit Enhancement (SBE)

0 = off
1 = on (200 Hz board present)
0 = Super Resolution SD
1 = Super Resolution HD

Bit 3

Super Resolution

01)

Bit 2

Light Sensor LUT

001)

Bit 1

00 = Lut 0
01 = Lut 1
10 = Lut 2
11 = Lut 3

Bit 0 (LSB)

Light Sensor

11)

0 = OFF
1 = ON

Side IO

01)

0 = not present
1 = present

AV3

0111)

000 = none
001 = CVBS
010 = YPbPr
011 = YPbPr/LR
100 = YPbPr/HV/LR
101 = CVBS/LR
110 = CVBS/Yc/LR
111 = future use

AV2

111)

00 = Scart/CVBS/RGB/LR
01 = CVBS/LR
10 = YPbPr/LR
11 = none

AV1

001)

00 = Scart/CVBS/RGB/LR
01 = CVBS/YC/YPbPr/HV/LR
10 = CVBS/YC/YPbPr/LR
11 = YPbPr/LR

Option 3 (prescribed value 154211))


Bit 15 (MSB)

32768

Bit 14

16384

Bit 13

8192

Bit 12

4096

Bit 11

2048

Bit 10

1024

Bit 9

512

Bit 8

256

Bit 7

128

3D Prepared

01)

0 = not prepared
1 = prepared

Bit 6

64

Sound in Stand

01)

0 = Sound in Cabinet
1 = Sound in Stand

Bit 5
Bit 4

32
16

Headphone

1)

0 = OFF
1 = ON

Seamless System

11)

0 = OFF
1 = ON

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Alignments

Option Name

Prescribed Value1)

Description

Bit 3

ViewPort 21_9/PQL

11)

0 = OFF
1 = ON

Bit 2

HDMI Side

11)

0 = OFF
1 = ON

HDMI 3

01)

0 = OFF
1 = ON

HDMI 2

11)

0 = OFF
1 = ON

Cabinet

000011)

Cabinet type
(no detailed info available)

Region

0001)

000 = Europe (/02, /05 & /12)


001 = AP PAL multi
010 = AP NTSC
011 = Russian (/60)
100 = Latam (/78 & /77)
101 = Australia
110 = China (/93)
111 = future use

Option & Bit

Bit 1
Bit 0 (LSB)

Dec. Value

2
1

Option 4 (prescribed value 022351))


Bit 15 (MSB)

32768

Bit 14

16384

Bit 13

8192

Bit 12

4096

Bit 11

2048

Bit 10

1024

Bit 9

512

Bit 8

256

Bit 7

128

Display MSB

11)

0 = display option =< 255


1 = display option > 255

Bit 6

64

S Video

01)

0 = OFF
1 = ON

Bit 5

32

Video Store SD Card

11)

0 = OFF
1 = ON

Internet software Upgrade

11)

0 = OFF
1 = ON (automatic software upgradable via internet)

Bit 4

16

1)

0 = OFF
1 = ON (connection to internet provider Philips)

Bit 3

Online Service

Bit 2

WiFi

01)

0 = OFF
1 = ON (wireless connection to ethernet; no link with Ethernet option bit 0)

Bit 1

DLNA

11)

0 = OFF
1 = PC link

Bit 0 (LSB)

Ethernet

11)

0 = OFF
1 = Ethernet vonnector and HW present

Option 5 (prescribed value

438471)

Bit 15 (MSB)

32768

8 Days EPG

11)

0 = OFF
1 = ON (country dependent)

Bit 14

16384

DVBC Installation

011)

Bit 13

8192

00 = OFF
01 = Country dependent
10 = ON
11 = future use

Bit 12

4096

DVBT Installation

011)

Bit 11

2048

00 = OFF
01 = Country dependent
10 = ON
11 = future use

Bit 10

1024

DVB-S

01)

0 = OFF
1 = ON (ATSC/DVB should be ON)

Bit 9

512

DVB-C

11)

0 = OFF
1 = ON (ATSC/DVB should be ON)

Bit 8

256

DVB

11)

Bit 7

128

Bit 6

64

Bit 5

32

Bit 4

16

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Display Type

01000111

0 = analogue only
1 = DVBT (and C/S depending DVBC/S option)
1)

Display Type (ex.: 327)

Option 6 (prescribed value 366151))


Bit 15 (MSB)

32768

E-sticker

11)

0 = OFF
1 = ON

Bit 14

16384

Hotel Mode

001)

Bit 13

8192

00 = OFF
01 = 1V1
10 = 1V2
11 = future use

Bit 12

4096

Virgin

01)

0 = ON
1 = OFF

Bit 11

2048

USB Time Shift

11)

0 = OFF
1 = ON

Auto Store Mode

111)

00 = none
01 = PDC_VPS
10 = TXT page
11 = PDC_VPS_TXT

PVR

11)

0 = OFF
1 = ON

Ginga

001)

00 = OFF
01 = Country dependent
10 = ON
11 = future use

Bit 10

1024

Bit 9

512

Bit 8

256

Bit 7

128

Bit 6

64

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Alignments
Option & Bit

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6.

EN 69

Option Name

Prescribed Value1)

Description

MHP

001)

00 = OFF
01 = Country dependent
10 = ON
11 = future use

Over the Air Download

011)

00 = OFF
01 = Country dependent
10 = ON
11 = future use

DVBC light

11)

0 = OFF
1 = ON (when DVBC Installation is OFF or when ON but selected
country is OFF, this option is used)

DVBT light

11)

0 = OFF
1 = ON (when DVBT Installation is OFF or Country depend to a
country is OFF, this option is used)

Dec. Value

Bit 5

32

Bit 4

16

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Option 7 (prescribed value 330241))


Bit 15 (MSB)

32768

Visual Identity

11)

0 = User Interface 2k10


1 = User Interface 2k11

Bit 14

16384

Red LED Config LUT

0001)

Bit 13

8192

Bit 12

4096

000 = LED config LUT 0


001 = LED config LUT 1
010 = LED config LUT 2
011 = LED config LUT 3
100 = LED config LUT 4
101 = LED config LUT 5
110 = LED config LUT 6
111 = LED config LUT 7

Board Identifier

001)

not used, should always be 00

Bit 11

2048

Bit 10

1024

Bit 9

512

Manet

01)

0 = all sets except Manet


1= Manet

Bit 8

256

Auto Power Down

11)

0 = OFF
1 = ON

Light Guide

01)

0 = OFF
1 = ON
0 = integrated set
1 = e-box/monitor

Bit 7

128

Bit 6

64

E-box

01)

Bit 5

32

Temp LUT

0001)

Bit 4

16

Bit 3

000 = temp lut 0


001 = temp lut 1
010 = temp lut 2
011 = temp lut 3
100 = future use
101 = future use
110 = future use
111 = future use

Bit 2

Temp Sensor

001)

Bit 1

00 = no temp sensor
01 = temp sensor in display
10 = temp sensor on additional board
11 = temp sensor in AL module

Bit 0 (LSB)

FAN

01)

0 = no fan
1 = fan(s) present)

Option 8 (prescribed value

000121))

Bit 15 (MSB)

32768

Test 8

01)

Bit 14

16384

Test 7

01)

Bit 13

8192

Test 6

01)

Bit 12

4096

Test 5

01)

Bit 11

2048

Test 4 (Trick Mode)

01)

0 = OFF
1 = ON

Test 3 (XRay)

1)

0 = OFF
1 = ON
0 = OFF
1 = ON

Bit 10

1024

Bit 9

512

Test 2 (DBV-T light)

01)

Bit 8

256

Test 1 (Monitor out)

01)

0 = OFF
1 = ON

Bit 7

128

not used

00001)

Bit 6

64

Bit 5

32

Bit 4

16

Bit 3

WM DRM10

11)

0 = OFF
1 = ON

HBBTV

1)

0 = OFF
1 = ON
0 = OFF
1 = ON
0 = OFF
1 = ON

Bit 2

Bit 1

DVB-T2 Installation

01)

Bit 0 (LSB)

DVB-T2

01)

Also the virgin bit is to be set. To set all this, you can use the
ComPair tool or use the NVM editor and Dealer options
items in SAM (do not forget to store).

Note
1). Example

6.5

Reset of Repaired SSB

After a repaired SSB has been mounted in the set (set repair
on board level), the type number (CTN) and production code of
the TV has to be set according to the type plate of the set. For
this, you can use the NVM editor in SAM. This action also
ensures the correct functioning of the Net TV feature and
access to the Net TV portals. The loading of the CTN and

A very important issue towards a repaired SSB from a Service


repair shop (SSB repair on component level) implies the reset
of the NVM on the SSB.
A repaired SSB in Service should get the service Set type
00PF0000000000 and Production code 00000000000000.
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2011-Nov-04

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6.

Q552.2E LA

Alignments
6.5.1

production code can also be done via ComPair (Model number


programming).

SSB identification
Whenever ordering a new SSB, it should be noted that the
correct ordering number (12nc) of a SSB is located on a sticker
on the SSB. The format is <12nc SSB><serial number>. The
ordering number of a Service SSB is the same as the ordering
number of an initial factory SSB.

After a SSB repair, the original channel map can be restored,


provided that the original channel map was stored on a USB
stick before repair was commenced and that basic functionality
of the TV, needed for this procedure, was not hampered as a
result of the defect. The procedure of channel map cloning is
clearly described in the (electronic) user manual.
In case of a display replacement, reset the Operation hours
display to 0, or to the operation hours of the replacement
display.

18310_221_090318.eps
090319

Figure 6-1 SSB identification

2011-Nov-04

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Alignments
6.6

Q552.2E LA

6.

EN 71

Total Overview SAM modes


Table 6-22 SAM mode overview
Main Menu

Sub-menu 1

Sub-menu 2

Hardware Info

A. software version

e.g. Q5551_0.9.1.0

B. Stand-by processor
version

e.g. STDBY_83.84.0.0

C. Production code

e.g. see type plate

Sub-menu 3

Description
Display TV & Stand-by software version and CTN serial
number

Operation hours

Displays the accumulated total of operation hours.TV


switched on/off & every 0.5 hours is increase one

Errors

Displayed the most recent errors

Reset error buffer


Alignment

Clears all content in the error buffer


White point

Colour temperature

Normal

3 different modes of colour temperature can be selected

Warn
Cool
White point red

LCD White Point Alignment. For values,


see Table 6-3 White tone default setting 32" (Blockbuster)
to 6-15 White tone default setting 55" (Sundance 3D)

White point green


White point blue
Ambilight

Select module
Brightness
Select matrix

Dealer options

Virgin mode

Off/On

Select Virgin mode On/Off. TV starts up / does not start up


(once) with a language selection menu after the mains
switch is turned on for the first time (virgin mode)

E-sticker

Off/On

Select E-sticker On/Off (USPs on-screen)

Auto store mode

None
PDC/VPS
TXT page
PDC/VPS/TXT

Option numbers

Miscellaneous

Hotel mode

Group 1

e.g. 00008.00001.15421.02239

Off

The first line (group 1) indicates hardware options 1 to 4

Group 2

e.g. 44816.34311.33024.00000

The second line (group 2) indicates software options 5 to 8

Store

Hotel mode is Off

Store after changing

Initialise NVM

N.A.

Store

Select Store in the SAM root menu after making any


changes

Operation hours
display

Software maintenance

Software events

0003

In case the display must be swapped for repair, you can


reset the Display operation hours to 0. So, this one
does keeps up the lifetime of the display itself (mainly to
compensate the degeneration behaviour)

Display

Display information is for development purposes

Clear
Test reboot
Test cold reboot
Test application crash
Hardware events

Display

Display information is for development purposes

Clear
Test setting

Digital info

Current frequency: 538


QAM modulation: 64-qam

Display information is for development purposes

Symbol rate:
Original network ID: 12871
Network ID: 12871
Transport stream ID: 2
Service ID: 3
Hierarchical modulation: 0
Selected video PID: 35
Selected main audio PID: 99
Selected 2nd audio PID: 8191
Install start frequency

000

Install start frequency from 0 MHz

Install end frequency

999

Install end frequency as 999 MHz

Digital only

Select Digital only or Digital + Analogue before installation

Default install frequency


Installation

Digital + Analogue

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6.

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Alignments

Main Menu

Sub-menu 1

Sub-menu 2

Development file
versions

Development 1 file version

Display parameters DISPT5.0.9.29

Sub-menu 3

Description
Display information is for development purposes

Acoustics parameters ACSTS


5.0.6.20
PQ - TV550 1.0.27.22
PQS- Profile set
PQF - Fixed settings
PQU - User styles
Ambilight parameters PRFAM
5.0.5.2
Development 2 file version

12NC one zip software

Display information is for development purposes

Initial main software


NVM version Q55x1_0.4.5.0
Flash units software
Temp com file version none
Upload to USB

Channel list

To upload several settings from the TV to an USB stick

Personal settings
Option codes
Alignments
Identification data
History list
All (options included)
Download from USB

Channel list

To download several settings from the USB stick to the TV

Personal settings
Option codes
Alignments
Identification data
All (options included)
NVM editor

2011-Nov-04

Type number

see type plate

AG code

see type plate

NVM editor; re key-in type number and production code


after SSB replacement

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div. table

Circuit Descriptions

Q552.2E LA

7.

EN 73

7. Circuit Descriptions

Index of this chapter:


7.1 Introduction
7.2 Power Supply
7.3 DC/DC Converters
7.4 Front-End Analogue and DVB-T, DVB-C; ISDB-T reception
7.5 Front-End DVB-S(2) reception
7.6 HDMI
7.7 Video and Audio Processing - PNX855xx

The Q552.2E LA chassis comes with the following stylings:


Blockbuster (series xxPFL66xx),
Sundance (series xxPFL76xx).

Notes:
Only new circuits (circuits that are not published recently)
are described.
Figures can deviate slightly from the actual situation, due
to different set executions.
For a good understanding of the following circuit
descriptions, please use the wiring-, block- (see chapter
9. Block Diagrams) and circuit diagrams (see chapter
10. Circuit Diagrams and PWB Layouts).Where necessary,
you will find a separate drawing for clarification.

7.1.1

Introduction

7.1.2

Implementation
Key components of this chassis are:
PNX855xx System-On-Chip (SOC) TV Processor
TX26xx Hybrid Tuner (DVB-T/C, analogue)
STV6110AT DVB-S Satellite Tuner
SII9x87 HDMI Switch
TPA312xD2PWP Class D Power Amplifier
LAN8710 Dual Port Gigabit Ethernet media access
controller.
TV550 Architecture Overview
For details about the chassis block diagrams refer to chapter 9.
Block Diagrams. An overview of the TV550 2011 architecture
can be found in Figure 7-1.

The Q552.2E LA is part of the TV550 platform, is a derivative


from the Q552.1E LA and uses the (same) PNX855xx chipset.
The major deltas versus its predecessor Q551 are:
support of DVB-T2 (second generation DVBT)

FLASH
512MB
DDR2
4x 128MB -533

NVM
8kB

SPI
64kB

LVDS only

32

Matrix
FHD@120p
FHD@100p
DVB-T (EU)
DVB-C (EU+HK)

Hybrid
Tuner
DVB-S2
Tuner

NXP
PNX85500
SOC

AL

DVB-S2 (EU)

DC/DC

Ethernet
PHY

3V3
1V1
1V8
2V5
3V3
5V

USB

3D

IR

Stdby

CPLD

CLASS-D

HDMI 1.3
mux

WIFI

7.1

implementation of passive 3D
removal of TCON from the SSB (comes with the display)
changed power architecture
new USB hub (for Sundance xxPFL76xx/xx sets).

buffer
SD-CARD
CI

19100_059_110217.eps
110217

Figure 7-1 Architecture of TV550 platform 2011

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2011-Nov-04

EN 74
7.1.3

7.

Circuit Descriptions

Q552.2E LA

SSB Cell Layout

1M95

1M99

1M59

DVB-S DC/DC

LONG

PCMCIA

1M71

DC/DC
C

Ambilight
CPLD

FLASH

CD
DDR2

DVB-S2

Tuner

F-type
13.65mm

1G50

DDR2

DDR

LVDS-OUT

1D38

Class-D

1735

DDR2

CA
PNX85500
M1
27x27
1.00mm

TS-IN
USB

ETH

Heatsink

IS
SPDIF

ANA
AUD

ANA
VID

DVB-S DC/DC

HDMI
GPIO
STDBY

SD-SLOT
DDR2
1F24

SCART1/YPbPr

Hybrid
Tuner

1E32

Pb

Pr

L/R

U
T

HDMI

C
TR

91
87

3D

HDMI

HDMI

HDMI

SPDIF
Output

Process Support Wire

1M21

1M20

7E01

Head
Phone

SVC

VGA

1G51

USB2.0

19100_058_110217.eps
110217

Figure 7-2 SSB layout cells (top view)

2011-Nov-04

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Circuit Descriptions
7.2

Power Supply

7.2.1

Power Supply Unit Blockbuster sets

7.

EN 75

Table 7-3 Connector overview 40" sets


Connector

No detailed information is given because of design protection


issues. When defective, replace the whole unit.
7.2.2

Q552.2E LA

Connector overview Blockbuster (series xxPFL6600/xx)


Table 7-1 Connector overview 32" sets
Connector

no.

1308

1316

Descr.

Mains

to display

1M95
to SSB

Pin

CN1

CN2

CN4

Anode 1+

+3V3stdby

n.c.

Standby

Cathode 1-

GND1

n.c.

GND1

Anode 2+

+12V

n.c.

+12V

Cathode 2-

+Vsnd (+24V)

no.

1308

1316

1M95

n.c.

GND_SND

Descr.

Mains

to display

to SSB

Anode 3+

BL-ON-OFF

Pin

CN1

CN2

CN4

10

n.c.

BL-DIM1 (Vsync)

A2

+3V3SB

11

Cathode 3-

BL-I-CTRL

n.c.

Standby

12

n.c.

POK

pin 5

GND1

13

Anode 4+

+24V (AL2_DVBS)

n.c.

GND1

14

n.c.

GND1

15

Cathode 4-

pin 3

+12V3

n.c.

+12V3

OCD

+Vsnd

n.c.

GND1

A1

BL-ON-OFF

10

n.c.

BL-DIM1

11

pin 13

BL-I-CTRL

12

n.c.

POK

13

pin 11

+24V

14

n.c.

GND1

15

GND1

7.3

The on-board DC/DC converters deliver the following voltages


(depending on set execution):
+3V3-STANDBY, permanent voltage for the Stand-by
controller, LED/IR receiver and controls; connector 1M95
pin 1
+12V, input from the power supply for TV550 common
(active mode); connector 1M95 pins 6, 7 and 8
+24V, input from the power supply for DVB-S2 (in active
mode); connector 1M09 pins 1 and 2
+1V1, core voltage supply for PNX855xx; has to be started
up first and switched "off" last (diagram B03B)
+1V2, supply voltage for analogue blocks inside PNX855xx
+1V8, supply voltage for DDR2 (diagram B03B)
+2V5, supply voltage for analogue blocks inside PNX855xx
(see diagram B03E)
+3V3, general supply voltage (diagram B03E)
+5V, supply voltage for USB and CAM (diagram B03E)
+5V-TUN, supply voltage for tuner (diagram B03E)
+V-LNB, input voltage for LNB supply IC (item no. 7T50)
+5V-DVBS, input intermediate supply voltage for DVB-S2
(diagram B08A)
+3V3-DVBS, clean voltage for silicon tuner and DVB-S2
channel decoder
+2V5-DVBS, clean voltage for DVB-S2 channel decoder
+1V-DVBS, core voltage for DVB-S2 channel decoder.

Table 7-2 Connector overview 37" sets


Connector
no.

1308

1316

Descr.

Mains

to display

to SSB

Pin

CN1

CN2

CN4

1M95

Anode_R

+3V3stdby

n.c.

Standby

R5 Cathode

GND1

R4 Cathode

GND1

R3 Cathode

+12V

R2 Cathode

+12V

R1 Cathode

+Vsnd (+24V)
GND_SND

L1 Cathode

L2 Cathode

BL-ON-OFF

10

L3 Cathode

BL-DIM1 (Vsync)

11

L4 Cathode

BL-I-CTRL

12

L5 Cathode

POK

13

n.c.

+24V (AL2_DVBS)

14

Anode_L

GND1

15

DC/DC Converters

A +12 V under-voltage detector (see diagram B03C) enables


the 12V to 3.3V and 12V to 5V DC/DC converters via the
ENABLE-3V3-5V line, and the 12V to 1.8V DC/DC converter
via the ENABLE-1V8 line. DETECT2 is the signal going to the
Stand-by microcontroller and ENABLE-3V3n is the signal
coming from the Stand-by microcontroller.
Diagram B03D contains the following linear stabilisers:
+2V5 stabiliser, built around item no. 7UCO
+5V-TUN stabiliser, built around items no. 7UA6 and 7UA7
+1V2 stabiliser, built around items no. 7UA3 and 7UA4.
Diagram B08A contains the DVB-S2-related DC/DC
converters and -stabilisers:
a +24V under-voltage detection circuitry is built around
item no. 7T04
the switching frequency of the 24 to 14...20V switched
mode converter is 350 kHz (item no. 7T03 and +V-LNB
lines)
the output signal on the +V-LNB line goes to the LNBH23Q
(item no. 7T50)
the LNBH23Q (item no. 7T50) sends a feedback signal via
the V0-CNTRL line
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2011-Nov-04

EN 76

7.

Circuit Descriptions

Q552.2E LA

7.5

the switching frequency of the +5V-DVBS to +1-DVBS


switched mode converter is 900 kHz (item no. 7T00)
a delay line for the +2V5-DVBS and +1V-DVBS lines is
created with item no. 3T03 (R=10k) and 2T06 (C=100n)
a 3.3V to 2.5V linear stabiliser is built around item no. 7T01
a 5V to 3.3V linear stabiliser is built around item no. 7T02.

Front-End DVB-S(2) reception


The Front-End for the DVB-S(2) application consist of the
following key components:

Diagram B08B contains the DVB-S2 LNB supply:


the +V-LNB signal comes from item no. 7T03
the V0-CTRL signal goes to item no. 7T03
the LNB-RF1 goes to the LNB.

Figures gives a graphical representation of the DC/DC


converters with its current consumptions:

Satellite Tuner; I2C address 0xC6 (bridged via channel


decoder)
Channel decoder; I2C address 0xD0
LNB switching regulator; I2C address 0x14
Amplifier
PNX855xx SoC TV processor with integrated DVB-T and
DVB-C channel decoder and analogue demodulator.

Below find a block diagram of the front-end application for


DVB-S(2) reception.

+ 5V 5-TUN
196 m A
+ 5V
dc -dc

+ 12V
2919 m A

+ 3V 3
dc -dc

+ 1V 8
dc -dc

+ 1V 1
dc -dc

+ 5V 5-TUN

+ 5V
2179 m A

+ 3V 3

+ 3V 3
2371 m A

+ 1V 8

+ 1V 8
2450 m A

+ 5V -TUN
s tabiliz er

+ 2V 5
s tabiliz er

+ 1V 2
s tabiliz er

+ 5V -TUN
196 m A

+ 2V 5
450 m A

+ 1V 2
550 m A

+ 1V 1
5100 m A

18770_237_100127.eps
100219

18770_226_100127.eps
100426

Figure 7-5 Front-End block diagram DVB-S(2) reception

Figure 7-3 DC/DC converters

7.4

Front-End Analogue and DVB-T, DVB-C;


ISDB-T reception

7.4.1

European/China region

This application supports the following protocols:


Polarization selection via supply voltage (18V = horizontal,
13V = vertical)
Band selection via toneburst (22 kHz): tone on = high
band, tone off = low band
Satellite (LNB) selection via DiSEqC 1.0 protocol
Reception of DVB-S (supporting QPSK encoded signals)
and DVB-S2 (supporting QPSK, 8PSK, 16APSK and
32APSK encoded signals), introducing LDPC low-density
parity check techniques.

The Front-End for the European/China region consist of the


following key components:

Hybrid Tuner
Switchable SAW filter 7/8 MHz (Eur.), or single SAW filter
(8 MHz) (China)
Bandpass filter
Amplifier
PNX855xx SoC TV processor with integrated DVB-T and
DVB-C channel decoder and analogue demodulator.

7.6

In this platform, the Silicon Image Sil9x87 HDMI multiplexer is


implemented. Refer to figure 7-6 HDMI input configuration for
the application.

Below find a block diagram of the front-end application for this


region.

18770_235_100127.eps
100219

Figure 7-4 Front-End block diagram European/China region

2011-Nov-04

HDMI

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Circuit Descriptions

Q552.2E LA

7.

EN 77

and vivid colour management. High flat panel screen


resolutions and refresh rates are supported with formats
including 1366 768 @ 100Hz/120Hz and 1920 1080 @
100Hz/120Hz. The combination of Ethernet, CI+ and H.264
supports new TV experiences with IPTV and VOD. On top of
that, optional support is available for 2D dimming in
combination with LED backlights for optimum contrast and
power savings up to 50%.
For a functional diagram of the PNX855xx, refer
to Figure 7-7.

18770_243_100203.eps
100203

Figure 7-6 HDMI input configuration


The following multiplexers can be used:
Sil9187A (does not support Instaport technology for fast
switching between input signals)
Sil9287B (supports Instaport technology for fast
switching between input signals).
The hardware default I2C addresses are:
Sil9187A: 0xB0/0xB2 (random: software workaround)
Sil9287B: 0xB2 (fixed).
The Sil9x87 has the following specifications:
+5V detection mechanism
Stable clock detection mechanism
Integrated EDID
RT control
HPD control
Sync detection
TMDS output control
CEC control
EDID stored in Sil9x87, therefore there are no EDID pins
on the SSB.

7.7

Video and Audio Processing - PNX855xx


The PNX855xx is the main audio and video processor (or
System-on-Chip) for this platform. It has the following features:

Multi-standard digital video decoder (MPEG-2, H.264,


MPEG-4)
Integrated DVB-T/DVB-C channel decoder
Integrated CI+
Integrated motion accurate picture processing (MAPP2)
High definition ME/MC
2D LED backlight dimming option
Embedded HDMI HDCP keys
Extended colour gamut and colour booster
Integrated USB2.0 host controller
Improved MPEG artefact reduction compared with
PNX8543
Security for customers own code/settings (secure flash).

The TV550 combines front-end video processing functions,


such as DVB-T channel decoding, MPEG-2/H.264 decode,
analog video decode and HDMI reception, with advanced
back-end video picture improvements. It also includes next
generation Motion Accurate Picture Processing (MAPP2). The
MAPP2 technology provides state-of-the-art motion artifact
reduction with movie judder cancellation, motion sharpness
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2011-Nov-04

EN 78

7.

Q552.2E LA

Circuit Descriptions

PNX85500x

MEMORY
CONTROLLER

TS input

DVB

MPEG
SYSTEM
PROCESSOR

CI/CA

TS out/in for
PCMCIA

PRIMARY
VIDEO
OUTPUT

LVDS

LVDS for
flat panel display
(single, dual or
quad channel)

DVB-T/C
channel decoder
AV-PIP
SUB-PICTURE
VIDEO
DECODER

CVBS, Y/C,
RGB

3D COMB
SECONDARY
VIDEO
OUTPUT

Low-IF

SSIF, LR

DIGITAL IF

MPEG/H.264
VIDEO
DECODER

VIDEO
ENCODER

analog CVBS

AUDIO DACS

analog audio

Motion-accurate
pixel processing
SCALER,
DE-INTERLACE
AND NOISE
REDUCTION

AUDIO DEMOD
AND DECODE

AUDIO IN

SPDIF

AUDIO DSP
AUDIO OUT
HDMI
RECEIVER

HDMI

450 MHz
AV-DSP
560 MHz
MIPS32
24KEf CPU

SYSTEM
CONTROLLER
(8051)

I 2S
SPDIF

DRAWING
ENGINE

DMA BLOCK

I2C

PWM GPIO

IR

ADC

SPI

UART

I 2C

GPIO Flash USB 2.0 SD Ethernet


Memory MAC
x8
Card

18770_241_100201.eps
111103

Figure 7-7 PNX855xx functional diagram

2011-Nov-04

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IC Data Sheets

Q552.2E LA

8.

EN 79

8. IC Data Sheets
This chapter shows the internal block diagrams and pin
configurations of ICs that are drawn as black boxes in the

Diagram USB Hub B01C, USB2513B (IC 7F25)

Block diagram
To Upstream
VBUS

Upstream
USB Data

To EEPROM or
SMBus Master

24 MHz
Crystal

SDA SCL

3.3 V

BusPower
Detect/
Vbus Pulse

Upstream
PHY

Regulator

Serial
Interface

PLL

Serial
Interface
Engine

Repeater

3.3 V

...

TT
#1

Regulator

Controller

TT
#x

Port
Controller

CRFILT

Routing & Port Re-Ordering Logic

Port #1
PHY#1

OC Sense
Switch Driver/
LED Drivers

...

Port #x
OC Sense
Switch Driver/
LED Drivers

PHY#x

USB Data
OC
Port
Downstream Sense Power
Switch/
LED
Drivers

OC
USB Data
Port
Downstream Sense Power
Switch/
LED
Drivers

The x indicates the number of available downstream ports: 2, 3, 4, or 7.

NC

NC

NC

21

19

SCL / SMBCLK / CFG_SEL[0]

24

20

HS_IND / CFG_SEL[1]

25

VDD33

RESET_N

26

SDA / SMBDATA / NON_REM[1]

VBUS_DET

27

Pinning information

22

The LED port indicators only apply to USB2513i.

23

SUSP_IND / LOCAL_PWR / NON_REM[0]

28

18

NC

VDD33

29

17

OCS_N[2]

USBDM_UP

30

16

PRTPWR[2] / BC_EN[2]*

USBDP_UP

31

15

VDD33

XTALOUT

32

14

CRFILT

XTALIN / CLKIN

33

13

OCS_N[1]

PLLFILT

34

12

PRTPWR[1] / BC_EN[1]*

11

TEST

10

VDD33

9
NC

6
NC

5
VDD33

4
USBDP_DN[2]

NC

3
USBDM_DN[2]

36

VDD33

35

Ground Pad
(must be connected to VSS)

USBDP_DN[1]

RBIAS

SMSC
USB2512/12A/12B
USB2512i/12Ai/12Bi
(Top View QFN-36)

NC

Note :

USBDM_DN[1]

8.1

electrical diagrams (with the exception of memory and logic


ICs).

Indicates pins on the bottom of the device.

18770_301_100217.eps
100217

Figure 8-1 Internal block diagram and pin configuration


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2011-Nov-04

EN 80
8.2

8.

IC Data Sheets

Q552.2E LA

Diagram Temp sensor & headphone B01J, LM75BDP (IC 7FD1)

Block diagram
VCC

LM75B
BIAS
REFERENCE

POINTER
REGISTER

CONFIGURATION
REGISTER

BAND GAP
TEMP SENSOR

COUNTER

TEMPERATURE
REGISTER

TIMER

TOS
REGISTER

COMPARATOR/
INTERRUPT

THYST
REGISTER

11-BIT
SIGMA-DELTA
A-to-D
CONVERTER

OSCILLATOR

POWER-ON
RESET

OS

LOGIC CONTROL AND INTERFACE

A2

A1

A0

SCL SDA

GND

Pinning information

SDA

VCC

SCL

A0

A1

A2

OS

GND

LM75BDP

18770_300_100217.eps
100217

Figure 8-2 Pin configuration

2011-Nov-04

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IC Data Sheets
8.3

Q552.2E LA

8.

EN 81

Diagram B02 313912364954 B02A, PNX855xx (IC7S00)

Block diagram
PNX8550x

MEMORY
CONTROLLER

TS input

MPEG
SYSTEM
PROCESSOR

CI/CA

TS out/in for
PCMCIA

PRIMARY
VIDEO
OUTPUT

LVDS

LVDS for
flat panel display
(single, dual or
quad channel)

DVB-T/C
channel decoder

DVB

AV-PIP
SUB-PICTURE
VIDEO
DECODER

CVBS, Y/C,
RGB

3D COMB
SECONDARY
VIDEO
OUTPUT

Low-IF

MULTISTANDARD
VIDEO
DECODER

DIGITAL IF

Direct-IF

SPDIF

AUDIO IN

HDMI

HDMI
RECEIVER

analog CVBS

AUDIO DACS

analog audio

analog Y/C

Motion-accurate
pixel processing
SCALER,
DE-INTERLACE
AND NOISE
REDUCTION

AUDIO DEMOD
AND DECODE

SSIF, LR

VIDEO
ENCODER

AUDIO DSP
AUDIO OUT
450 MHz
AV-DSP
500 MHz
MIPS32
24KEf CPU

SYSTEM
CONTROLLER
(8051)

I2S
SPDIF

DRAWING
ENGINE
Scatter/Gather
TS Demux

I2C

PWM Px_x

IR

ADC

SPI

UART

I2C

GPIO Flash USB 2.0 SD Ethernet


Memory MAC
x 10
Card

Pinning information
ball A1
index area

PNX8550xE
2 4 6 8 10 12 14 16 18 20 22 24 26
1 3 5 7 9 11 13 15 17 19 21 23 25

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
Transparent top view
18770_308_100217.eps
100217

Figure 8-3 Internal block diagram and pin configuration

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2011-Nov-04

EN 82
8.4

8.

IC Data Sheets

Q552.2E LA

Diagram B03 313912364954 B03A, TPA312xD2PWP (IC7D10)

Block diagram
TPA3120D2
1 F

0.22 F
LIN

BSR

RIN

ROUT

1 F

22 H

0.68 F

PGNDR

0.68 F

PGNDL

1 F
BYPASS
AGND

470 F

LOUT
22 H

BSL

470 F

0.22 F

PVCCL
AVCC
PVCCR

VCLAMP
Shutdown
Control

SD

1 F

MUTE

GAIN0
GAIN1

Pinning information

PVCCL
SD
PVCCL
MUTE
LIN
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PVCCR

Control

PWP (TSSOP) PACKAGE


(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

PGNDL
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
PGNDR
I_18020_142.eps
100402

Figure 8-4 Internal block diagram and pin configuration

2011-Nov-04

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IC Data Sheets
8.5

Q552.2E LA

8.

EN 83

Diagram DC/DC B03B, TPS53126PW (IC7U03)

Block diagram

Pinning information
VBST1

28

NC

27

LL1

EN1

26

DRVL1
PGND1

DRVH1

25

24

TRIP1

NC

23

VIN

22

VREG5

GND

TEST1

NC

TPS53124

VO1
VFB1

21

V5FILT

20

TEST2
TRIP2

VFB2

10

19

VO2

11

18

PGND2

17

DRVL2

EN2

12

NC

13

16

LL2

VBST2

14

15

DRVH2

18310_300_090319.eps
100416

Figure 8-5 Internal block diagram and pin configuration

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2011-Nov-04

EN 84
8.6

8.

IC Data Sheets

Q552.2E LA

Diagram DC/DC B03E, ST1S10PH (IC 7UD0)

Block diagram

ST1S10PH

Pinning information

DFN8 (4 4)

PowerSO-8
I_18010_083.eps
110601

Figure 8-6 Internal block diagram and pin configuration

2011-Nov-04

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IC Data Sheets
8.7

Q552.2E LA

8.

EN 85

Diagram DC/DC B03E, LD1117DT25 (IC 7UD2)

Block diagram

LD1117DT

Pinning information

DPAK

F_15710_166.eps
100402

Figure 8-7 Internal block diagram and pin configuration

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2011-Nov-04

EN 86
8.8

8.

IC Data Sheets

Q552.2E LA

Diagram Ethernet & Service B04C, LAN8710A-EZKH (IC 7E10)

Block diagram
MODE0
MODE1
MODE2
nRST

MODE Control

AutoNegotiation

10M Tx
Logic

Reset
Control

SMI

RMIISEL

HP Auto-MDIX

10M
Transmitter

TXP / TXN

Transmit Section
100M Tx
Logic

Management
Control

RXP / RXN

100M
Transmitter
MDIX
Control

TXD[0:3]
TXEN
TXER
TXCLK

CRS
COL/CRS_DV

RMII / MII Logic

RXD[0:3]
RXDV
RXER
RXCLK

100M Rx
Logic

DSP System:
Clock
Data Recovery
Equalizer

PLL

Analog-toDigital

XTAL2

Interrupt
Generator

nINT

100M PLL

Receive Section

LED Circuitry
10M Rx
Logic

Squelch &
Filters
10M PLL

MDC
MDIO

XTAL1/CLKIN

LED1
LED2

Central
Bias

RBIAS

PHY
Address
Latches

PHYAD[0:2]

RBIAS

RXP

RXN

TXP

TXN

VDD1A

RXDV

TXD3

32

31

30

29

28

27

26

25

Pinning information

VDD2A

24

TXD2

LED2/nINTSEL

23

TXD1

LED1/REGOFF

22

TXD0

21

TXEN

20

TXCLK

19

nRST

18

nINT/TXER/TXD4

17

MDC

13

14

15

16

RXER/RXD4/PHYAD0

CRS

COL/CRS_DV/MODE2

MDIO

VSS
12

VDDIO

RXD3/PHYAD2

10

11

RXD0/MDE0

VDDCR
RXCLK/PHYAD1

RXD1/MODE1

RXD2/RMIISEL

XTAL2
XTAL1/CLKIN

SMSC
LAN8710/LAN8710i
32 PIN QFN
(Top View)

18770_302_100217.eps
100217

Figure 8-8 Internal block diagram and pin configuration

2011-Nov-04

back to
div. table

IC Data Sheets
8.9

Q552.2E LA

8.

EN 87

Diagram HDMI B04D, SiI9x87B (IC 7EC1)

Block diagram

Pinning information

18770_303_100217.eps
100217

Figure 8-9 Internal block diagram and pin configuration

back to
div. table

2011-Nov-04

EN 88

8.

IC Data Sheets

Q552.2E LA

8.10 Diagram Headphone B04E, TPA6111A2DGN (IC 7EE1)

Block diagram
VDD 8

VDD/2
2

IN 1

BYPASS

VO1 1

TPA6111A2
6

IN 2

SHUTDOWN

VO2 7

Bias
Control

Pinning information
D OR DGN PACKAGE
(TOP VIEW)

VO1
IN1
BYPASS
GND

VDD
VO2
IN2
SHUTDOWN
18770_309_100217.eps
110602

Figure 8-10 Internal block diagram and pin configuration

2011-Nov-04

back to
div. table

IC Data Sheets

Q552.2E LA

8.

EN 89

8.11 Diagram DVBS-FE B07A, STV6110AT (IC 7R02)

Block diagram
STV6110AT

RF_OUT
IP

RF_IN

IN
QP
AGC
QN
PLL, dividers
XTAL_IN
XTAL_INN

DC offset compensation
SCL
I2C bus interface

Amplifier

SDA

XTAL_OUT

18770_304_100217.eps
110601

Figure 8-11 Internal block diagram and pin configuration

back to
div. table

2011-Nov-04

EN 90

8.

IC Data Sheets

Q552.2E LA

8.12 Diagram DVBS supply B08A, TPS54283PWP (IC 7T03)

Block diagram
TPS54283PWP
CLK1

Level
Shift

+
4
+
FB1

BOOT1

PVDD1

SW1

Current
Comparator

f(IDRAIN1) + DC(ofst)
GND

2
BP

R
R

f(IDRAIN1)

Overcurrent Comp

0.8 VREF

RCOMP
Soft Start
1

SD1

f(ISLOPE1)

BP

f(IMAX1)
CLK1

CCOMP

Anti-Cross
Conduction

VDD2

Weak
Pull-Down
MOSFET

f(ISLOPE1)
Ramp
Gen 1
TSD

6 A
EN1

EN2

1.2 MHz
Oscilator

6 A

CLK1

Divide
by 2/4

f(ISLOPE2)
Ramp
Gen 2

SD1
Internal
Control

SD2

CLK2

UVLO
150 k
SEQ 10

BP
150 k

FB1
FB2

CLK2

Output
Undervoltage
Detect

13 BOOT2
BP

Level
Shift

14 PVDD2

f(IDRAIN2) + DC(ofst)

Current
Comparator
+

GND

4
+

FB2

R
R

FET
Switch

f(IDRAIN2)

Overcurrent Comp

0.8 VREF

RCOMP
Soft Start
2

SD2

f(ISLOPE2)

CLK2

CCOMP

5.25-V
Regulator

BP 11
150 k

12 SW2
BP

f(IMAX2)

Anti-Cross
Conduction

Weak
Pull-Down
MOSFET

PVDD2

BP
ILIM2

Level
Select

9
150 k

0.8 VREF
References
IMAX2 (Set to one of two limits)
UDG-07007

18770_305_100217.eps
110601

Figure 8-12 Internal block diagram and pin configuration

2011-Nov-04

back to
div. table

IC Data Sheets

Q552.2E LA

8.

EN 91

8.13 Diagram DVBS supply B08B, LNBH23Q (IC 7T50)

Block diagram
ISEL

TTX

ADDR

SDA SCL

Vcc

LX
PWM
Controller

Rsense

Byp

Vcc- L

Preregulator
+U.V.lockout
+P.ON reset
EN
VSEL

P-GND

VSEL
EN

TTX
ITEST

Vup

I2C interface

VOUT Control
TEN

Linear Post-reg
+Modulator
+Protections
+Diagnostics

VoRX

I2C Diagnostics

VoTX
TTX

22KHz
Oscill.

22KHz Tone
Amp. Diagn.

EXTM

22KHz Tone
Freq. Detector

DETIN

DSQOUT

DSQIN

LNBH23

V CTRL

A-GND

Pinning information
1 n.c .
2 n.c .
3 n.c .
4 LX
5 P -G N D
6 S DA
7 n.c .
8 n.c .
9 S CL
10 A D DR
11 DS Q out
12 DS Q IN
13 E XTM
14 TTX
15 B Y P
16 n.c .
17 n.c .
18 V c c -L
19 V c c
20 A -G N D
21 V oRX
22 V oTX
23 n.c .
24 n.c .
25 n.c .
26 n.c .
27 V up
28 IS E L
29 D E TIN
30 V C TRL
31 n.c .
32 n.c .

Epad

Connected with power grounds and to


the ground layer through vias
to dissipate the heat.

18770_306_100217.eps
100217

Figure 8-13 Internal block diagram and pin configuration

back to
div. table

2011-Nov-04

EN 92

8.

Q552.2E LA

IC Data Sheets

Personal Notes:

10000_012_090121.eps
110804

2011-Nov-04

back to
div. table

Block Diagrams

Q552.2E LA

9.

EN 93

9. Block Diagrams
9-1 Wiring diagram Berlinale 32"
WIRING DIAGRAM 32" BERLINALE

1316

1M95

10P

14P

TO DISPLAY
SUPPLY

8M95

LOUDSPEAKER
(5213)

MAIN POWER SUPPLY


32" PLDC-P015A
(1005)
1M95

SSB

USB

3139 123 6523.x


(1150)

HDMI

2P

HDMI

HDMI

TUNER

51P
3P

51P

1D38
TO DISPLAY

8P

LCD DISPLAY
(1004)

1M20

8G51

1G51

14P

VGA

130

C2

(8308)

C1

IR/LED/CONTROL BOARD

J1

(1108)

8P

1M95 (B01)
1. +3V3STBY
2. STANDBY
3. GND
4. GND
5. +12VS
6. +12VS
7. +24VAUDIO
8. GND
9. LAMP-ON
10. BACKLIGHT-PWM
11. BACKLIGHT-BOOST
12. POWER-OK
13. N.C.
14. GND

LEADING EDGE

2011-Nov-04 back to

div. table

1735 (B03A)
1D38
(B03)

1M20 (B04C)

1.
2.
3.
4.

1.
2.
3.
4.
5.
6.
7.
8.

LEFT_SPEAKER
LEFT-SPEAKER
GND-AUDIO
RIGHT_SPEAKER
GND-AUDIO
RIGHT-SPEAKER

1G51 (B06B)
1. +VDISP-INT
2. +VDISP-INT
3. +VDISP-INT
4. +VDISP-INT
|
|
51. GND

(5216)

LOUDSPEAKER

MAINS
SWITCH

INLET

8308

(5216)

LOUDSPEAKER

LIGHT-SENSOR
GND
RC
LED-2
+3V3STBY
LED-1
KEYBOARD
+5V_SW

19130_053_110616.eps
110928

Block Diagrams

Q552.2E LA

9.

EN 94

9-2 Wiring diagram Berlinale 40" - 46"


WIRING DIAGRAM BERLINALE 40" - 46"

DISPLAY
SUPPLY

CN2

MAIN POWER SUPPLY


14P
CN4

40 PLDE-P017A
(1005)

8M95

SPEAKER BOX
(5213)

SSB
(1150)

CN6004 CN6005 CN7001


4P
3P
14P

CN1
2P

CN4003
8P

CN4010
51P

8G51
8308

51P

INLET

LCD DISPLAY
(1004)

TWEETER

TWEETER

(5216)

(5216)
CN2

CN1

MAINS
SWITCH
(8308)

LEADING EDGE

2011-Nov-04 back to

div. table

(1108)

J1
4P

CN4010 (B010)
1. Panel_12V
2. Panel_12V
3. Panel_12V
4. Panel_12V
|
|
51. GND

CN4003 (B04)
1.
2.
3.
4.
5.
6.
7.
8.

LIGHT_SENSOR
GND
RC6
Green_Button
3V3SB
LED_G
Key1
+5V_SW

CN7001 (B01)
1. STB_PWR3V3
2. STANDBY
3. GND
4. GND
5. +12V
6. +12V
7. +24V
8. GND
9. INVERTER_ON_OFF
10. BRIGHT_ADJ
11. N.C.
12. N.C.
13. N.C.
14. GND

CN6005 (B06)
1. OUT2A
2. GND
3. OUT2B

CN6004 (B06)
1.
2.
3.
4.

OUT1A
GND
GND
OUT1B

19150_001_110511.eps
110914

Block Diagrams

Q552.2E LA

9.

EN 95

9-3 Wiring diagram Blockbuster 32"


WIRING DIAGRAM 32" BLOCKBUSTER

TO DISPLAY
SUPPLY

8M95

1M95
14P

LOUDSPEAKER

41P

SD-CARD
READER

HDMI

USB

HDMI

INLET

MAINS
SWITCH

C2

(8308)

1316 (PSU)

1M95 (PSU)

1308 (PSU)

1. ANODE 1
2. NC
3. CATHODE 1
4. GND
5. ANODE 2
6. NC
7. CATHODE 2
8. NC
9. ANODE 3
10. NC
11. CATHODE 3
12. NC
13. ANODE 4
14. NC
15. CATHODE 4

1. +3V3STDBY
2. STANDBY
3. GND
4. GND
5. +12V
6. +12V
7. +VSND
8. GND_SND
9. BL-ON-OFF
10. BL-DIM1
11. BL-I-CTRL
12. POK
13. +24V
14. GND1

1. N
2. L

C1

IR/LED/CONTROL BOARD

J1

(1108)

8P

1M95 (B03C)
1. +3V3-STANDBY
2. STANDBY
3. GND
4. GND
5. +12VIN
6. +12VIN
7. +24V-AUDIO-POWER
8. GND
9. LAMP-ON
10. BACKLIGHT-PWM_BL-VS
11. BACKLIGHT-BOOST
12. POWER-OK
13. +24V
GND

LEADING EDGE

2011-Nov-04 back to

div. table

VGA

LOUDSPEAKER

HDMI

PHONE

41P

8308

(5216)

LOUDSPEAKER

2P
130
8

TO DISPLAY

SPDIF

51P

LCD DISPLAY
(1004)

ETHER
NET

(1005)

TO DISPLAY

HDMI

51P

SCART
TUNER

1G51

8G51

8P

MAIN POWER SUPPLY


32" DPS-93BP

1M19

8G50

1735 (B03A)
1D38
(B03A)

1M19 (B09A)

1.
2.
3.
4.

1.
2.
3.
4.
5.
6.
7.
8.

LEFT-SPEAKER
GND-AUDIO
RIGHT-SPEAKER
GND-AUDIO
RIGHT-SPEAKER

1735 (B03A)
1.
2.
3.
4.

LEFT-SPEAKER
GND-AUDIO
GND-AUDIO
RIGHT-SPEAKER

LIGHT-SENSOR
GND
RC
LED-2
+3V3-STANDBY
LED-1
KEYBOARD
+5V

(5216)

14P

3139 123 6495.x


(1150)

3P

1M95

10P

SSB

4P

1316

1735 1D38

1G50

(5213)

1G51 (B06B)
1. +VDISP
2. +VDISP
3. +VDISP
4. +VDISP
|
|
51. CTRL-DISP

19100_808_110211.eps
110322

Block Diagrams

Q552.2E LA

9.

EN 96

9-4 Wiring diagram Blockbuster 37"


WIRING DIAGRAM 37" BLOCKBUSTER

TO DISPLAY
SUPPLY

8M95

14P

SD-CARD
READER

8G50

3139 123 6495.x


(1150)

3P

14P

SSB

4P

1M95

10P

1735 1D38

1316

41P

1M95

(5213)

1G50

LOUDSPEAKER

USB

51P

SCART

TO DISPLAY
41P

2P

HDMI

HDMI

HDMI

PHONE

51P

LCD DISPLAY
(1004)

SPDIF

TO DISPLAY

ETHER
NET

TUNER

(1005)

HDMI

1G51

8P

MAIN POWER SUPPLY


37" FSP110-4FS01

1M19

8G51

VGA

13
0

MAINS
SWITCH

1316 (PSU)
1. ANODE 1
2. NC
3. CATHODE 1
4. GND
5. ANODE 2
6. NC
7. CATHODE 2
8. NC
9. ANODE 3
10. NC
11. CATHODE 3
12. NC
13. ANODE 4
14. NC
15. CATHODE 4

1M95 (PSU)
1. +3V3STDBY
2. STANDBY
3. GND
4. GND
5. +12V
6. +12V
7. +VSND
8. GND_SND
9. BL-ON-OFF
10. BL-DIM1
11. BL-I-CTRL
12. POK
13. +24V
14. GND1

1308 (PSU)
1. N
2. L

C1

IR / LED BOARD

J1

(1108)

8P

1M95 (B03C)
1. +3V3-STANDBY
2. STANDBY
3. GND
4. GND
5. +12VIN
6. +12VIN
7. +24V-AUDIO-POWER
8. GND
9. LAMP-ON
10. BACKLIGHT-PWM_BL-VS
11. BACKLIGHT-BOOST
12. POWER-OK
13. +24V
GND

(8308)

2011-Nov-04 back to

div. table

1D38 (B03A)

1M19 (B09A)

1G51 (B06B)

1. LEFT-SPEAKER
2. GND-AUDIO
3. RIGHT-SPEAKER

1.
2.
3.
4.
5.
6.
7.
8.

1. +VDISP
2. +VDISP
3. +VDISP
4. +VDISP
|
|
51. CTRL-DISP

1735 (B03A)
1.
2.
3.
4.

LEFT-SPEAKER
GND-AUDIO
GND-AUDIO
RIGHT-SPEAKER

LIGHT-SENSOR
GND
RC
LED-2
+3V3-STANDBY
LED-1
KEYBOARD
+5V

(5216)

LOUDSPEAKER

C2

INLET

8308

(5216)

LOUDSPEAKER

19100_809_110211.eps
110309

Block Diagrams

Q552.2E LA

9.

EN 97

9-5 Wiring diagram Blockbuster 40" - 55"


WIRING DIAGRAM 40"- 55" BLOCKBUSTER

TO DISPLY
SUPPLT

1316

14P

1M99

10P

8M95
1M95

MAIN POWER SUPPLY


40" PLDE-P007A
46" PLDG-P009A
55" PLDK-P011A

14P

41P

SSB

SD-CARD
READER

3P

3139 123 6495.x


(1150)

USB

4P

8G51

(5213)

51P

LCD DISPLAY
(1004)

HDMI

HDMI

HDMI

PHONE

SPDIF

ETHER
NET

8G50

TO DISPLAY

HDMI

SCART
TUNER

51P

1735 1D38

1G51

8P

LOUDSPEAKER

1M19

2P

1308

1G50

(1005)

VGA

TO DISPLAY
41P

8308

INLET
LOUDSPEAKER

LOUDSPEAKER

(5216)

(5216)
MAINS
SWITCH

C2

C1

(8308)

1316 (PSU)

1M95 (PSU)

1308 (PSU)

1. ANODE 1
2. NC
3. CATHODE 1
4. GND
5. ANODE 2
6. NC
7. CATHODE 2
8. NC
9. ANODE 3
10. NC
11. CATHODE 3
12. NC
13. ANODE 4
14. NC
15. CATHODE 4

1. +3V3STDBY
2. STANDBY
3. GND
4. GND
5. +12V
6. +12V
7. +VSND
8. GND_SND
9. BL-ON-OFF
10. BL-DIM1
11. BL-I-CTRL
12. POK
13. +24V
14. GND1

1. N
2. L

IR/LED/CONTROL BOARD

J1

(1108)

8P

LEADING EDGE

2011-Nov-04 back to

div. table

1M95 (B03C)
1. +3V3-STANDBY
2. STANDBY
3. GND
4. GND
5. +12VIN
6. +12VIN
7. +24V-AUDIO-POWER
8. GND
9. LAMP-ON
10. BACKLIGHT-PWM_BL-VS
11. BACKLIGHT-BOOST
12. POWER-OK
13. +24V
GND

1735 (B03A)

1M19 (B09A)

1.
2.
3.
4.

1.
2.
3.
4.
5.
6.
7.
8.

LEFT-SPEAKER
GND-AUDIO
GND-AUDIO
RIGHT-SPEAKER

1D38 (B03A)
1. LEFT-SPEAKER
2. GND-AUDIO
3. RIGHT-SPEAKER

LIGHT-SENSOR
GND
RC
LED-2
+3V3-STANDBY
LED-1
KEYBOARD
+5V

1G51 (B06B)
1. +VDISP
2. +VDISP
3. +VDISP
4. +VDISP
|
|
51. CTRL-DISP

19100_807_110211.eps
110404

Block Diagrams

Q552.2E LA

9.

EN 98

9-6 Wiring diagram Infinity 32"


WIRING DIAGRAM 32" INFINITY

8M84
TO DISPLAY
SUPPLY

4P
SD-CARD
READER
USB
USB

AL
1M83

HDMI

HDMI

26P

HDMI

TUNER
SPDIF

41P

18P

3139 123 6519.x


(1150)

SCART

ETHER
NET

51P

TO DISPLAY

1M85

4P

1M71

SSB

41P

1G50
51P

1G51

LCD DISPLAY
(1004)

11P

8G51

(1005)

(1163)

5P

AMBILIGHT MODULE

1F24

26P

8G50

1M20

(1163)

4P

AL

1M59

4P

09

MAIN POWER SUPPLY


32" FSP103-4FS01

TO DISPLAY

VGA

HDMI

2P
08

MAINS
SWITCH

CN1

(5216)

CN2

8M21

INLET

LOUDSPEAKER

8308

(8308)

1M99

14P

3P

1735 1D38

14P

1M

AMBILIGHT MODULE

1M95

13

1M95

4P

(5213)

10P

1T02

8M59
8M59

(1027)

8F24

8M95

18P

1M86

8M99

8M71

LOUDSPEAKER

1316

TEMP. SENSOR

TS

LOUDSPEAKER
(5216)

IR/LED/CONTROL BOARD

IR BOARD

J1

(1108)

11P

WIFI MODULE
(1115)

1M95 (B03C)
1D38 (B03A)

1735 (B03A)

1. LEFT-SPEAKER
2. GND-AUDIO
3. RIGHT-SPEAKER

1.
2.
3.
4.

1G51 (B06B)
1. +VDISP
2. +VDISP
3. +VDISP
4. +VDISP
|
|
51. N.C.

1M71 (B09A)
1.
2.
3.
4.

SCL-BL
GND
SDA-BL
+3V3

1F24 (B01C)
1.
2.
3.
4.
5.

LEFT-SPEAKER
GND-AUDIO
GND-AUDIO
RIGHT-SPEAKER

1M99 (B03C)
1. GND_AL
2. +12V_AL
3. GND_AL
4. +12V_AL

+5V
USB-WIFI-DDn
USB-WIFI-DDP
GND
GND

2011-Nov-04 back to

div. table

1M20 (B09A)
1.
2.
3.
4.
5.
6.
7.
8.
9.

LIGHT-SENSOR
LED-1
LED-2
GND
KEYBOARD
+3V3-STANDBY
RC
SCL-SET
SDA-SET

1. +3V3-STANDBY
2. STANDBY
3. GND
4. GND
5. +12VIN
6. +12VIN
7. +24V-AUDIO-POWER
8. GND
9. LAMP-ON
10. BACKLIGHT-PWM_BL-VS
11. BACKLIGHT-BOOST
12. POWER-OK
13. +24V
GND

1M59 (B09A)
1. AMBI-SPI-CLK-OUT
2. GND
3. AMBI-SPI-SDO-OUT
4. AMBI-SPI-SDI-OUT-GI
5. V-AMBI
6. AMBI-PWM-CLK_B2
7. GND
8. AMBI-SPI-CS-OUTn_R2
9. AMBI-LATCH1_G2
10. V-AMBI
11. AMBI-BLANK_R1
12. AMBI-PROG_B1
13. AMBI-LATCH2_DIS
14. AMBI-TEMP

15. GND_AL
16. GND_AL
17. GND_AL
18. GND_AL
19. GND_AL
20. N.C.
21. +12V_AL
22. +12V_AL
23. +12V_AL
24. +12V_AL
25. +12V_AL
26. +12V_AL

19100_824_110708.eps
110708

Block Diagrams

Q552.2E LA

9.

EN 99

9-7 Wiring diagram Infinity 42"


WIRING DIAGRAM 42" INFINITY
LED
POWER

8M84

TEMP. SENSOR

1F24

26P

5P

HDMI HDMI

VGA

26P

USB
HDMI

USB

TUNER
SPDIF

ETHER
NET

HDMI

1M83

SD-CARD
READER

3P
4P

51P
11P

1735 1D38

1G51
1M20

2P

1308

(1163)

8G50

SCART

AL

3139 123 6519.x


(1150)

41P

1G50

SSB

(5213)

AL

AMBILIGHT MODULE

B
LOUDSPEAKER

26P

1M59

4P

1M84

1M99

14P
4P

1M71

14P

1M95

(1005)

1M95

(1163)

8M59

8M95

MAIN POWER SUPPLY


42" DPS-186FP

AMBILIGHT MODULE

8M99

4P

1T02

10P
4P

10P

(1027)

8F24
1M09

1319

1M83

26P

TS
1316

8G51

8308
TO DISPLAY
41P

MAINS
SWITCH

(8308)

INLET

LCD DISPLAY
(1004)

TO DISPLAY
51P

LOUDSPEAKER

LOUDSPEAKER

(5216)

CN1

(5216)

CN2

8M21
KEYBOARD CONTROL

IR BOARD

(1108)

1D38 (B03A)
1. LEFT-SPEAKER
2. GND-AUDIO
3. RIGHT-SPEAKER

1G51 (B06B)
1. +VDISP
2. +VDISP
3. +VDISP
4. +VDISP
|
|
51. N.C.

1M71 (B09A)
1.
2.
3.
4.

SCL-BL
GND
SDA-BL
+3V3

1F24 (B01C)
1.
2.
3.
4.
5.

WIFI MODULE

J1

(1115)

11P

+5V
USB-WIFI-DDn
USB-WIFI-DDP
GND
GND

2011-Nov-04 back to

div. table

1735 (B03A)
1.
2.
3.
4.

LEFT-SPEAKER
GND-AUDIO
GND-AUDIO
RIGHT-SPEAKER

1M99 (B03C)
1. GND_AL
2. +12V_AL
3. GND_AL
4. +12V_AL

1M20 (B09A)
1.
2.
3.
4.
5.
6.
7.
8.
9.

LIGHT-SENSOR
LED-1
LED-2
GND
KEYBOARD
+3V3-STANDBY
RC
SCL-SET
SDA-SET

1M95 (B03C)
1. +3V3-STANDBY
2. STANDBY
3. GND
4. GND
5. +12VIN
6. +12VIN
7. +24V-AUDIO-POWER
8. GND
9. LAMP-ON
10. BACKLIGHT-PWM_BL-VS
11. BACKLIGHT-BOOST
12. POWER-OK
13. +24V
GND

1M59 (B09A)
1. AMBI-SPI-CLK-OUT
2. GND
3. AMBI-SPI-SDO-OUT
4. AMBI-SPI-SDI-OUT-GI
5. V-AMBI
6. AMBI-PWM-CLK_B2
7. GND
8. AMBI-SPI-CS-OUTn_R2
9. AMBI-LATCH1_G2
10. V-AMBI
11. AMBI-BLANK_R1
12. AMBI-PROG_B1
13. AMBI-LATCH2_DIS
14. AMBI-TEMP

15. GND_AL
16. GND_AL
17. GND_AL
18. GND_AL
19. GND_AL
20. N.C.
21. +12V_AL
22. +12V_AL
23. +12V_AL
24. +12V_AL
25. +12V_AL
26. +12V_AL
19100_825_110708.eps
110708

Block Diagrams

Q552.2E LA

9.

EN 100

9-8 Wiring diagram Sundance 32" - 37"


WIRING DIAGRAM 32"- 37" SUNDANCE

8M84

18P

4P
SD-CARD
READER
USB
USB

SPDIF

HDMI

HDMI

26P

1M83

TUNER

HDMI

AL

SCART

ETHER
NET

41P

1M85

4P

3139 123 6519.x


(1150)

41P

1M71

SSB

3P

1G50
TO DISPLAY

(1163)

5P

VGA

HDMI

8308

51P

51P

LCD DISPLAY
(1004)

TO DISPLAY

1G51

8G51

8P

(1163)

4P

AL

1F24

26P

8G50

(1005)

2
13 P
08

CN1

CN2

8M20

LOUDSPEAKER
(5216)

1M59

4P

09

MAIN POWER SUPPLY


32" FSP096-4FS01

1M99

14P

(1027)

4P

1735 1D38

INLET

1M20

14P

1M95

LOUDSPEAKER

1M

AMBILIGHT MODULE

1M95

10P

1T02

8M59
8M59

8M95

18P

1M86

8M09

8M71

(5213)

1316

TEMP. SENSOR

TS

AMBILIGHT MODULE

TO DISPLAY
SUPPLY

LOUDSPEAKER
(5216)

MAINS
SWITCH
(8308)

IR/LED/CONTROL BOARD

J1

(1108)

8P

1D38 (B03A)
1. LEFT-SPEAKER
2. GND-AUDIO
3. RIGHT-SPEAKER

1G51 (B06B)
1. +VDISP
2. +VDISP
3. +VDISP
4. +VDISP
|
|
51. N.C.

1M71 (B09A)
1.
2.
3.
4.

SCL-BL
GND
SDA-BL
+3V3

1F24 (B01C)
1.
2.
3.
4.
5.

+5V
USB-WIFI-DDn
USB-WIFI-DDP
GND
GND

WIFI MODULE
(1115)

1735 (B03A)
1.
2.
3.
4.

LEFT-SPEAKER
GND-AUDIO
GND-AUDIO
RIGHT-SPEAKER

1M99 (B03C)
1. GND_AL
2. +12V_AL
3. GND_AL
4. +12V_AL

2011-Nov-04 back to

div. table

1M20 (B09A)
1.
2.
3.
4.
5.
6.
7.
8.
9.

LIGHT-SENSOR
LED-1
LED-2
GND
KEYBOARD
+3V3-STANDBY
RC
SCL-SET
SDA-SET

1M95 (B03C)
1. +3V3-STANDBY
2. STANDBY
3. GND
4. GND
5. +12VIN
6. +12VIN
7. +24V-AUDIO-POWER
8. GND
9. LAMP-ON
10. BACKLIGHT-PWM_BL-VS
11. BACKLIGHT-BOOST
12. POWER-OK
13. +24V
GND

1M59 (B09A)
1. AMBI-SPI-CLK-OUT
2. GND
3. AMBI-SPI-SDO-OUT
4. AMBI-SPI-SDI-OUT-GI
5. V-AMBI
6. AMBI-PWM-CLK_B2
7. GND
8. AMBI-SPI-CS-OUTn_R2
9. AMBI-LATCH1_G2
10. V-AMBI
11. AMBI-BLANK_R1
12. AMBI-PROG_B1
13. AMBI-LATCH2_DIS
14. AMBI-TEMP

15. GND_AL
16. GND_AL
17. GND_AL
18. GND_AL
19. GND_AL
20. N.C.
21. +12V_AL
22. +12V_AL
23. +12V_AL
24. +12V_AL
25. +12V_AL
26. +12V_AL

19100_819_110505.eps
110803

Block Diagrams

Q552.2E LA

9.

EN 101

9-9 Wiring diagram Sundance 42" - 47" - 55"


WIRING DIAGRAM 42"- 55" SUNDANCE
LED
POWER

8M84

TEMP. SENSOR

1F24

26P

5P

USB
HDMI

USB

TUNER
SPDIF

ETHER
NET

HDMI

HDMI HDMI

VGA

26P

SD-CARD
READER

3P
4P
51P
8P

1735 1D38
1G51
1M20

2P

1308

(1163)

8G50

SCART

AL

3139 123 6519.x


(1150)

41P

1G50

SSB

(5213)

AL

AMBILIGHT MODULE

B
LOUDSPEAKER

26P

1M59

4P

1M84

1M99

14P

1M83

(1005)

1M95

4P

1M71

14P

1M99

MAIN POWER SUPPLY


42" DPS-139AP
47" DPS-186FP

(1163)

8M59

8M95

AMBILIGHT MODULE

8M99

4P

1T02

10P
4P

10P

(1027)

8M71
1M09

1319

1M83

26P

TS
1316

8G51

8308

INLET

TO DISPLAY
41P

LCD DISPLAY
(1004)

TO DISPLAY
51P

LOUDSPEAKER

LOUDSPEAKER

(5216)

CN1

(5216)

CN2

MAINS
SWITCH

8M20

(8318)

IR/LED/CONTROL BOARD

J1

WIFI MODULE

(1108)

8P

(1115)

1D38 (B03A)
1. LEFT-SPEAKER
2. GND-AUDIO
3. RIGHT-SPEAKER

1G51 (B06B)
1. +VDISP
2. +VDISP
3. +VDISP
4. +VDISP
|
|
51. N.C.

1M71 (B09A)
1.
2.
3.
4.

SCL-BL
GND
SDA-BL
+3V3

1F24 (B01C)
1.
2.
3.
4.
5.

+5V
USB-WIFI-DDn
USB-WIFI-DDP
GND
GND

2011-Nov-04 back to

div. table

1735 (B03A)
1.
2.
3.
4.

LEFT-SPEAKER
GND-AUDIO
GND-AUDIO
RIGHT-SPEAKER

1M99 (B03C)
1. GND_AL
2. +12V_AL
3. GND_AL
4. +12V_AL

1M20 (B09A)
1.
2.
3.
4.
5.
6.
7.
8.
9.

LIGHT-SENSOR
LED-1
LED-2
GND
KEYBOARD
+3V3-STANDBY
RC
SCL-SET
SDA-SET

1M95 (B03C)
1. +3V3-STANDBY
2. STANDBY
3. GND
4. GND
5. +12VIN
6. +12VIN
7. +24V-AUDIO-POWER
8. GND
9. LAMP-ON
10. BACKLIGHT-PWM_BL-VS
11. BACKLIGHT-BOOST
12. POWER-OK
13. +24V
GND

1M59 (B09A)
1. AMBI-SPI-CLK-OUT
2. GND
3. AMBI-SPI-SDO-OUT
4. AMBI-SPI-SDI-OUT-GI
5. V-AMBI
6. AMBI-PWM-CLK_B2
7. GND
8. AMBI-SPI-CS-OUTn_R2
9. AMBI-LATCH1_G2
10. V-AMBI
11. AMBI-BLANK_R1
12. AMBI-PROG_B1
13. AMBI-LATCH2_DIS
14. AMBI-TEMP

15. GND_AL
16. GND_AL
17. GND_AL
18. GND_AL
19. GND_AL
20. N.C.
21. +12V_AL
22. +12V_AL
23. +12V_AL
24. +12V_AL
25. +12V_AL
26. +12V_AL
19100_818_110505.eps
110708

Block Diagrams

Q552.2E LA

9.

EN 102

9-10 Block Diagram Video


VIDEO
B01A

COMMON INTERFACE

B02

1P00
17
51
52

7F01
74LVC245APW
20

VIDEO OUT - LVDS

7S00
PNX85537EB
+3V3

68P

PCMCIA

B06B

PNX85500

+5VCA

18

1G50
1

B02A VIDEO STREAM

2
B02F LVDS

CONDITIONAL
ACCESS

MDO(0-7)

CA-MDO(0-7)

BUFFER

9R04

B10A

DVBT2

1T01
TH2627

10

TUN-IF-P

4 5F73

11

TUN-IF-N

1
2F90

1F75

2F78

IF-P-DVBT2

3F79-4

DRX2+

26

DRX2DRX1+

25
24

AVI-B

20

AV1-CVBS

DRX1DRX0+

23
RXD
22

DRXC+

20

12

DRXC-

19

7E06
EF

72

ARX2ARX1+

71
70

ARX1ARX0+

69
RXA
68

AV1-STATUS

21

7E09-1

16

66

12

ARXC-

65

B02G
CONTROL
B02G
CONTROL

R-VGA

G-VGA
B-VGA
H-SYNC-VGA

3
13
14

11

AF16 VGA_R
AD16
VGA_G
AE16
VGA_B
AB18
HSYNC_IN
AC18
VSYNC_IN

V-SYNC-VGA

19
18

1
2

1P03

HDMI 2
CONNECTOR

BRX2+

BRX2BRX1+

7
6

BRX1BRX0+

5
RXB
4

BRX0-

BRXC+

12

BRXC-

B04B

B01C

+5V-USB1
1P08
1

USB_DN
USB_DP

FLASH

7FL5
CY7C65631

7F20
H27U4G8F2DTR

NAND_CE1
NAND_RDY1
NAND_WP_

CRX2+

18

CRX2CRX1+

17
16

CRX1CRX0+

15
14

9
10

CRX0-

13

CRXC+

12

12

CRXC-

11

+3V3-HDMI

9,27,64

USB
HUB

A2
V1

AV3-PR

AC15

AV3-Y

AE15

AV3-PB

AD15

2
3

USB2-DM
USB2-DP

4
21

9
7
19

+5V

13

22

1F24
1

SIDE USB
CONNECTOR

2
3
4
5

USB-WIFI-DDn
USB-WIFI-DDP

+3V3

DDR2-VREF-CTRL2
DDR2-VREF-CTRL3

SSB 3139 123 6519.x

DDR

PR_R_C1
DDR2-D(0-31)

DQ

1E03

SIDE USB
CONNECTOR

+5V-USB2
1P07
1

9
10
5

14

B05A
2

1E08
EXT 3

NAND-CE1n
E21
F21 NAND-RDY1n
NAND-WPn
A21

Y_G1
PB_B1

7B00
H5PS1G83E

SDRAM
128Mx8

17

NAND
FLASH

XIO-D(00-07)

VCC
12,37
VREF_1
VREF_2

2
3

USB1-DM
USB1-DP

9F25

7B02
H5PS1G83E

SDRAM
128Mx8

7B03
H5PS1G83E

SDRAM
128Mx8

7B01
H5PS1G83E

SDRAM
128Mx8

B02C HDMI_DV

RXC

VCC33

62
TXC_P
63
TXC_N
60
TX0_P
61
TX0_N
58
TX1_P
59
TX1_N
56
TX2_P
57
TX2_N

HDMIA-RXC+
HDMIA-RXCHDMIA-RX0+
HDMIA-RX0HDMIA-RX1+
HDMIA-RX1HDMIA-RX2+
HDMIA-RX23S0W
+3V3

W25
RXC_A_P
W26
RXC_A_N
V25
RX2_A_P
V26
RX2_A_N
U25
RX1_A_P
U26
RX1_A_N
T25
RX0_A_P
T26
RX0_A_N
W24
RREF

VDDL
VREF

1
2
19
18

R25

B02A FLASH

1P02

HDMI 1
CONNECTOR

9F26

USB-DM
USB-DP

R26

B01B

1E04
PR

PB

4
6
7

USB HUB

B02E CONROL

B02B MEMORY

ANALOGUE EXTERNALS B

+VDISP

XIO_D

VGA
CONNECTOR

9
10

3
2

1E05

OPTIONAL

4
6
7

CVBS1_OUT

VGA

10

67

B01I

15

ARX0ARXC+

IF_AGC

40

18

9
10

AF11

CVBS-MON-OUT1

HDMI
SWITCH

1
2
19
18

19

20

ARX2+

TUNER_N

AC13
AV1_R
AE13
AV1_G
AD13
AV1_B
AB15
CVBS_Y1

15

SCART1

3
4
6
7

HDMI 3
CONNECTOR

7E05
EF

11

16

AF12

AV1-R
AV1-G

AV1-BLK

1P04

PNX-IF-N

TUNER_P

1E01

1
2
19
18

HDMI SIDE
CONNECTOR

AE12

AD12

21

BANDPASS
FILTER

PNX-IF-P

OUT
4 IN
AGC CONTROL

DRX0-

PX4

LOUT4
3F79-1

ANALOGUE EXTERNALS A

EXT 1

PX3

LOUT3
B02I ANALOG VIDEO

VCC

15
11

9
10

TS-FE-DATA

TO DISPLAY

IF-P-DVBT2

1P05

49
40

SSB 3104 313 6519.x

AGC AMPLIFIER 7

*7EC1
SII9187BC
SII9287BC

4
6
7

I2C

PNX-IF-AGC

B04A

HDMI

7F75
UPC3221GV

7F70

B04D

64

2F74

SELECT-SAW
B02E
CONTROL

HDMI

IF-AGC

SAW 36MHZ17

B01H

49
50

TS-FE-VALID
4
TS-FE-SOP
3
5 TS-FE-CLOCK

A1 E2
A

A1 E2

A1 E2

VDDL
VREF

IF-OUT2

DVBT2-IFN
DVBT2-IFP

DVBT2
CHANNEL
DECODER

VDDL
VREF

IF-OUT1

1G51
51

24M

RF_AGC

RF IN

+5V-TUN-PIN
RF-AGC

5F70

MAIN HYBRID
TUNER

N.C.

50
53

TUNER

41

N.C.

7FJ0
CXD2820R

7FJ1

B01F

TS-FE-DATA

16

9R03-4

3 2

11

AGC

TS-DVBS-DATA

QM

73

PX2

R23 TNR_SER1_MIVAL
R22
TNR_SER1_SOP
T22
TNR_SER1_MICLK
T21 TNR_SER1_DATA

19

9R03-2

TS-FE-VALID
TS-FE-SOP
TS-FE-CLOCK

3 2

122
12

TS-DVBS-VALID
TS-DVBS-SOP
TS-DVBS-CLOCK

IM
XTAL
QP

9R03-1

78
75
74

D(16-23)

31

20
32
18

1FL5

16M

1R10

30

IP

VDDL
VREF

SAT IN

LOUT2

DVB-S
CHANNEL
8
DECODER

21

D(8-15)

DVB-S
TUNER

D(0-7)

1R01

TO DISPLAY

7R01
STV0903BAC

D(24-31)

7R02
STV6110A

MDI

PNX85537

DVBS-FE

PX1

LOUT1
CA-MDI(0-7)

B07A

MD0

A1 E2
DDR2-A(0-14)
+1V8
DDR2-VREF-DDR

*6000 SERIE MUX SII9187 NON INSTAPORT


7000 SERIE MUX SII9287 INSTAPORT
19100_811_110214.eps
110414

2011-Nov-04 back to

div. table

Block Diagrams

Q552.2E LA

9.

EN 103

9-11 Block Diagram Audio


AUDIO
B02

1P00
17

7F01
74LVC245APW
20

ADAC_1

122
12

19

QM

11

AGC

16

73

TS-DVBS-DATA

9R03-2
9R04

TUNER

+5V-TUN-PIN

MAIN HYBRID
TUNER

IF-OUT1
IF-OUT2

10
11

4 5F73

TUN-IF-P

TUN-IF-N

2F90

1
2

5F70

RF IN

1F75

2F74

B04D

HDMI

DVBT2-IFN

49

DVBT2-IFP

50

DVBT2
CHANNEL
DECODER

TS-FE-VALID
4
TS-FE-SOP
3
5 TS-FE-CLOCK

B04A

IF-P-DVBT2

B03C

1
2
19
18

HDMI SIDE
CONNECTOR

DRX2+

26

AE12
AF12

PNX-IF-N

AD12

B02D

1E01-1
3

AP-SCART-OUT-L

3EA7-1

AUDIO-OUT-L

AP-SCART-OUT-R

3EA7-4

AUDIO-OUT-R

DRX2DRX1+

25
24

DRX1DRX0+

23
RXD
22

DRX0-

21

4
6
7
9
10

DRXC+

20

12

DRXC-

19

1
2

20

ARX2+

72

ARX2ARX1+

71
70

PNX85500: AUDIO

7S05

ADAC(5)

AE6

ADAC(6)

AF6 ADAC_6

ARX1ARX0+

69
68 RXA
67

12

ARX0-

AUDIO-IN1-R

AF10

15

B04E

ANALOGUE EXTERNALS B
1E08

AUDIO IN
L+R

AUDIO-IN3-L

AE9

AUDIO-IN3-R

AF9

AIN3_L

VGA (OR DVI)


AUDIO

OPTIONAL

A-STBY

5D03

B01J

HEADPHONE

AUDIO-IN4-L

AD9

AUDIO-IN4-R

AC9

AB19

TEMP SENSOR + HEADPHONE

7EE0-2
B03A

A-PLOP

RESET-AUDIO

B04A

HEADPHONE
AMPLIFIER
5

ADAC3

ADAC(3)

AD6

ADAC(4)

IN-1

VO_2

AMP1

AMP2

B01C

IN-2

VDD

HEADPHONE
OUT 3.5mm

+3V3

USB HUB
+5V-USB1
1P08
1

B02E CONROL

USB_DN
USB_DP

R26

9F26

USB-DM
USB-DP

R25

2
3

USB1-DM
USB1-DP

9F25

B01B

7FL5
CY7C65631

FLASH

B02A FLASH

7F20
H27U4G8F2DTR-BC

17

USB
HUB

2
3

USB2-DM
USB2-DP

NAND_CE1
NAND_RDY1
NAND_WP_

XIO-D(00-07)
NAND-CE1n
E21
F21 NAND-RDY1n
NAND-WPn
A21

9
7
19

NAND
FLASH

VCC

AIN4_R

21

+5V
13

22
21,37

USB-WIFI-DDn
USB-WIFI-DDP

14
+3V3

USB 1 SIDE
CONNECTOR

+5V-USB2
1P07
1

9
10
5

18
XIO_D

AIN4_L

1328

SHUTDOWN
VO_1

AF7

1
ADAC4

AIN3_R

1E09

65

ARXC-

AIN1_R

21

66

ARXC+

ADAC_5

AE10 AIN1_L

SPEAKER R
1D38
1

7EE1
TPA6111A2DGN

IF_AGC

AUDIO-IN1-L

A-PLOP

7D03
STANDBY &
PROTECTION

TUNER_N

A-PLOP

B04B

B04E
PO_6

7E01

9
10

16

RIGHT-SPEAKER

15

SD

TUNER_P

SCART1

1
4
6
7
19
18

11

HDMI
SWITCH

1P04

HDMI 3
CONNECTOR

DETECT2

7EE0-1

1P05
1

7D11
MAINS SWITCH
DETECT

SPEAKER
WOOFER

B02D AUDIO

*7EC1
SII9187BCNU
SII9287BCNU

SPEAKER L
3

4 MUTE

PNX-IF-P

BANDPASS
FILTER

ANALOGUE EXTERNALS A

TS-FE-DATA

IF-P-DVBT2

IN-R

OUT-R

B02I ANALOG VIDEO

6 3F79-4

1735
1

LEFT-SPEAKER

22

B04E

AUDIO-MUTE-UP

7FJ0
CXD2820R

PNX-IF-AGC

HDMI

PO_7

AC19

SSB 3139 123 6519.x

AGC AMPLIFIER 7 3F79-1

SELECT-SAW
B02E
CONTROL

A-PLOP

A-PLOP

A-STBY

DVBT2

OUT
4 IN
AGC CONTROL

SAW 36MHZ17
7F70

10

B02G STANDBY

VCC

AE7

7D15

R23
TNR_SER1_MIVAL
R22
TNR_SER1_SOP
T22
TNR_SER1_MICLK
T21
TNR_SER1_DATA

TS-FE-DATA

7F75
UPC3221GV

2F78

TS-FE-VALID
TS-FE-SOP
TS-FE-CLOCK

9R03-4

B10A

1T01
TH2627

RESET-USBn

42

USB 2 SIDE
CONNECTOR

1F24
1
2
3
4
5

TO WIFI MODULE
(OPTIONAL)

B02G

BRX1BRX0+

5
RXB
4

4
6
7
9
10

BRX0-

BRXC+

12

BRXC-

1
2

DIGITAL
AUDIO
OUT

SSB 3139 123 6519.x


2
1
3

+3V3

SPDIF-OPT
SSB 3139 123 6519.x

1E07

+3V3

B02B MEMORY
SPDIF-OUT-PNX

AF5

SEL-HDMI-ARC

AF18

9,27,64

18

CRX2CRX1+

17
16

CRX1CRX0+

15
RXC
14

CRX0-

13

CRXC+

12

CRXC-

11

12
14

DDR2-D(0-31)

P0_4

ARC-eHDMI+

5EC2

HDMIA-RX0+
HDMIA-RX0HDMIA-RX1+
HDMIA-RX1HDMIA-RX2+
HDMIA-RX2-

eHDMI+

3S0W
+3V3

W24

7B00
H5PS1G83EFR

SDRAM
128Mx8

B02C HDMI_DV
W25
RXC_A_P
W26
RXC_A_N
V25
RX2_A_P
V26
RX2_A_N
U25
RX1_A_P
U26
RX1_A_N
T25
RX0_A_P
T26
RX0_A_N

HDMIA-RXC+
HDMIA-RXC-

62
TXC_P
63
TXC_N
60
TX0_P
61
TX0_N
58
TX1_P
59
TX1_N
56
TX2_P
57
TX2_N

DDR

DQ

VCC33

CRX2+

9
10

B05A

B02G STANDBY
8

1
4
6
7

SPDIF_OUT

SPDIF-OUT

7S09
2
&
1

SSB 3139 123 6495.x


+3V3-HDMI
1P02

HDMI 1
CONNECTOR

1E10

A1 E2

7B02
H5PS1G83EFR

SDRAM
128Mx8

A1 E2

7B03
H5PS1G83EFR

SDRAM
128Mx8

A1 E2

7B01
H5PS1G83EFR

SDRAM
128Mx8
VDDL
VREF

7
6

D(24-31)

BRX2BRX1+

VDDL
VREF

D(16-23)

VDDL
VREF

BRX2+

D(8-15)

HDMI 2
CONNECTOR

VDDL
VREF

19
18

1
2

1P03

19
18

B01H

9R03-1

D(0-7)

B01F

IM
XTAL
QP

TS-DVBS-VALID
TS-DVBS-SOP
TS-DVBS-CLOCK

OUT-L

-AUDIO-R

31

20
32
18

78
75
74

ADAC(2)

+24V-AUDIO-POWER

3 2

16M

1R10

30

5D07
10,12 5D08
1,3

PVCC_L

IN-L

SAT IN

ADAC_2

DVB-S
CHANNEL
8
DECODER

IP

21

+AUDIO-L

PVCC_R

7R01
STV0903BAC

DVB-S
TUNER

14

12

ADAC(1)

AD7

MDI

1R01

CLASS D
POWER
AMPLIFIER

7S05
LM324P

3 2

7R02
STV6110A

B02D AUDIO

MD0

CA-MDO(0-7)

BUFFER

1FL5

DVBS-FE

AUDIO

7D10
TPA3123D2PWP

B02A VIDEO STREAM


MDO(0-7)

CA-MDI(0-7)

B07A

B03A

7S00
PNX85537EB

+3V3

68P

CONDITIONAL
ACCESS

PNX85500: AUDIO

51
52
PCMCIA

B02D

PNX85500

+5VCA

18

24M

COMMON INTERFACE

PNX85537

B01A

A1 E2
DDR2-A(0-14)

+1V8
VREF_1
VREF_2

RREF

A2
V1

DDR2-VREF-DDR
DDR2-VREF-CTRL2
DDR2-VREF-CTRL3

*6000 SERIE MUX SII9187 NON INSTAPORT


7000 SERIE MUX SII9287 INSTAPORT
19100_812_110215.eps
110324

2011-Nov-04 back to

div. table

Block Diagrams

Q552.2E LA

9.

EN 104

9-12 Block Diagram Control & Clock Signals


CONTROL + CLOCK SIGNALS

Pin6 Pin5

Pin4

Pin3

Pin2

5
7
8

Pin8 Pin7

SDIO-DAT1

9
10
12

B02B MEMORY

DDR2-D(0-31)

DQ

W2
CC_DAT3
W6
CMD
W1
CLK
W5
DAT_0
W4
DAT_1
W3
DAT_2
U6
SDCD
V6
SDWP

SDIO-DAT2
SDIO-CDn
SDIO-WP

7B00
H5PS1G83EFR

SDRAM
128Mx8

SDRAM
128Mx8

F8 E8

F8 E8

CLK_N
CLK_P

7E10
LAN8710A-EZK
ETH-RXD
ETH-TXD

ETHERNET

SDRAM
128Mx8

ETH-RXCLK

AA3

20

ETH-TXCLK

AA2

B06C

TXCLK

F8 E8

B09A

7GA0
XC9572XL

NON DVBS CONNECTOR BOARD

B03D

PNX-SPI-CSBn

PNX-SPI-CLK
PNX-SPI-SDI

41

PNX-SPI-SDO

39

B02E CONTROL
RESET-ETHERNETn

F8 E8

B03B

SENSE+1V2

25M

1E70

AMBILIGHT CPLD

SENSE+1V1

4
19

SDRAM
128Mx8

DDR-CLK_N
DDR-CLK_P

N5
N4

B02H POWER
AF1
VDD_1V1
AA15
VDDA_1V2

RXCLK

7B01
H5PS1G83EFR

DDR2-A(0-13)

RXD
TXD

ETHERNET
CONNECTOR
RJ45

CPLD

40

B02G

1M59
1

22

AMBI-SPI-CLK-OUT

27

AMBI-SPI-SDO-OUT

23
29
30

AMBI-SPI-SDI-OUT_G1
AMBI-PWM-CLK_B2
AMBI-SPI-CS-OUTn_R2

4
6
8

31

AMBI-LATCH1_G2

20
19
28

AMBI-BLANK_R1
AMBI-PROG_B1
AMBI-LATCH2_DIS

11
12
13

32

AMBI-TEMP

14

TO AMBILIGHT
MODULE

DVBS-FE

B10A
B01F
B01F
B02E

B01A

FLASH

9R03-1

TS-FE-SOP
TS-TS-VALID

DVBT2

7FJ0
CXD2820R

DVBT2-IFN

49

DVBT2-IFP

50

TS-FE-VALID
4
TS-FE-SOP
3
DVBT2
CHANNEL 5 TS-FE-CLOCK

DECODER 7

TS-FE-DATA

RESET-SYSTEMn

COMMON INTERFACE
7F00

1P00
1
20

MOCLK

CA-MOCLK

K24

62
63

MOVAL
MOSTRT

CA-MOVAL
CA-MOSTRT

L23
L22

VS_2
MOVAL
MOSTRT
MDI

7F01

VCC

12,37

+3V3

MDO(0-7)

COMMON INTERFACE

NAND
FLASH

PCMCIA

CONDITIONAL
ACCESS

GPI0_7

PXCLK54
PNX-SPI-CS-BLn

AC5
V22

MDO

CA-MDO(0-7)
7F02
7F03

B02A FLASH

CA-A(00-14)

XIO-A(0-15)

XIO_A

7F04
7F05

CA-D(0-7)

26

BL_PWM

AD5

BACKLIGHT-PWM

B02E

9GA0

VIO
BACKLIGHT-PWM_BL-VS

B03C

OPTIONAL

B01C

PNX85500: MIPS

USB HUB
+5V-USB1
1P08
1

USB_DN
USB_DP

9F26

USB-DM
USB-DP

R26
R25

2
3

USB-DM1
USB-DP1

9F25

4
RESET-SYSTEMn
SELECT-SAW

AE4
RESET_SYS
U23
GPI0_11

B04C

B01F

7FL5
CY7C65631

ETHERNET + SERVICE

+5V-USB2
1P07
1

USB
HUB

10
5

18

2
3

USB-DM2
USB-DP2

1E06
GPI0_2
GPI0_3

RXD1-MIPS

Y23

TXD1-MIPS

Y24

21
UART
SERVICE
CONNECTOR

3
1

SIDE USB
CONNECTOR

SSB 3139 123 6495.x

B01K B02G

17

+5V
13

22

SIDE USB
CONNECTOR

1F24
1
2
3
4
5

USB-DM3
USB-DP3

14

SSB 3139 123 6519.x

XIO_D

XIO-D(00-15)

43
3
VCCIO

B02G

CA-MDI(0-7)

7F20
H27U4G8F2DTR

CLK_54_OUT

52

T21
TNR_SER1_DATA
T22
TNR_SER1_MICLK
R22
TNR_SER1_SOP
R23
TNR_SER1_MIVAL

TS-FE-CLOCK

3 2

SENSE+1V0-DVBS

TS-FE-DATA
9R04

9R03-2

TS-DVBS-DATA
73
74 TS-DVBS-CLOCK
MULTI
11
TS-DVBS-SOP
75
STANDARD
7 DEMODULATOR 78 TS-DVBS-VALID
8 FOR SAT DIG TV 62
RESET-DVBS

12

3 2

122

QP
QM
IP
IM

20

XTAL

24M

18
19
21

B02G
9R03-4

PNX85537

32

SATELLITE
TUNER

B08A

B02A VIDEO STREAM

7R01
STV0903BAC

7R02
STV6110A

B01B

7B03
H5PS1G83EFR

ETHERNET + SERVICE
1N00

B07A

7B02
H5PS1G83EFR

1FL5

B04C

SDIO-DAT3
SDIO-CMD
SDIO-CLK
SDIO-DAT0

D(24-31)

Pin1

Pin9

1
2

DDR

D(16-23)

1P09

SD-CARD
CONNECTOR

B05A

PNX85500

7S00
PNX85537EB
B02E ETHERNET

D(8-15)

B02A

SD-CARD

D(0-7)

B01D

B02G

68

PNX85500: STANDBY CONTROLLER

B01E

PNX85500-CONTROL

XIO-D(00-07)
B02G STANDBY

GPIO_10

9CH0

BOOST-PWM

V23

BACKLIGHT-BOOST

B03C

B06C

DC / DC

1M19
1

LIGHT-SENSOR

2
3
4
TO IR / LED BOARD AND
KEYBOARD CONTROL

5
6

AE26

RC
LED-2

9U41

P5_1
P1_0

LED2

AD19
AC25

LED1

AD26

PWM_0

PWM_1

7U43

+3V3-STANDBY
LED-1

SPI_CLK
P6_5
SPI_CSB
SPI_SDO
SPI_SDI
P3_0

KEYBOARD

7
8

P3_1
P1_7
RESET_IN
P6_4

AE22
AF23
AE23
AF25

PNX-SPI-CLK

PNX-SPI-WPn

PNX-SPI-CSBn
PNX-SPI-SDO
PNX-SPI-SDI

1
5
2

DETECT2
RESET-SYSTEMn
AV1-BLK

B03C
B02E
B04A

AA22

P3_2
P3_3

AB22
AD22

XTAL_IN

P3_5
XTAL_OUT

AV1-STATUS

AE25

LCD-PWR-ONn

AC20

B04A

CADC_2
P1_1

B03H

P2_0

P0_4
P2_2

19
18

1
2

B04D HDMI

4x HDMI
CONNECTOR

TO PIN:
1P02-13
1P03-13 PCEC-HDMI
1P04-13
1P05-13
ARX-HOTPLUG
1P02-19
BRX-HOTPLUG
1P03-19
CRX-HOTPLUG
1P04-19
DRX-HOTPLUG
1P05-19

P2_7

7EC0
EF

CEC-HDMI

AF19

7EC1
SII9187ACNU
SII9287BCNU
31
35
41
45

HDMI
SWITCH

P1_2

B02C HDMI_DV
RX

HDMIA-RX
3S0W
+3V3

W24

P0_1
P0_3
P2_6
P2_3
P0_6
P0_7

1F51
3
1 LEVEL SHIFTED
2
FOR
DEBUG USE
4
ONLY
5

SDM
FF29
SPI-PROG

7S20
NCP303LSN28G
2
3

INP OUTP
GND

AD18

RESET-USBn

AD21

ENABLE-3V3n

AF18
AE20
AA18
AE18

SEL-HDMI-ARC
LAMP-ON
RESET-DVBS
RESET-ETHERNETn

AC21

POWER-OK

AF20

STANDBY
RESET-AUDIO
AUDIO-MUTE-UP

RREF

+3V3-STANDBY

FF04

AE17

AB19
AC19

TXD-UP

AF22

AF17

VCC

512K

SDM
RESET-STBYn
SPI-PROG
+3V3-STANDBY

PNX85500: STANDBY CONTROLLER

FLASH

RXD-UP

AE21
AF21
AB20
AA26

1S02

B02G

P5_0

AD23

+5V

AF24

RESET-STBYn

B01C

B03C

+12V
+3V3-STANDBY

B02D
B07A
B04C

B06C
B01E

RES

DC / DC

CONTROL

B03C

CONNECTORS COMP

54M

B09A

7F52
M25P05-AVMN6P

BACKLIGHT-PWM_BL-VS
BACKLIGHT-BOOST

ENABLE-3V3-5V
ENABLE-1V8
DETECT2

B03E
B03B B03D
B02G B03A

1M95
9
10
TO
11 POWER SUPPLY
12
2

B04E
B03A

19100_813_110216.eps
110318

2011-Nov-04 back to

div. table

Block Diagrams

Q552.2E LA

9.

EN 105

9-13 Block Diagram I2C


IC
B01E

PNX85500: MIPS

B01J

PNX85500-CONTROL

DDC_A_SCL

3F65

TXD-UP

3F64

uP
LEVEL SHIFTED
FOR DEBUG
1
USE ONLY

3S84

3S83

Y24

B02I

B02I

DRX-DDC-SDA

44

DRX-DDC-SCL

RXD1-MIPS

3E53-4

3E53-3

TXD1-MIPS

3E53-2

3E53-1

PNX85500: ANALOG VIDEO

47

UART
SERVICE
CONNECTOR

EDID
SW

SDRAM
128Mx8

48

VGA-SDA-EDID-HDMI

9FC1

VGA-SCL-EDID-HDMI

9FC3

3S5V-1

VGA-SDA-EDID

9FC2

3S5V-3

VGA-SCL-EDID

9FC4

D(0-7)

3R14

3R15

3FJH

3FJJ

3T51

3T61

3R01

3R00
1P05
16

HDMI
CONNECTOR
SIDE

OPTIONAL

1E05
12
15

VGA
CONNECTOR

RES

+3V3

B02B
MEMORY

DDR2-A(0-13)

DDR2-D(0-31)

DQ

B24

3S60

A23

3S61

4_SDA
4_SCL

B01F

RES

TUNER

SDA-TUNER

3F75

TUN-P7

SCL-TUNER

3F76

TUN-P6

ERR
18

1T01
FA2327

D(24-31)

SDRAM
128Mx8

ERR
31

ANALOGUE
VIDEO

7B03
H5PS1G83EFR

D(16-23)

7B02
H5PS1G83EFR

DVBT
CHANNEL
DECODER

+5V-VGA

AD24

3S6F

SDRAM
128Mx8

1
2

+5V-EDID

1E06

LNB
CONTROLLER

ERR
36

15

AD25

3S6G

7B01
H5PS1G83EFR

D(8-15)

7B00
H5PS1G83EFR

HDMI

OPTIONAL
ETHERNET + SERVICE

7FJ0
CXD2820R

VGA

VGA_EDID_SDA
VGA_EDID_SCL

1
2

+3V3
43

7T50
LNBH23QT

DIN-5V

HDMI
CONNECTOR 1

B01I
B04C

Y23

3FE8

3FE9

3EC3

3EC1-1

3EC1-3

19
18

15

DDCA-SCL

GPIO_2

SDRAM
128Mx8

CRX-DDC-SCL

B01H

1
2

RXD-UP

HDMI_DV

DDR

16

+3V3

MAIN
SW

GPIO_3

40

DDCA-SDA

Y26

1P02
CRX-DDC-SDA

12

30

SATELITE
TUNER

RES

10

Y25

HDMI
CONNECTOR 2

1F51
3

RES

DDC_A_SDA
XIO_D

13

29

15

B02C

39

DEBUG
ONLY

RES

7R02
STV6110A

B02A

AF21

1F52
3

SCLT

11

P3_1

FLASH

B05A

DVBT2

P3_0

7F20
H27U4G8F2DTR

XIO-D(00-07)

B10A

AE21

MAIN NVM
SW

3S1H

3S1G

FLASH

3F62

15

SDAT

19

ERR
28

19
18

+3V3-STANDBY

3F63

BRX-DDC-SCL
CIN-5V

RES

ERR
35

16

3FBF-1

3S2G

BRX-DDC-SDA

18

CHANEL DEC
DVBS

1P03

34
EEPROM
(NVM)

+3V3RF
97

7R01
STV903BAC

DEMODULATOR

3FBF-2

AC24

33

7FE0
TC90517FG

3FC2

3S2F

MC_SDA

15

3FC1

AC23

ERR
23

98

19
18

ERR
53

MC_SCL

FLASH
(4Gx16)

DVBS-SUPPLY

1
2

ERR
15

RES

B01B

ERR
42

16

ARX-DDC-SCL

19
18

STANDBY
SW

7F58
M24C64

45

HDMI
CONNECTOR 3

3ECA-2

PNX-SPI-CSBn
PNX-SPI-SDO
PNX-SPI-SDI

+3V3-STANDBY
STANDBY

ARX-DDC-SDA

BIN-5V

3ECA-4

1
5
2

AF24
SPI_CLK
AE22
P6_5
AF23
SPI_CSB
AE23
SPI_SDO
AF25 SPI_SDI

30

HDMI
MUX

46

1P04

3ECP-1

PNX-SPI-WPn

TEMP
SENSOR

29

3ECP-3

PNX-SPI-CLK

PNX85500: STANDBY
CONTROLER

3S6V

512K

SCL-UP-MIPS

AIN-5V
54

7EC1
SII9287B
SII9187A

7FD1
LM75BDP

SDA-UP-MIPS

3S6W

FLASH

B02G

B02G

53

3ECA-1

3S57

3F60

1_SCL

3ECA-3

C26

1_SDA

3F59

C25

3S56

3S69

CONTROL

3S6A

ERR
13

PNX85537

VCC

B08B

DVBS-FE

SCL-SSB
+3V3

B07A

TUNER BRAZIL

SDA-SSB

3EC5

3S5Z

3FD3

3_SCL

+3V3-STANDBY

B01K

HDMI

3ECU-4

3S5Y

A24

3_SDA

3ECU-2

B25

3S6D

B02E

7F52
M25P05-AVMN6P

B04D

TEMP SENSOR +
HEADPHONE

+3V3

7S00
PNX85537EB

3FD4

B02E

PNX85500: CONTROL

3S6E

B01E

MAIN
TUNER
ERR
34

ETHERNET + SERVICE

A25

3S5W

3S6B

3S58

22
23
24
25

ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)
ETH-TXD(3)

AA1
AA4
AB1
AB2

20

ETH-TXCLK

AA2

AA3

9S11

SCL-DISP

3G2Y

49

LVDS
CONNECTOR

3C83

1M71
3

1T02
3

3124

SDA-TEMP1

3C81

3123

SCL-TEMP1

+3V3

ERR
14

RXD_2
RXD_3
RXCLK

W21
GPIO_2

TXD_2
TXD_3

50

SCL-SET
+3V3

RXD_0
RXD_1

TXD_0
TXD_1

3G2W

GPIO_3

W22

RXD2-MIPS
TXD2-MIPS

7S01
PCA9540B
2 CHAN.
MULTIPLEX.
ERR
24

ERR
64

3S66

AC1

ETH-RXD(2)

SDA-DISP

3S68

ETH-RXD(3)
ETH-RXCLK

2_SCL

9S12

3S65

Y5
Y6
AB4

SDA-SET

3S67

ETH-RXD(0)
ETH-RXD(1)

3S80

11
10
9

VIDEO OUT - LVDS

1G51

2_SDA

ETHERNET
CONNECTOR
RJ45

B26

3S6C

7E10
LAN8710A-EZK

ETHERNET

B06B

+3V3

3S81

B04C

B09A

TS1

DVBS CONNECTOR BOARD

TEMP SENSOR

TXCLK

RES
9S13

SDA-BL

9S10

SCL-BL

7104
LM75ADP
TEMP
SENSOR

OPTIONAL

2011-Nov-04 back to

div. table

SW

Programmable via USB

19100_814_110217.eps
110309

Block Diagrams

Q552.2E LA

9.

EN 106

9-14 Supply Lines Overview


SUPPLY LINES OVERVIEW

8
9

8
9

HDMI SIDE
CONNECTOR

+12V_AL

STANDBY
GND1
GND1
GND1
+12V3

2
3
4
5

STANDBY

B02G

B01J

+12V
+24V-AUDIO-POWER

7
8

T 3.0A

9
10

9
10

BL-DIM1
11
BL-I-CTRL
12
POK

11
12

LAMP-ON
B02G
BACKLIGHT-PWM_BL-VS
B06C
BACKLIGHT-BOOST
B01E
POWER-OK
B02G

13

13

14

14

+24V

GND1

TEMP SENSOR + HEADPHONE

B03B

B04D
12V/1V1
COVERSION

B03e

B03e

+3V3

+1V8
+1V2

7UA3

B02g,h,
B03e,B10a

+5V

3U16
3U15

DDR2-VREF-CTRL3

3F01

3S06

DDR2-VREF-CTRL2

+2V5-LVDS

CUA0

+5V5-TUN

+3V3

+12V

+3V3

+3V3
+5V

B03d

B03e

3F32

B03e

PNX85500: AUDIO

+2V5

+2V5

+3V3

+3V3
3S11

+5V-USB1
+5V-USB2

IN OUT
COM

+T
+24V-AUDIO-POWER

B03c

B01D

3S0Z

SD-CARD

3F40

B02E

B03E

+2V5-AUDIO

B02h

+1V1

+12V

+24V-AUDIO-POWER
5UD3

IN OUT
COM

+24V-AUDIO-VDD

5UD2

+3V3

5UD1

+5V5-TUN

IN OUT
COM

6UD0

+5V

+3V3-STANDBY

B03e

B02G

+3V3-STANDBY

PNX85500: STANDBY CONTROLLER

T 2.0A

1UM0

B09a

TUNER

1G03

B03d

9F71

B02H

+5V-TUN-PIN

B10a
B03b
B03d
B03b

B01G

TOSHIBA SUPPLY

+3V3

B03d
+3V3

7FA3
B03e
IN OUT
COM

B03e

+3V3

+12V

+12V

5FA3
5FA4

+1V2-BRA-VDDC
+1V2-BRA-DR1

+1V2

+1V2

+1V8

+1V8

B03c

+3V3

+2V5

+2V5

B03c

+2V5-LVDS

B03d
B01k

+3V3

+3V3
+VDISP

B01k

+3V3-STANDBY

B03e

B03d

+1V2

B06C

5FJ3

+2V5-DVBT2-A

5FJ4

+2V5-DVBT2-X
+1V2

AMBILIGHT CPLD

+1V2-FE
5FJ5

+1V2-DVBT2-C

5FJ6

+1V2-DVBT2-M

5FJ7

+1V2-DVBT2-P

+3V3
VINT
VIO

B01f

+5V-TUN-PIN

+5V-TUN-PIN
SSB 3139 123 6519.x

B06D

SPI-BUFFER
+3V3

+3V3

+3V3-STANDBY
+12VD

B07A

+3V3-STANDBY
+12VD

7UU0

+VDISP-INT

DVBS-FE

+1V-DVBS

B08a
B06a

+1V-DVBS

+2V5-DVBS

+2V5-DVBS

B08a

+2V5-LVDS
+3V3

+2V5-DVB
IN OUT
COM

VIDEO OUT - LVDS

B03e

VDISP - SWITCH

+3V3
B03e

+3V3-DVBT2-R

5FK1

B06B

+3V3

+2V5-AUDIO

+3V3
+3V3-DVBT2-D

7FK1

5GA1

+3V3

B03H

+1V1

TO
AMBILIGHT
MODULE

DVBT2

+3V3

5FJ2

FAN - CONTROL

PNX85500: POWER

+1V1

+2V5-AUDIO

B02d

B10A

5FJ1

5GA0

B03c

+5V-TUN

B06b

+VDISP

T 3.0A

B03e

+5V-TUN

+VDISP-INT

+3V3

B03e

B03G

10

V-AMBI

9FK6

V-AMBI

+5V

B03c

1M59
21

T 2.0A

DISPLAY INTERFACING-VDISP

B03e

B01F

+24V

DDR2-VREF-DDR

+VDISP

T 1.0A

+3V3-STANDBY

ONLY 7000 SERIES

1C86

B03b

+1V1

+3V3-STANDBY

+24V

+1V8

+3V3
5UM1

+1V1

B03b
+5V

B03d
B01,a,c,e,k,
B03c,d,e,
B04a,b,d,
B09a

B06a
+3V3

+3V3-STANDBY

+12V_AL
1C87

B03c

+1V8

TEMPSENSOR + AMBILIGHT

+3V3

+3V3

+12V_AL

DDR

B01,a,b,c,d,e,
g,j,k,
B02a,c,d,e,h,
B03c,f,g,h,
B04a,c,d,e,
B06b,c,d,
B08a,B09a,
B10a

+12V

PNX85500: CONTROL

B03e

TO
IR/LED
BOARD

B03h

7UD1

B03F

+3V3
+3V3-STANDBY

+VDISP-INT

+1V1
B03b
B03c

B03c

B01E

3B20

+3V3

+3V3-STANDBY

+5V

DC / DC

PNX85500: MIPS

+3V3

B03e

+3V3-STANDBY

+5V

B03e

HEADPHONE

+2V5-REF

5UD0

+3V3-SD

+3V3-STANDBY

TEMP
SENSOR
(OPTIONAL)

B03c
DIN-5V

B03f

+3V3

+T

CIN-5V

+3V3
1M71
4

B03c

B03b

7UD0

+3V3
B03e

1P02
18

B03e

+3V3

B06A

+3V3-ARC

7S08

+T
3FL2

BIN-5V

+3V3-STANDBY

+12V

7UA0
VOLT.
REG.

3UA0

+5V

B02h

B04E

B05A

ENABLE-1V8

USB HUB

B03e

1P03
18

CONNECTORS COMP

+3V3

B01f
+3V3
B03c

B02D

B08a

+5V-TUN

7UA6

B03e

B01C

+V-LNB

B03c

PNX85500: DIGITAL VIDEO IN

+3V3

B03e

+12V

+V-LNB

1M19 1M20
5
6

+5V5-TUN

B03e

+3V3

HDMI 2
CONNECTOR

AIN-5V

B03e

B02C

+3V3-DVBS

+12V

B01h

B02d,h

+5VCA

FLASH

B08a

B09A

1P04
18

DIN-5V

+2V5

IN OUT
COM

+T

B01B

DVBS-SUPPLY

7UC0

+1V8
3S20

+5V

B03e

+3V3

B07a

+5V

HDMI 1
CONNECTOR
+5V

B03e

PNX85500: SDRAM

+1V8

B03b

+5V-VGA

HDMI 3
CONNECTOR

+3V3

B03e

B08B
B03c

+12V

B02B

+3V3-HDMI

+5V-VGA

B03b

+2V5-DVBS

+V-LNB

+3V3-DVBS

DC / DC

IN OUT
COM

+3V3-STANDBY

B03c

+5V

B03c

5EC0

+5V

B07a,B08b

7T01

B08b

B02h,g,B03e +3V3-STANDBY

+5V

COMMON INTERFACE

B07a
+3V3-DVBS

+3V3

+5V-EDID

B03e

5T01 +1V-DVBS

HDMI

+3V3

B03e

+3V3

IN OUT
COM

12 5T04

+1V1

5U01

+1V8

+3V3

5T00

+3V3-ET-ANA

B03e

+2V5-BRA

PNX85500: NANDFLASH
CONDITIONAL ACCESS

+5V-DVBS

7T00

Dual
N-Synchr
Converter

IN OUT
COM

B01I

B03D

+3V3

5E08

7FE3
B08a,B09a

+24V

7T03
1 TPS54283PWP
3 5T03

+3V3

B02b,h,B03d,
B05a

23

+3V3-BRA-FLT

IN OUT
COM

+3V3

ETHERNET + SERVICE

+5V
5FE9

B02A

B01A

+5V
+3V3

B03e

7U04

+3V3-BRA

+5V

+5V

+3V3

+1V8

5U00

7U01

+3V3

5FE4

+3V3
+24V

B03c

ANALOGUE EXTERNALS B

+3V3

B04C

12V/1V8
COVERSION

7U02-1

+1V2-BRA-DR1

5FE7

B03e

DVBS-SUPPLY

7T02

12
Dual
Synchronous
7U02-2
Step-Down
Controller
14

+1V2-BRA-VDDC

+3V3

+24V

+5V

+5V

B03e

TUNER BRAZIL

+1V2-BRA-DR1

B03e

+3V3

+5V

+12V

+12V

B03c
+3V3

+1V2-BRA-VDDC

B03e

+3V3

B03e
+3V3-STANDBY

B01g
B03b,d,e,g,
B08b,B09a

B08A

B03e

B01g

B02d,B03a

+3V3

B03e

DC / DC

7U03
TPS53126PW

B03h
+12VD

+AVCC

+3V3-STANDBY

+12VIN

7
8

BL-ON-OFF

B04d

B01e,B02e,
g,h,B03a,b,h,
B04d,e,B09a

B03h

+VSND
GND1

+5V-VGA

+3V3

B01K

1U40

+24V-AUDIO-POWER

B04B

B03c

B03e

2
3
4
5

1E05
9

+12VIN

+3V3-STANDBY

+24V-AUDIO-POWER

ANALOGUE EXTERNALS A

VGA

VGA
CONNECTOR

B02E

1M95
1

B04d

B04A

+3V3-STANDBY

3D09

B01I
3D-LR

AUDIO

+3V3-STANDBY

B03c
B03c

GND_AL

PSU
1M95
1

DIN-5V

B09a

ONLY 8000 SERIES

3V3SB

1P05
18

5T02

HDMI

6EC1

N.C.
GND1
+12V3

B01H

2
3
4
5
6

B03A

DC / DC

1M99
1

5U02

B03C
1M99
1
GND1
2
+12V3
3
GND1
4
+12V3
5
GND1
6
+12V3

7UU2
LCD-PWR-ONn

+3V3-STANDBY

B03c

+3V3-DVBS

+3V3-DVBS

B08a
5R00

+3V3-DEMOD

5R01

+3V3RF

19100_803_110208.eps
110415

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 107

10. Circuit Diagrams and PWB Layouts


10-1 B01 313912364954
Common Interface

Common Interface

+3V3

3F01
+5VCA

19

0R3

3F02

CA-MOCLK
CA-MOVAL
CA-MOSTRT

IF01

3F03-1

IF02
3
4
5
6
7
8
9

8
100R

7
100R

CA-CD2n
CA-DATAENn

100R
3F03-2 2

IF03

CA-CD1n

3EN1
3EN2
G3
1
2

18

MOCLK

17
16
15
14
13
12
11

MOVAL
MOSTRT

CA-DATADIR

MOCLK

MOVAL

10
19

MDO1
RES
MDO2

20

100n

MDO3

3EN1
3EN2
G3

3F04-1 1

8 100R

2
IF06

CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7

3F04-3 3
3F05-1 1
3F05-3 3

3F04-2
6 100R
3F04-4
8 100R
3F05-2
6 100R
3F05-4

7 100R

5 100R

7 100R

5 100R

3
4
5
6
7
8
9

1
2

18

MDO0

MDO5
17
16
15
14
13
12
11

MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7

3F08-2

3F10-1

MDO6
MDO7

3F10-2

3F12

CA-RDY

10

IF07

CA-WAITn
+3V3

CA-INPACKn
2F03

15-BIT ADDRESS
3EN1
3EN2
G3
18

XIO-A01
XIO-A02
XIO-A03
XIO-A04
XIO-A05
XIO-A06
XIO-A07

17
16
15
14
13
12
11

1
2

CA-VS1n

1
19

CA-ADDENn

CA-A00

3
4
5
6
7
8
9

CA-A01
CA-A02
CA-A03
CA-A04
CA-A05
CA-A06
CA-A07

10

XIO-A00

CA-WP

100n

20

7F02
74LVC245A

RES

10K
2 3F11-2 7
10K
3F11-3
3
6
10K
4 3F11-4 5
10K
8 3F11-1 1
10K

17
16
15
14
13
12
11

20
1
2

1
19

CA-ADDENn

CA-A08

3
4
5
6
7
8
9

CA-A09
CA-A10
CA-A11
CA-A12
CA-A13
CA-A14

10

XIO-A09
XIO-A10
XIO-A11
XIO-A12
XIO-A13
XIO-A14

RES

100n

3EN1
3EN2
G3
18

+3V3
2F05

8-BIT DATA
3EN1
3EN2
G3
18

XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07

17
16
15
14
13
12
11

1
2

CA-DATADIR

19

CA-DATAENn

CA-D00

3
4
5
6
7
8
9

CA-D01
CA-D02
CA-D03
CA-D04
CA-D05
CA-D06
CA-D07

10

XIO-D00

RES

100n

20

7F04
74LVC245A

+3V3
2F06

CONTROL
7F05
74LVC245A

XIO-D09
XIO-D08
XIO-OEn
XIO-WEn
XIO-D14
XIO-D15
CA-WAITn

18

1
2

17
16
15
14
13
12
11

RES

100n

3EN1
3EN2
G3
XIO-D11

IF08

+5VCA

+3V3

1P00

+5VCA
2F04

XIO-A08

+3V3

CA-D03
CA-D04
CA-D05
CA-D06
CA-D07
CA-CE1n
CA-A10
CA-OEn
CA-A11
CA-A09
CA-A08
CA-A13
CA-A14
CA-WEn
CA-RDY

+3V3

7F03
74LVC245A

IF04

8
10K
7
10K
3F10-3
3
6
10K
3F10-4
4
5
10K

MDO4

IF05
CA-MDO0

3F08-1

1 3F09-1 8
10K
2 3F09-2 7
10K
3F09-3
3
6
10K
3F09-4
4
5
10K

MDO0

7F01
74LVC245A
1

+3V3

8
10K
7
10K
3F08-3
3
6
10K
3F08-4
4
5
10K

+3V3
2F02

B01A

100K

3F07-4

5
10K
3F07-2
2
7
10K
3F07-3
3
6
10K
3F07-1
1
8
10K

CA-ADDENn

MOSTRT

20

22u 16V

RES 2F01

+T

3F06

CA-RST
RES

100n

20

7F00
74LVC245A
1
+5V

2F00

TRANSPORT STREAM FROM CAM

1
19

CA-ADDENn

CA-REGn

3
4
5
6
7
8
9

CA-CE1n
CA-CE2n
CA-OEn
CA-WEn
CA-IORDn
CA-IOWRn
XIO-D10

CA-MIVAL
CA-MICLK
CA-A12
CA-A07
CA-A06
CA-A05
CA-A04
CA-A03
CA-A02
CA-A01
CA-A00
CA-D00
CA-D01
CA-D02
CA-WP

CA-CD1n
MDO3
MDO4
MDO5
MDO6
MDO7
CA-CE2n
CA-VS1n
CA-IORDn
CA-IOWRn
CA-MISTRT
CA-MDI0
CA-MDI1
CA-MDI2
CA-MDI3
+5VCA
CA-MDI4
CA-MDI5
CA-MDI6
CA-MDI7
MOCLK
CA-RST
CA-WAITn
CA-INPACKn
CA-REGn
MOVAL
MOSTRT
MDO0
MDO1
MDO2
CA-CD2n
71
72

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70

1X07
REF EMC HOLE

1X04
EMC HOLE

1X08
REF EMC HOLE

1X01
REF EMC HOLE

92789-055LF

SPB SSB TV550


2K11 4DDR EU

10

B01A

2010-12-10

3139 123 6495


19100_001_110114.eps
110114

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 108

Flash

Flash

B01B

12

7F20
H27U4G8F2DTR-BC

37

100n

100n
2F21

2F20

+3V3

VCC

[FLASH]
4G 16
3F20-1 1

3F20-3 3

3F21-1 1

3F21-3 3

100R
3F20-2
100R
3F20-4
100R
3F21-2
100R
3F21-4

100R

100R

100R

100R

3F22-2
+3V3

XIO-OEn
XIO-WEn
NAND-WPn

3F23
3F22-4

16
17
9
8
18
19
7

100R
3F22-3 3
10K
3F22-1 1
5 100R

100R

100R
IF22

3F24

+3V3

NC

2K2

CLE
ALE
CE
RE
WE
WP
R
B

IF23
VSS

13

3F19

10K

NAND-RDY1n

0
1
2
3
IO
4
5
6
7

IF21

NAND-CE1n
NAND-CLE
NAND-ALE

29
30
31
32
41
42
43
44

36

XIO-D00
XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07

1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
25
26
27
28
33
34
35
38
39
40
45
46
47
48

+3V3

B01B

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_002_110114.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 109

USB Hub

B01C

USB Hub

B01C
IF44

100n

2F25

+3V3

26
11

IF32
+3V3
3F30
3 3F31-3 6
10K

IF41

12K IF40

IF39
4 3F31-4 5

31
30
27
35
22
24
25

100n

100n
2F33

100n
2F32

100n
2F31

100n
2F30

1u0
2F29

2F28

IF35

OSC1
USBDP_DN1|PRT_DIS_P1
USBDM_DN1|PRT_DIS_M1
BC_EN1|PWRTPWR1

13
2
1
12

3F37

9F25

USB-DP2

USB-DM

9F26

USB-DM2

RES 9F29

USB-DP3

RES 9F30

USB-DM3

10K

IF36

RESET
OSC2
USBDP_DN2|PRT_DIS_P2
USBDM_DN2|PRT_DIS_M2
SUSP_IND|LOCAL_PWR|NON_REM0BC_EN2|PWRTPWR2
TEST

DP
USBUP
DM
VBUS_DET

OSC3
USBDP_DN3|PRT_DIS_P3
USBDM_DN3|PRT_DIS_M3
BC_EN3|PWRTPWR3

RBIAS
SDA|SMBDATA|NON_REM1
SCL|SMBCLK|CFG_SEL0
HS_IND|CFG_SEL1

NC

17
4
3
16

USB-OC2n
USB-DP2
USB-DM2

+5V

IF37
19
7
6
18

USB-OC3n
USB-DP3
USB-DM3

8
9
20
21

GND_HS

3F34-4

FF33

+5V-USB2

100K
3 3F34-3 6

USB-OC2n

10K
VIA
38
39
40
41

IF31

28

XTALOUT

37

USB-DP
USB-DM

IF42

10K

XTALIN|CLKIN

USB-DP

0R3

32

+3V3

3F32

IF30

33

VDD_3V3

USB HUB

+T

10p

2F35

IF33

RESET-USBn

3F31-2

34

CR PLL
FILT

IF34

36
23
15
5
10
29

1u0

7F25
USB2513B-AEZG

24M

10p

3F35

10K
2F34

4
2

1F25

14

3F28

+3V3

1M0

2F26

100n
2F27

IF43

+3V3

3F36

2
USB-OC3n

100K
3F34-2

100K

10K

3F34-1

SIDE USB

100K

1P08
USB-DM2
USB-DP2

+5V-USB2

FF36
FF37

FF32

1
2
3
4 IF45

5401

FF38
USB-DM3
USB-DP3

+5V

FF39

FF30
FF31

RES
1F24
1
2
3
4
5

6
502382-0570

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_003_110114.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 110

SD Card

SD-Card

B01D

3F40
+3V3
22u 16V

+T
2F40

B01D

FF45

+3V3-SD

0R3

+3V3

3F41-4

IF47

47K

3F41-3

SDIO-DAT3

SDIO-DAT3

SDIO-CMD

SDIO-CMD

3F44-2

FF47

100R

47K

3F43-3

1P09-1
6

FF48

100R

3F45 RES

SDIO-CLK

SDIO-CLK

3F44-1

+3V3-SD
8
FF49

100R

10K
2 3F41-2 7

SDIO-DAT0

47K

1 3F41-1 8

1 3F42-1 8

47K

SDIO-DAT0

SDIO-DAT1

SDIO-DAT1

SDIO-DAT2

SDIO-DAT2

47K

2 3F43-2 7

FF41

100R

1 3F43-1 8

3 3F44-3 6

100R

FF42

3F42-2

FF46

SCDA7A0200

1P09-2
7

SDIO-CDn

SDIO-CDn

FF44

SDIO-WP

SDIO-WP

FF50

47K
3 3F42-3 6

14
16

FF43

100R

13
15

1
2
3
4
5
6
7
8
9

10
11
12
SCDA7A0200

47K

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_004_110114.eps
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2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 111

PNX85500 Control

PNX85500 Control

B01E

+3V3-STANDBY

10K

3F67

3F66

IF50
5

512K
FLASH C

BACKLIGHT-BOOST
7F53 RES
PDTA114EU

PNX-SPI-SDO
IF52

6
IF53
1

PNX-SPI-CSBn
IF54

HOLD

+5V

PNX-SPI-CLK

PNX-SPI-WPn
+3V3-STANDBY
FF29

VSS

IF55

BOOST-PWM

IF61

47K

+3V3

+3V3

3F68 RES

PNX-SPI-SDI

3F52

7F52
M25P05-AVMN6

VCC
IF51

+3V3

100n
RES

100p

2F52

2F49

+3V3-STANDBY

10K
RES

+3V3-STANDBY

10K

7F54-1 RES
BC847BPN(COL) 6

7F54-2 RES
BC847BPN(COL)

SPI-PROG

IF56
4

IF57

2
1

FF04

IF62
SDM

FF58

1K0
RES

RES

3F69

10K

2F53

MAIN NVM

+3V3

RES

9CH0

10K

3F54

3F53

1u0

B01E

DEBUG ONLY
IF58

2F58 RES

SCL-SSB

1
2
3

0
1
2

WC

ADR
SDA

100R

SDA-SSB
FF63

SCL

3F63

100R

SCL

1
2
3

SDA
5

7
6
5

FF55

3F59
100R

3F60

SCL-UP-MIPS

FF56

SDA-UP-MIPS

100R

IF59

(8K 8)
EEPROM

10K

3F58

RES
1F52

3F62

FF62

100n
7F58

FF61

FF57

LEVEL

DEBUG / RS232 INTERFACE

TXD-UP
RXD-UP
RESET-STBYn
SPI-PROG

FF65

3F64

FF66

100R

SHIFTED

RES
1F51
FF64

3F65
100R

1
2
3
4
5

UP

FOR
DEBUG
USE ONLY

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_005_110114.eps
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2011-Nov-04 back to

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 112

Tuner

Tuner

B01F

B01F

IF10
IF11

AGC CONTROL

3F79-4

AF73

15p

2F73

2F65 RES
1p0

2F72

220R

PNX-IF-N

3F77
IF79

3F81
220R

IF14

2F64

IF15

IF+

10n

* For BR NIM Tuner Only

3K3

470n

5F70

TUN-IF-P

5F73

3F78

10n
3

IF-

10n

2F90

IF86

TUN-IF-N

IF13

15p

220R

2F63

680n
2F66

10n

1K0
2F92

3F72

BA591

6F72

4K7

9F06

IF12

5F66

3F80
+5V-TUN-PIN
3F71

9F05

47n

2F85

100p

820R

VAGC

10n

IF16
330n
3F82 RES

10n

IF80

RES 5F76

2F79

*
2F70 RES

220R

10n
IF78

*
AF72

3F79-1

2F62

5F74

IF76

2F82

2F75

2p2
2F77

9F02

9F03

IF72

RES 2F95

FF82

OUTPUT2

IF74

2F80

INPUT2

RES
2F76

OUTPUT1

5F71

IF77

INPUT1

VCC

10n
2F78

GND2

IF81

IF73

FF01

IF-AGC

100n

2F93

5
4

GND

4K7
IF-AGC

FF75

FF81

IF82

PNX-IF-AGC

100p

2F61

* 9F04

TUN-IF-N
TUN-IF-P

RES 2F96

100n
2F60

2F91 RES

ATB2012
10n
IF89

15p

47R

2F86

3F75

15p

47R

IF87

SCL-TUNER

IF88

SDA-TUNER

IF90

SELECT-SAW

2F94

TUN-P6

TUN-P7

7F70
PDTC114EU

10n

3F76

RES

2F84

* For EU Hybrid Tuner Only

9F71
5F72 RES
+5V-TUN-PIN

+5V-TUN
22u

30R
2F88

4n7

AF71
AF70
FF00

O1
O2

2F74

GND1

IF75

X7251M
36M17

+5V-TUN-PIN

TUN-P6
TUN-P7

RES 2F59

RES 2F81

4n7

FF76

I
ISWI

RES 2F9D

RES 2F9C

RES 2F9B

RES 2F9A

RES 2F99

RES 2F98

RES 2F97

FF74

10n

12
6p8

6p8

6p8

6p8

6p8

6p8

6p8

1
2
3

TUN-P1

+5V-TUN-PIN
7F75
UPC3221GV-E1

1F75

PNX-IF-P

2F71

9F01

9F00

13
NC

IF_OUT2

IF_OUT1

11

4MHZ_REF

14

10

B+_TUN

I2C_SDA

I2C_ADR
5

TUN

RF_AGC

RF_IO

B+_LNA
2

16

I2C_SCL

TUNER

15

FF71

1T01

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_006_110114.eps
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2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 113

Toshiba Supply

Toshiba supply

B01G

+1V2-BRA-DR1

+3V3

5FA4

30R
10u

2FA4

OUT

30R

IN

100n

5FA3

7FA3
LD1117DT12

2FA3

+1V2-BRA-VDDC

FFAF

100n

COM

2FA2

B01G

FFA2

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_007_110114.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 114

HDMI

HDMI

B01H

HDMI CONNECTOR SIDE


1P05
DRX2+

DIN-5V

DRX2DRX1+
DRX1DRX0+
DRX0DRXC+
DRXCPCEC-HDMI
FFB1
FFB2
FFB3
FFB4
20
22

DRX-DDC-SCL
DRX-DDC-SDA

DRX-DDC-SCL
DRX-DDC-SDA

47K

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FFB5 21
23

1 3FBF-1 8

B01H

2 3FBF-2 7

DIN-5V

47K
DIN-5V
DRX-HOTPLUG

FFB6

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


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div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 115

VGA

VGA

B01I
3FC5
CDS4C12GTA
12V

RES 6FC1

1FC1

100p

RES 2FC1

FFC1

CDS4C12GTA
12V

RES 6FC2

1FC2

100p

G-VGA

18R

1FC3

RES 6FC3

FFC4

100p

RES 2FC3

FFC3

CDS4C12GTA
12V

3FC7

9FC5

H-SYNC-VGA

9FC6

V-SYNC-VGA

4K7

3FC3

CDS4C12GTA
12V

RES 6FC4

1FC4

FFC6
1216-02D-15L-2EC

B-VGA

18R

FFC5

47p

CDS4C12GTA
12V

RES 6FC6

47p

2FC6

10K

RES
3FC2

FFC9

RES 6FC7

47p

2FC7

10K

4K7

3FC4

CDS4C12GTA
12V

RES 6FC5

1FC5

FFC8

CDS4C12GTA
12V

RES
3FC1

47p

2FC5

FFC7

9FC1

VGA-SDA-EDID-HDMI

9FC2

VGA-SDA-EDID

RES

9FC3

VGA-SCL-EDID-HDMI

9FC4
RES

VGA-SCL-EDID

RES 6FC8

1FC6

47p

+5V-VGA
CDS4C12GTA
12V

17

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

2FC4

VGA
CONNECTOR

3FC6

RES 2FC2

1E05

R-VGA

18R

FFC2

2FC8

B01I

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 116

Temp sensor & headphone

Temp sensor & headphone

B01J

SCL

A2

1K0

3FD2

9FD2 RES

9FD1 RES

100n

IFD3

IFD5

RES

+VS

A1

9FD5

SDA

1K0

2FD1

1K0
IFD4

IFD1

A0

100R

100R

OS

1K0
3FD7

SCL-SSB

3FD4

3FD6

SDA-SSB

IFD2

7FD1
LM75BDP

GND

3FD3

LTST-C190KGKT

RES

RES
3FD1

+3V3

6FD1

RES
1329

1
2
3

502382-0370

1328
MSJ-035-12D-B-AG-PBT-BRF

FFDA

AMP1

2
3
1

22n

FFDB
22n
2FDD

CDS4C12GTA
12V
2FDC

RES

6FD3

CDS4C12GTA
12V
1FD3

6FD2

1FD2

RES

1K0

1K0
3FDG-1

3FDG-2

AMP2

B01J

FFDC

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


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2011-Nov-04 back to

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 117

Tuner Brazil

B01K

Tuner Brazil

B01K

5FE0

IF63

IF64
+1V2-BRA-VDDC

+2V5-BRA

+3V3-BRA-FLT

1u0

100n
2FF1

100n
2FF0

100n
2FE5

100n
2FE4

2FE3

1u0

2FE0

30R

AGND
5FE3

IF65

IF66

+3V3-BRA-FLT

5FE4
+3V3-BRA

1u0

100n
2FF6

100n
2FF5

100n
2FF4

100n
2FF3

1u0

2FF2

30R
2FE6

30R

AGND
5FE5

IF67

IF68
+1V2-BRA-DR1
IF48

5FE7

+3V3-BRA

+3V3

1u0

100n
2FF9

100n
2FF8

2FF7

1u0

2FE8

30R

30R

5FE8

IF69

+2V5-BRA
7FE3
LD3985M25

1u0

100n
2FG1

25M4
4

5FE9

+5V
30R

18p

2FG3

18p

2FG2

1FE0

2FG0

30R
1

IN

OUT

INH

BP

FF03

+2V5-BRA

10n
2FG6

2FG7
AGND

2FG9

100n
2FG8

10n

100n

IF17
IF18

30
29

BFE2

28
27

BFE3

100n
2FH6

100n

24
25

2FH7

100n

26

AGND

39

AGND

0
XSEL
1

PBVAL
RERR
RLOCK

P
ADI_AI
N

RSEORF

P
ADQ_AI
N

SBYTE
SLOCK

P
AD_VREF
N

SRCK

AD_VREF

SRDT

DTCLK

STSFLG1

21
58
53
54
55

1n5

33R

TS-BR-VALID

9F27-1

TS-FE-VALID

3FG6-3

33R

TS-BR-SOP

9F27-2

TS-FE-SOP

TS-FE-CLOCK

TS-FE-DATA

11
SCL-SSB
SDA-SSB

3FE8

100R
3FE9

IF49
100R

45
46

SYRSTN
AGCI
0
SLADRS
1

CKI
SCL
SDA

AGND

PLLVSS

STSFLG0

DFE8

DFE9
5FG0
3FG7

60

3FG6-2

TN

SCL
SDA

33R

TS-BR-CLOCK

33R TS-BR-DATA

9F28
4

9F27-4

30R
5FG2

DFF1
30R

3FE5
18K

10
51

1u0

DFE7

DFF2

IF28
IF-AGC

AGND

42
6
5
12
14

3FG2-1

RESET-SYSTEMn
10K

3FG2-2
10K

3FG4-2
4K7

3FG4-1
4K7

VSS

+3V3-BRA-FLT

4
15
33
37
44
47
50
57
62

10K IF29

0
TSMD
1

17

3FE7

AGCCNTR

AD_DVSS

1
41

10K

S_INFO

31

3FE6

AGCCNTI

AD_AVSS

DTMB

23

+3V3-BRA-FLT

10n

DFE6

61

38

3FG6-4

IF27
40

AGND

59
52

2FH4

* To be drawn near PNX85500

2FH3

2FH5

1u0

43
FIL

2FH2

VDDS

DR2VDD

34
48

13
35
49
64

20

16
36
56
63
VDDC

10n

2FG4

IF+
IF-

2FH8

3
2

DR1VDD

18

PLLVDD

19

32

AGND

AD_AVDD

AGND

AD_DVDD

AGND

22

COM
7FE0
TC90517FG

AGND

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 118

10-2 B02 313912364954


NANDflash - conditional access

PNX85500: NANDflash - conditional access

B02A

7S00-5
PNX85500

D22
ALE
NAND
C21
CLE

XIO-A00
XIO-A01
XIO-A02
XIO-A03
XIO-A04
XIO-A05
XIO-A06
XIO-A07
XIO-A08
XIO-A09
XIO-A10
XIO-A11
XIO-A12
XIO-A13
XIO-A14
XIO-A15

J25
J26
H21
H22
H23
H24
H25
H26
G21
G22
G23
G24
G25
G26
F22
F23

IS25

00
01
02
03
04
05
06
07
XIO_A
08
09
10
11
12
13
14
15

XIO-D00
XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07
XIO-D08
XIO-D09
XIO-D10
XIO-D11

XIO

B22
OE_
C22
WE_

XIO-OEn
XIO-WEn

CLK_BURST

INPACK
XIO-D14
XIO-D15

IS26

INPACK

3S15
10K

+3V3

B21

E21
CE1_
D21
CE2_
A20
NAND RDY2
F21
RDY1
A21
WP_

NAND-CE1n

NAND-RDY1n
NAND-WPn

9S08

10K
RES

NAND-ALE
NAND-CLE

D25
D26
C24
D23
C23
B23
A22
E22
F24
F25
F26
E23
E24
E25
E26
D24

00
01
02
03
04
05
06
07
XIO_D
08
09
10
11
12
13
14
15

3S1V

FLASH

10K

3S1W

+3V3

IS00

7S00-11
PNX85500
1

3S01-1
33R
3S01-3 6

CA-MDI0
CA-MDI1
CA-MDI2
CA-MDI3
CA-MDI4
CA-MDI5
CA-MDI6
CA-MDI7

8
3S01-2 2

3 33R
33R 5 3S02-4 4
33R
7 3S02-2 2
33R 3S02-1 1
3 33R
6
3S02-3
33R 5 3S01-4 4
33R

P21
7 P22
P23
P24
P25
8 P26
N21
N22

CA-ADDENn

J22

CA-DATADIR

K25

CA-DATAENn

K26
3S03

CA-MICLK

N23
10R
L25

CA-MOCLK

N24
3S31
CA-MIVAL
33R

N25

CA-MOSTRT

L22

CA-MOVAL

L23
J21
L24

CA-RDY

L26

CA-RST

J23

RES
9S01

CA-MISTRT

J24
+3V3

VIDEO_STREAM

0
1
2
3
MDI
4
5
6
7

0
1
2
3
MDO
4
5
6
7

10K

3S1X

+3V3

N26
M21
M22
M23
M24
M25
M26
L21

CA-MDO0
CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7

ADD_EN
DATA_DIR

VS

K23
1
K24
2

CD

K21
1
K22
2

DATA_EN
I
MCLK
O

9S00

CA-VS1n
CA-MOCLK
CA-CD1n
CA-CD2n

CA

+3V3

MISTRT
MIVAL

TS-FE-DATA

3S1R

MOSTRT

TS-FE-CLOCK

3S1S

MOVAL

TS-FE-VALID

3S1T

OOB_EN

TS-FE-SOP

560R
560R

3S1U RES
RES

560R
560R

RDY
RST
VCCEN
VPPEN

T21
DATA
T23
ERR
T22
TNR_SER1 MICLK
R23
MIVAL
R22
SOP

TS-FE-DATA

TS-FE-DATA

3S23

TS-FE-CLOCK
TS-FE-VALID
TS-FE-SOP

TS-FE-CLOCK

3S24

TS-FE-VALID

3S28

TS-FE-SOP

470R
3S29 RES

TS-FE-ERR

470R
470R

100n

7S02
5

33R

RES 470R

3S04
2S09

B02A

1
4
2
3

74LVC1G08GW

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_012_110209.eps
110209

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 119

SDRAM

PNX85500: SDRAM

B02B

F3
C2
F2
C3
B4
F1
C1
E1
F4
B2
E5
C5
A4
G5
B3
F5
U3
P2
U2
P3
N1
U1
P1
T1
V4
R5
U5
P5
N3
V3
R4
V5

3S07

180R 1%

180R 1%

3S22

DDR2-VREF-CTRL2

2S12

N
P

DQS0

N
P

DQS1

N
P

DQS2

N
P

DQS3

N
P

CASB
CKE
CSB
ODT
PCAL
RASB
WEB
VREF

1
2

N5
N4

3S30
10R

DDR2-CLK_N
DDR2-CLK_P

3S33
10R

E2
E3

DDR2-DQS0_N
DDR2-DQS0_P

D3
D4

DDR2-DQS1_N
DDR2-DQS1_P

R1
R2

DDR2-DQS2_N
DDR2-DQS2_P

T3
T4

DDR2-DQS3_N
DDR2-DQS3_P

K3
K4
L5
M4
M1
M5
H3

DDR2-CAS
DDR2-CKE
DDR2-CS
DDR2-ODT
DDR2-RAS
DDR2-WE

A2
V1

DDR2-CKE

3S6Q
10K

DDR2-ODT

3S6P
10K
RES

DDR2-VREF-CTRL2
DDR2-VREF-CTRL3

3S0V

FS01

DDR2-VREF-CTRL3

CLK

2S24

FS02

100u 2.0V

3S06

180R 1%

180R 1%

3S20

+1V8

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DQ
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

M0

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13
DDR2-A14

1%

DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D6
DDR2-D5
DDR2-D4
DDR2-D7
DDR2-D8
DDR2-D9
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D14
DDR2-D15
DDR2-D16
DDR2-D17
DDR2-D19
DDR2-D18
DDR2-D22
DDR2-D23
DDR2-D20
DDR2-D21
DDR2-D24
DDR2-D30
DDR2-D26
DDR2-D25
DDR2-D28
DDR2-D31
DDR2-D27
DDR2-D29

0
1
DM
2
3

J1
J3
K1
G4
L3
G3
L2
H5
L1
J5
J2
M3
J4
M2
K5

IS42
261R

D1
D5
R3
T5

0
1
2
3
4
5
6
7
A 8
9
10
11
12
13
14

100p

DDR2-DQM0
DDR2-DQM1
DDR2-DQM2
DDR2-DQM3

MEMORY

0
1 BA
2

100n
2S25

DDR2-BA2

H1
H2
G1

DDR2-BA0
DDR2-BA1

100n
2S17

7S00-8
PNX85500

100p
2S20

B02B

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_013_110209.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 120

Digital video in

PNX85500: Digital video in

B02C

7S00-6
PNX85500
T25
T26

HDMIA-RX1+
HDMIA-RX1-

U25
P
U26
RX1_A
N

P
RX0_A
N

DDC_A

Y26
SCL
Y25
SDA

HDMIA-RX0+
HDMIA-RX0-

V25
P
V26
RX2_A
N
HOT_PLUG_A

HDMIA-RXC+
HDMIA-RXC-

W25
P
W26
RXC_A
N

DDCA-SCL
DDCA-SDA
IS10

T24

IS01

3S0W

W24

RREF

12K
10u

+3V3

HDMI_DV

HDMIA-RX2+
HDMIA-RX2-

RES
2S2E

B02C

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_014_110209.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 121

Audio

B02D

PNX85500: Audio

B02D
3S0Z
+2V5-AUDIO

3S53-1

+24V-AUDIO-POWER
4R7

100R

220n

2S3J
2S2S

10u RES

1u0 RES

2S34

100n

100u 4V

1u0

2S41

4R7
2S42

3S51

3S36-1
2S2G

1u0

AB9
POS
AB8
VR_AADC
NEG

4
IS1S

DBS8

AE5

7S05-3
LM324 8

3S39

-AUDIO-R

100R
11

ADAC(3)

33R
ADAC(4)

3S36-3

10K

10K

3S3H

3S36-4
2S2H

ADAC(5)

33R
3S3U

47p

ADAC(6)

+24V-AUDIO-VDD

33R

SPDIF_OUT

2S3D

AF5

56R

10

33R

AE1
1
AF2
2
VREF_AADC
AE3
I2S_OUT_SD 3
AC8
AF3
VCOM_AADC
4

3S3F

3S3G-2
2
7
3S3G-4

AD8
IS1A

IS03

ADAC(2)

SPDIF_IN1

1n0

IS1B

AD7
AE7
AF7
AD6
AE6
AF6

AD4
OSCLK
AD1
SCK
AD2
WS

I2S_OUT

ADAC(2)

33R

1n0
2S38

2S2L

AF8
L
AE8
AIN5
R

1n0
2S39

3S10
100R

ADAC(1)
3S3G-3

1n0
2S3A

1u0

1n0
2S3B

33R

1n0
2S3C

1
2
3
ADAC
4
5
6

AD9
L
AC9
AIN4
R

2S32

IS07
3

ADAC(5)

7S05-1
LM324

AUDIO-OUT-L

2
11

3S37

3S6L

10K

22K
2S2K

+3V3

47p

+3V3-ARC

+24V-AUDIO-VDD
3S11

IS1L

1R0
5

ADAC(6)

IS06

7S05-2
LM324 7

AUDIO-OUT-R

6
14

1 3S18-1 8

IS1G

SPDIF-OUT

220R

3S18-2

100n
7

+3V3

2S3K

+3V3

220R

&

7S09-1
74LVC00APW
1

IS1D

SPDIF-OUT-PNX

3S32

10K

22K
2S2J

7S09-3
74LVC00APW
9

&
6

14

+3V3-ARC

&

2S3L

180R

100n

3S6M

IS1K

2S3M

IS44
eHDMI+

100n
68R

3S25

+3V3

10

14

+3V3-ARC
7S09-4
74LVC00APW
12

&
11

+3V3

13
7

SEL-HDMI-ARC

IS1E

3S34

47p

+3V3-ARC
7S09-2
74LVC00APW
4

14

SPDIF-OUT-PNX

11

3S18-3

IS19

10K

7
10K

100n

22K

3S17-2

1 3S3G-1 8
IS1N

1u0

IS1Q

3S13-2

AE9
L
AF9
AIN3
R

1u0
2

10u
2S3G

2S33

100n
2S3H

AUDIO-IN4-R

22K

8
10K

3S36-2

47p

AC6
P
AB6
ADACR
N

AD10
L
AC10
AIN2
R

3S17-1

10u
2S3E

2S3F

AUDIO-IN4-L

+AUDIO-L

+24V-AUDIO-VDD
2S36

AUDIO
AC7
AE10
L
P
AB7
AF10
AIN1
ADACL
R
N

2S30
1u0

3S13-1

3S38
100R

11

10K

220R

6
10K

22K
1

7S05-4
LM324 14

13

7S00-2
PNX85500

2S31
1u0

IS1P

4
IS02

2S2Y
1u0

5
10K

3
3S17-3

+2V5

12

ADAC(1)

IS1M

3S17-4

4S14

100n

22K

INH

IS13

1u0
IS0V

3S13-3

BP

FS03

2S2Z

2S3Q

AUDIO-IN3-R

IS0R

3S13-4

IN

COM
2S2T

100R

10K
3S16-4 5
4
10K

OUT

1u0
3S16-3 3

5
IS12

2S2V

22K

AUDIO-IN3-L

100R

7S08
LD3985M25
FS08

3S53-4

7
10K

1u0

10K

AUDIO-IN1-R

IS1J

2 3S12-2

2
3S16-2

100R
3S53-3

10u

22K

2S2W

2S2R

3S19

AUDIO-IN1-L

1 3S16-1 8
10K

IS1H

3S12-1

9S06
RES

+24V-AUDIO-VDD

+3V3

3S53-2

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_015_110209.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 122

MIPS

PNX85500: MIPS

B02E

B02E
+3V3

7S00-3
PNX85500

CONTROL

10K
3S62

IS04

GPIO6

PNX-SPI-CS-BLn

+3V3

GPIO6
PNX-SPI-CS-BLn
BOOST-PWM
SELECT-SAW

+3V3

FS64

SELECT-SAW

5K6

3S64

3S55

10K

TRSTN
TMS
TCK
TDO
TDI

RESET_SYS
BL_PWM

10K
CLK_54_OUT

3S83
+3V3

RXD1-MIPS
3D-VS

10K
3S84
+3V3
10K

3S60

B24
SDA
A23
4
SCL

R26
DN
R25
USB
IS4Z R24 DP
RREF

USB-DM
USB-DP

B25
SDA
A24
SCL

1
100R

1
100R

2 3S5W

SDA-SET
SCL-SET

SDA-SET
SCL-SET

3S6C

4K7

3S5Z

SDA-SSB
SCL-SSB

SDA-SSB
SCL-SSB

3S6E

2K2

3S61

SDA-TUNER
SCL-TUNER

2
1
100R

AA25
AA24
AA23
AB26
AB25

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TDI-PNX85500

3S00

AE4

SDA-UP-MIPS
SCL-UP-MIPS

4K7

3S6A

SDA-TUNER
SCL-TUNER

3S6G

4K7
3S6B

4K7

3S6D

2K2

3S6F

2K2

FS44

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDI-PNX85500

FS49
FS50
FS51
FS52

EJTAG-DETECTn

FS53
10 9

1
2
3
4
5
6
7
8

FOR FACTORY
USE ONLY

2K2
3S6K

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TDI-PNX85500

1
10K

8 3S6H-1
10K
3
6 3S6H-3
2
10K
10K

+3V3

FS57

+3V3-STANDBY

BM08B-SRSS-TBT

7 3S6H-2
5 3S6H-4
4
10K

RESET-SYSTEMn

33R

AD5

BACKLIGHT-PWM

AC5

IS14
+3V3

TXD1-MIPS

3S72
3S4A

BACKLIGHT-PWM

+3V3
IS40
PXCLK54

47R
100R
IS15

3D-VS-DISP

3S4B
100R
RES

RES

+3V3
2S89
100n

+3V3

RES 3S21
+3V3

10K
10K

FS10 TXD2-MIPS
FS11 RXD2-MIPS

1
100R

1 3S5Y 2
100R

SDA-UP-MIPS
SCL-UP-MIPS

7S01
PCA9540B

SC0

VDD

SC1
SCL-SET

SCL

SDA-SET

SDA

INP
FIL

I2 C
-BUS
CTRL

3S65

SCL-DISP

1
4K7
1
4K7
3S67
1
4K7
3S68
1
2
4K7

SCL-DISP

3S66

SCL-BL

SD0

SDA-DISP

SD1

SDA-BL

SCL-BL
SDA-DISP
SDA-BL

2
2

VSS
6

+3V3
+3V3

3S80
3S81

10K

9S09

RES
1F10

3S69

2 3S57

10K

BOOST-PWM

+3V3

IS17

1
100R

3S58
1
2
100R

B26
SDA
A25
2
SCL

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_10
GPIO_11

3S27

3D-LR

DS52

10K
3S82

Y21
IS16 Y22
Y23
Y24
W21
W22
W23
V22
V23
U23

3S56

10K

+3V3

BOOTMODE
3D-LR
RXD1-MIPS
TXD1-MIPS
RXD2-MIPS
TXD2-MIPS

1
100R

3S6J

10K
3S40

C25
SDA
C26
SCL

3S26

BOOTMODE

RES 10K

IS05

3S45
+3V3

FS31

9S10
IS08
SCL-SET

SDA-SET

IS09

SCL-BL

9S11

FS2W

SCL-DISP

9S12

FS2Y

SDA-DISP

9S13

SDA-BL

7S00-4
PNX85500

ETHERNET

ETH-RXCLK

AA3

ETH-RXD(0)
ETH-RXD(1)
ETH-RXD(2)
ETH-RXD(3)

Y5
0
Y6
1
RXD ETH
AB4
2
AC1
3

IS50

RXCLK

ETH-RXDV
ETH-RXER

AC2
RXDV
Y4
RXER

SDIO-DAT3
SDIO-CLK
SDIO-CMD
SDIO-DAT0
SDIO-DAT1
SDIO-DAT2
SDIO-CDn
SDIO-WP

W2
W1
W6
W5
W4
W3
U6
V6

TXCLK
0
1
2
3
TXEN
TXER
COL
CRS
MDC
MDIO

TXD
ETH

CC_DAT3
CLK
CMD
0
SDIO
1 DAT
2
SDCD
SDWP

AA2

ETH-TXCLK

AA1
AA4
AB1
AB2
AA5
AB3
AC3
Y2
Y3
Y1

ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)
ETH-TXD(3)
ETH-TXEN
ETH-TXER
ETH-COL
ETH-CRS
ETH-MDC
ETH-MDIO

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_016_110209.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 123

Video out - LVDS

B02F

PNX85500: Video out - LVDS

B02F

7S00-7
PNX85500
PX1APX1A+

A7
B7

PX1BPX1B+

C8
B8

PX1CLKPX1CLK+

9S90
9S91

LVDS

N
A
P
N
B
P

C10
N
CLK
B10
P

N
P

N
P

CLK
LOUT1 LOUT3

D7
E7

PX3APX3A+

E8
D8

PX3BPX3B+

E10
N
D10
P

9S94
9S95

PX3CLKPX3CLK+

N
P

D9
E9

PX3CPX3C+

A11
N
D
B11
P

D11
N
E11
P

PX3DPX3D+

PX1EPX1E+

C12
N
E
B12
P

E12
N
D12
P

PX3EPX3E+

PX2APX2A+

A14
N
A
B14
P

D14
N
E14
P

PX4APX4A+

PX2BPX2B+

C15
N
B
B15
P

E15
N
D15
P

PX4BPX4B+

CLK

E17
N
D17
P

D16
N
E16
P

PX4CPX4C+

D18
N
E18
P

PX4DPX4D+

E19
N
D19
P

PX4EPX4E+

PX1CPX1C+

A9
B9

PX1DPX1D+

PX2CLKPX2CLK+
PX2CPX2C+
PX2DPX2D+
PX2EPX2E+

9S92
9S93

N
C
P

C17
N
CLK
B17
P
A16
B16 N
C
P
A18
B18 N
D
P
C19
B19 N
E
P

LOUT2 LOUT4

9S96
9S97

PX4CLKPX4CLK+

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_017_110209.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 124

Standby controller

PNX85500: Standby controller

B02G
POL

+1V1

B02G

2S13

100n

1u0
2S10

30R

RES
5S04

IS3B

10K

+3V3-STANDBY
3S1H
10K

3S1G

RXD-UP
TXD-UP

10K
3S2A

RXD-UP
TXD-UP
DETECT2

AE21
0
AF21
1
AA22
2
P3
AB22
3
AC22
4
AD22
5

RESET-SYSTEMn
AV2-BLK
AV1-BLK
KEYBOARD
LIGHT-SENSOR
AV1-STATUS
AV2-STATUS

AD23
0
AE26
1
P5
AE25
2
AE24
3

DETECT2

10K
RES
3S1K
10K
RES

RESET-SYSTEMn
3S1J
100K
RES

KEYBOARD
2S4E
100n

3S1L
10K

SPI-PROG

SPI-PROG
PNX-SPI-WPn

AF22
4
P6
AE22
5

VDD_XTAL

AF26

AC17

EA
ALE
PSEN
MC

RESET-STBYn

AB24

EA

AB23

AC23
SDA
AC24
SCL

AD26
0
PWM AC25
1

PSEN
3S2F
100R

100R

3S2G

SDA-UP-MIPS
SCL-UP-MIPS

100R

3S2K

3S2H
100R

LED1
LED2

AE23
SDO
AF25
SDI
SPI
AF24
CLK
AF23
CSB
AB17
0
AA18
1
AD18
2
AE18
3
P0
AF18
4
AA19
5
AB19
6
AC19
7

ALE

ALE

AC26

IS3F

3S44

IS3E

10K

3S43

IS3D

10K 3S42

10K

EA

PSEN
RES

SDA-UP-MIPS
SCL-UP-MIPS

3S6V
4K7
RES

LED1

3S6W
3S1P
10K

LED2

IS2V

CTRL-DISP
RESET-DVBS
RESET-USBn
RESET-ETHERNETn
SEL-HDMI-ARC
RESET-AVPIP
RESET-AUDIO
AUDIO-MUTE-UP

RES

3S41
10K

PNX-SPI-SDO
PNX-SPI-SDI
PNX-SPI-CLK
PNX-SPI-CSBn

IS2Z

4K7

RES
10K
RES 3S3Y
10K

CTRL-DISP
RESET-DVBS
RESET-USBn
RESET-ETHERNETn
SEL-HDMI-ARC
RESET-AVPIP
RESET-AUDIO
AUDIO-MUTE-UP

10K

3S2L
RES
10K
RES
10K

3S2S
RES
3S3W
4K7

3S46
3S47

+3V3-STANDBY

3S2M
RES
3S49

10K
4K7

+3V3-STANDBY

+3V3-STANDBY

7S20
NCP303LSN28
2

FS45
1

IS2U
5

INP
OUTP
CD

1K0

10K
3S3T

STANDBY

AA26

1 3S2V 2

RES 3S3S

RESET_IN

+3V3-STANDBY

10p

AF17

FS0Z

RESET-STBYn

NC GND
3

10K

AC20
0
AD20
1
AE20
2
AF20
3
P2
AA21
4
AB21
5
AC21
6
AD21
7

XTAL_OUT

AE17

3S3P

LCD-PWR-ONn
EJTAG-DETECTn
LAMP-ON
STANDBY
FAN-CTRL1
FAN-CTRL2
POWER-OK
ENABLE-3V3n

XTAL_IN

10p
2S4F

100n

10K

LCD-PWR-ONn
EJTAG-DETECTn
LAMP-ON
STANDBY
FAN-CTRL1
FAN-CTRL2
POWER-OK
ENABLE-3V3n

2
4
1

2S4K

3S3M

RES
10K
3S3N RES
10K
3S3Q RES
10K
3S3R
10K RES

7S00-9
PNX85500

9S0E

3S3L

10K

AD19
0
AE19
1
AF19
2 P1
AA20
3
AB20
7

2S4G

RES

+3V3-STANDBY

RC
TACHO
CEC-HDMI
BACKLIGHT-PWM-ANA-DISP
SDM

DS50

9S0D

3S1E
10K

RC
TACHO
CEC-HDMI
BACKLIGHT-PWM-ANA-DISP
SDM

AD17

10K
3S1D
27K

RES
10K
RES
3S1F

VDDA_ADC2V5

2S4D
1n0

3S1B
3S1C

VSS_XTAL

+3V3-STANDBY

VDDA_1V1_DCS

AA17

IS20

54M

100n

1S02

9S24

1u0
2S11

RES

2S37

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_018_110209.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 125

Power

PNX85500: Power

B02H

5S80

IS3Q

2S5A

RES 10u

100n

2S6A

+1V1

B02H

30R

5S81

2S5B

RES 10u

100n

2S6B

+2V5
30R

5S82

IS3S

100n

100n
2S68

+3V3
2S5D

2S4M

100n

U22

VDD_3V3_SBY

10u

VSSA_USB

VDDA_2V5_VADC
VDDA_2V5_VDAC
VDDA_3V3_USB

10u

100n
100n

2S4Y

10u

2S50

100n

2S4Z

6.3V
10u

100n

+1V2
30R
c000

SENSE+1V2

Y17
D13
POL

T20
Y13

+2V5-AUDIO

Y10

100n

VDDA_2V5_USB

30R

R21

R20

100n

2S45

+2V5-AUDIO

5S87
+2V5
1u0

2S56

100n

2S55

30R

5S88
30R

10u

100n
2S57

2S5M

+2V5-LVDS

5S89
100n
2S58

10u

100n
2S6K

2S6H

+2V5
30R

5S90
+2V5
10u

100n
100n

2S53

2S4T

30R

2SHW

5S92
+3V3
1u0

100n
2S59

2
1

100n
2S6L

2S6M

IS58

VDD_1V1_DDR

VSSA_2V5_LVDS_BG

VDDA_2V5_LVDS_BG

AA7

+2V5

30R

5S84

AA9

2S46

VDDA_2V5_DCS

5S95

Y12

RES 1u0
2S4W

+1V1
IS3L

2S52

VDDA_2V5_ADAC

5S83

B13

2S51

VDDA_2V5_AADC

2S6P

100n

100n
2S6C
10u
2S4U

2S4V

Y19
Y18

AA15
Y15
VDDA_1V2
AA13
VDDA_2V5

30R

+3V3-STANDBY

IS3K
VDDA_1V1_LVDS_PLL

+3V3

2
100n
2S6N
1

2
2S6F
1

100n
1 2S6G 2

5S85

W20
P20
M20
K20
V7
Y8

VDD_1V1

100n

2S4N

C7
C9
C11
C14
C16
C18

2S4P

+2V5-LVDS

N6
N7

VDD_2V5_LVDS

VDD_3V3

220u 6.3V

100n
2S6E 2

2S6D

U20
U21

+2V5

30R

1
HDMI_VDDA_2V5

VDD_2V5

C13

1u0

2S21

100n

2
1

2S5P

HDMI_VDDA_1V1

V20
V21

HDMI_VDDA_3V3_TERM

VSSA_1V1_LVDS_PLL

2S29

220u 2.5V

J7

30R

VDD

A13

100u

2S23

5
100n

5
100n

5S94
+1V1

10u
RES

VSS

2S4S

VSS

VSS

M7
N2
N20
P10
P12
P14
P16
P18
P4
P6
P7
T10
T12
T14
T16
T18
T2
T6
T7
U4
V10
V12
V14
V16
V18
V2
Y20

VDD_1V8

U24
V24 HDMI_AGND

3
7
2

100n
2S5J-4

100n
2S5J-2

6
100n
2S5H-3

2
8

100n
2S5J-1

4
100n
2S5J-3

100n
2S5K-4

6
100n
2S5K-3

7
2

100n
2S5K-2

2S5K-1
1
AA16
AA8
Y11
Y14
Y16
Y9

VSS

G14
G16
G18
G2
G20
G8
H4
H6
H7
J20
K10
K12
K14
K16
K18
K2
K6
K7
L20
L4
M10
M12
M14
M16
M18
M6

A1
A10
A12
A15
A17
A19
A26
A3
A8
B1
B20
C20
C4
D2
D20
E13
E20
E4
F10
F12
F14
F16
F18
F20
F8
G10
G12

100n
2S5H-4

8
100n
2S5H-2

100n
2S5H-1

100n
2S5G-4

100n
2S5G-3
3

100n
2S5G-2
2

2S5G-1
1

22u

22u
2S4R

100n

2S4Q

100n

2S27

2S28

100n

2S43

+1V1

AF1
AE2
AD3
AC4
AB5
H20
F11
G11
F13
G13
F15
G15
F17
G17
F19
G19
J9
J11
J13
J15
J17
L9
L11
L13
L15
L17
N9
N11
N13
N15
N17
R9
R11
R13
R15
R17
U9
U11
U13
U15
U17
J6
AA6
Y7
W7
F9
G9

30R

5S93
L6
L7
R6
R7
U7
A5
A6
B5
B6
C6
D6
E6
F6
G6
F7
G7

7S00-10
PNX85500

VSSA

RES 10u

c001

SENSE+1V1

7S00-12
PNX85500

100n

2S5C

100n
2S67

100n
2S66

100n
2S65

100n
2S64

100n
2S63

100n

2S62

100n
2S61

100u
2S60

2S26

+1V8

30R
4

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_019_110209.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 126

Analog video

PNX85500: Analog video

B02I

2S87

AV1-CVBS

Y-SVHS

47R

3S5B

22n

56R

Connectivity

2S8A

3S59

47R

22n

3S05

B02I

2S7J

AV1-R

C-SVHS

2S22

3S4J

56R

22n

22n

EU: SCART1

CVBS-MON-OUT1
22n

560R

3S5E

2S7K

AV1-B

56R

3S4L

AP:

3S08

560R

47p

2S7H

2S40

IS4V

22n

8K2

IS4W
3S09

56R

3S4K

AV1-G

2S7M

YPBPR1-SYNCIN1

10n
2S7L
56R

3S4P

AV3-Y

22n

2S7N

AP:

56R

YPBPR1
YPBPR1

3S4R

AV3-PR

EU:

22n
7S00-1
PNX85500

ANALOG_VIDEO

2S7P

2S8G

AV2-CVBS

9S18

22n

AB14
AF14
AE14
AC14
AD14

2S7R

AV4-Y

SCART2
YPBPR2

22n
9S19

EU:
AP:

AF15
AE15
AC15
AD15

AF16
AD16
AE16
AB18
AC18
AF4
AD24
AD25

AF11
AE11
AB10
AA11
AC16
AB16
AB13
AB12
AA12
AA10
AD12
AB11
AE12
AF12

IS5E

3S5S
10K

IS5D
IS5F
IS5G
IS5H
IS5J

3S75
BS15

PNX-IF-AGC

10K

BS10

IS11

3S76

PNX-RF-AGC

47K

9S20

10n

2S76

AA14

2S7U

2S14

BS13

AGND

22n

2S15
22n

AD11
AC11

+CVBS
AV4-PR

2S16
22n

22n

22n

IS5C

2S18
22n

AC12
AF13

2S19

CVBS_Y1 ATV_CVBS_Y3
C3
R
B AV1
CVBS_Y7
G
C7
SYNCIN1
CVBS1_OUT
Y_G1
CVBS2_OUT
PR_R_C1
PB_B1
RESREF
CURREF
CVBS_Y2
SYNCIN2
1
Y_G2
2
PR_R_C2
PB_B2
3
REF
4
R
5
6
G VGA
B
HSYNC_IN
IF_AGC
IN
RF_AGC
VSYNC
OUT
SCL VGA_EDID
P
TUNER N
SDA

10n

AB15
AC13
AD13
AE13

22n

2S75

56R

3S4T

AV3-PB

2S77

PNX-IF-P

10n

2S7E

AV4-PB
9S21

22n

2S78

319803104790 - RST SM0402 47R PMS Col R at 9S18 for Brazil

PNX-IF-N

10n

2S84
56R

3S50

R-VGA
22n

2S85
56R

3S52

G-VGA
22n

2S86

100R

3S5V-2

5
100R

100R

3S5V-4
4

7
100R

100R

3S5T-2

3S5T-1

H-SYNC-VGA

AP: VGA

22n

3S5T-4

56R

EU: VGA

3S54

B-VGA

3 3S5T-3 6

V-SYNC-VGA

100R

VGA-SCL-EDID

VGA-SDA-EDID

RES

RES

3S5V-3
100R
3S5V-1

100R

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_020_110209.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 127

10-3 B03 313912364954


Audio

B03A
7D03-1
BC847BS(COL)
6

3D09

+24V-AUDIO-POWER

+24V-AUDIO-POWER
FD14

Audio

+AVCC

B03A

220R

GND-AUDIO

1u0

3
6

3D02-3

7D15-2
BC847BS(COL)
4

4K7

ID19
ID18

2D16
2D17

ID29

ID30

1u0
AUDIO-MUTE-UP

ID37

2D22
220n

3D14-1
220n
1

2D26
RES

7
3D14-2
22K
2

6
3

3D14-3
22K

5
3D14-4
22K

22K

2D08

7D10-1
TPA3123D2PWP

1
3

R
PVCC
BSR

CLASS-D
AUDIO AMP

IN

11
7
4
2

1u0

18
17
GND-AUDIO

AVCC

47n

GND-AUDIO

10
12

2D23

ID15

19
20

2D29

4K7

FD03

3D02-1
8
1

+AUDIO-L

220n

7D15-1
BC847BS(COL)
1

4K7

2D19

7 3D02-2 2

ID28

2D07

FD08

47n

ID27

220u 35V

A-PLOP

4K7

1u0

220u 35V

2D24

ID14

2D20

2D28

3D02-4

FD01

-AUDIO-R

GND-AUDIO

220n

2D05

10u 35V

22K

220R
5D08

5D07

ID12

220n

3D16
ID11

2D06

4R7

R
OUT
L

0
GAIN
1

BSL

16

ID32

2D10
ID06

22u

22
21

5D05

5D02

ID10
220n

15

5D01

ID09
ID31

2D09

22u

ID05

2D12

220R

ID08

35V 220u

5D04

ID07

2D11

220R

RIGHT-SPEAKER

LEFT-SPEAKER

35V 220u

220n
VCLAMP
BYPASS
MUTE
SD
PGND

2D21
220n

3D10-1
220n
1

2D27
RES

7
3D10-2
22K
2

6
3D10-3
22K

4n7

4DETECT2

GND-AUDIO

GND-AUDIO

LEFT-SPEAKER

VIA
VIA

VIA

VIA

37
36
35
34

GND-AUDIO

10n

26
27
28
29

GND-AUDIO

V_NOM
2D14

7D10-2
TPA3123D2PWP

GND-AUDIO

GND-AUDIO

40
39
38

2D03

47K
100p

GND-AUDIO

3D01-4

GND-AUDIO

+3V3-STANDBY
ID35

GND-AUDIO

RES 2D31

ID34

7D11-2
BC847BS(COL)
4

EMC 4n7

1D50

22K

4K7

EMC

RES 2D30

CD10

3D10-4
22K

8
9

MAINS SWITCH DETECT

GND_HS

7D11-1
BC847BS(COL)
1

3D15

+3V3-STANDBY

3D01-3

47K

25

L
23
24

AGND

13
14

FD09

A-STBY

VIA
1D38

30
31
32
33

1735

LEFT-SPEAKER
3

100K

100K

100K

10n

4
RIGHT-SPEAKER
ID33
1D52

GND-AUDIO
3D06-4

2041145-3

2041145-4

100K

1
2
3

8 3D06-1 1

RIGHT-SPEAKER

10n
2D13

3D06-2

FD02

1
2
3
4

2D02

V_NOM

3D06-3 FD07

GND-AUDIO

2D01

220R
GND-AUDIO
3 7D03-2
BC847BS(COL)

FD05
FD06

5D03

5
10u

SPB SSB TV550


2K11 4DDR EU

GND-AUDIO

2010-12-10

3139 123 6495


19100_021_110209.eps
110209

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 128

DC/DC

DC/DC

B03B

B03B
5U03 RES
30R
5U02

FU05

IU22
+12V
1u0

2U20

10u

10u

7 8

IU10

12V/1V8 CONVERSION

3R3

3U11

2U19

2U25

7U02-1
SI4952DY

10u

10u

2U23

2U24

30R

FU02

2U21

5U00

FU03
22u

47u

2U16

2U15

8
47R
1

47R
3U23-1

3U23-2

3u6

5 6
IU23

1n0

2U17

IU09

47R

7U02-2
SI4952DY

3U23-4

47R
3U23-3

220p

+1V8
IU11

IU15

IU08

5 6 7 8

IU12

3U14
IU07

GND-SIG

20

3U28
GND-SIG

18
19

FU04

1u0

2U05

10u

10K

100n

2U14

RES 100u 2.0V

22u

2U13

IU17

IU25

GND

+1V1

IU18
1u0

2U10

GND-SIG

1n0

2U09

GND-SIG

3U21

FU00

SENSE+1V1

IU19

GND-SIG

2U07

RES 100p

22K

3U10

GND-SIG

FU08

100n

1% 330R
1% 1K0

CU00

5K6

FU09

IU04

3U19

3U22
1K0 1%
3U09

330R 1%

1K0 1%

3U08
+1V8

100p RES

IU20

RES
2U29

3U17
3U18

100R 1%

2U08

10K

V5FILT
VREG5

VIN

7
17

47u

1
2

2U12

TEST

10R
RES

1
TRIP
2

22
15

3U20

1
2

+1V1

47R

PGND

FU01

2u0
47R
3U24-1

1
VFB
2

5U01

FU06

24
13

3U24-2

1
2

47R

SW

12V/1V1 CONVERSION

1
12

3U24-4

1
VO
2

1 2 3

47R
3U24-3

21
16

1
2

4
IU14

1n0

IU02

DRVH

2U06

3U00

3U01

3U03
12K

1
EN
2

5 6 78

IU16

23
14

2U11

22K
GND-SIG

1
2

2U04

1
2

+3V3-STANDBY

5
8
IU01

DRVL

7U04
SI4778DY

6U00

1n0 RES

2U03
IU03

4
9

+1V1
+1V8

1
VBST
2

220p

STPS2L30A

3
10

ENABLE-1V8

3R3

2U01

100n

2
11

IU24

GND-SIG
3U02

3U05

7U03
TPS53126PW

IU13

10R

2U02
100n

7U00
BC847BW

3R3

2U22
IU06

IU05

RES

1 2 3

3R3

10u

2U00

10R

3U04

1n0

3U27

2U18

7U01
SI4778DY

IU21

CU01
CU02
CU03
CU04
CU05

GND-SIG

GND-SIG

GND-SIG

GND-SIG
GND-SIG

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_022_110210.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 129

DC/DC

B03C

DC/DC

B03C

+3V3-STANDBY

+3V3

RES 10K

+5V +3V3-STANDBY

3U75

3U74

RES 10K

LED-2

IU43

3U69

RES 10K

optionally 1M99 is a 9 pin connector

10K

3U68

9U41

IU44

3U41

IU45
9U42
RES

LED-1

LED2

3U59

LED2

10K RES

10K RES

7U42 RES
BC847BW

IU47
7U43
BC847BW

+3V3

3U70

LED1

3U53

LED1

10K

10K

1M99

3U56

3U44

FU07

3D-LR

100p

2U71

BL-SPI-CSn
BL-SPI-CLK

+3V3-STANDBY

3U71

STANDBY

7U48-2
BC857BS(COL)

5
10K 6

100R

2U68

3U62-4

3U83-2

100K

IU40

100R

FU53

3U42

BACKLIGHT-PWM_BL-VS

3U43

BACKLIGHT-BOOST

FU55

POWER-OK
100p

1n0

10n

2U44

2U45

2U46

100K

3U65

1n0

RES 10K

3U61

10K

2
22K

5
IU50

3U60-4

7U41-2
BC847BS(COL)
8

22K

4K7

IU62

6
1
7U41-1
BC847BS(COL)
1

Items

1K0
2U53

DETECT2

3U60-1

IU57
1

ENABLE-3V3n

22K

IU52

8
2

Optional table for 4U00 and 4U01

IU55

3U64

FU72

10K

LAMP-ON

100R

4U01
RES
4U00
RES

3U73
+3V3-STANDBY

ENABLE-1V8

RES 10K

100R

10K
3U62-1

3K3

3U45

FU51

3U60-2

IU63

10K

FU76

3U62-2

FU73

22K

IU56

IU49
6
7U40-1
BC847BPN(COL)

3U80

2U55

3U81

3 3U60-3 6

3U63

+3V3

GND-AUDIO

1K0

3U72

100p
RES

2U49
+24V

GND_AL

3U83-3
100K

IU61

10n

+24V-AUDIO-POWER

FU67

2U50

FU66

3U62-3

3
IU51
T 3.0A 32V

BZX384-C6V2

+12V

+12VIN

FU52

+12VIN

1U40

6U40

10n
2U54

**

IU48

1u0 RES

+3V3-STANDBY

1n0
RES

1-2041145-4

FU58
FU59
FU60
FU61
FU63
FU75

FU62

3
4

10n

2U58

1
2
3
4
5
6
7
8
9
10
11
12
13
14

7U40-2
BC847BPN(COL)

1u0
2U47
1M95

ENABLE-3V3-5V

BL-SPI-SDO

RES 100p

100R

RES
3U67
100R
RES
3U84
100R
RES
3U76
MAINS-OK
RES 100R

2U43

RES 100p
2U52

2U51

RES 100p

100p RES
2U72

1n0
2U48

1n0

RES 2U56

1-2041145-3
RES 2U57

3U66

FU56
FU57
FU74
FU68

7U48-1
BC857BS(COL)

100K
IU41

100R
+12VIN

3U83-4

FU54

100K

10K

+3V3

FU50

GND_AL

1K0 RES

+12V_AL

3U83-1

FU49

100n

GND_AL

IU64

3U82

FU48

GND_AL

1
2
3
4
5
6
7
8
9
10
11
12
13

If 1M99
is not mounted

If 1M99
is mounted

For non-Amblight sets

4U00

yes

no

no

4U01

yes

no

no

Dream Catcher
Core Range

2U44

3U43

1M95

0R

open

13 POLE

100p

100R

14 POLE

+12VD
4

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_023_110210.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 130

DC/DC

B03D

DC/DC
+3V3

B03D

7UC0
LF25ABDT

+12V

IN

OUT

1u0

2UA4

2K2

3UA0

COM

FUA0
+2V5-REF

7UA0
TS2431

FUA4
+2V5

CUA0

IUB6

+2V5-LVDS

+5V-TUN

3UB0

IUA5

22R
4

FUA3

3U15-2
100R
3U15-3
100R
3U15-4

+1V2

+5V

3U16-1

+3V3

100R
2

3U16-2
100R
3U16-3
100R
3U16-4

100R

100R

1u0

2UB1

470R

2
470R
3UB7-3
3
3UB7-4470R
5
4

IUB4

1u0

7UA3
PHD38N02LT

2UB0

7UA7-1
BC847BS(COL)
3U13

+3V3

100R

3UB7-2

22u

2UB8

7UA7-2
4
BC847BS(COL)

3U15-1

IU26

470R

+5V

2UB2

+1V8

RES 1u0

3UB6-1
1
8
1K0
3UB7-1
8
1

+2V5-REF

7
1K0 IUB2
3UB6-3
3
6
6
1K0
3UB6-4
5
4
1K0
IUB5
3 1

7UA6
BC817-25W
3U12
IUB3

330R
1%

+12V

3UB6-2

330R
1%

+5V5-TUN

NOT FOR 5000 SERIES

ENABLE-1V8
5

3UB1

+12V

RES
7UA4
TS431AILT

RES

NC

REF

470R

NC

470R
3U26-2

3U26-3
470R
3U26-4

IUB1

1
3UB3

RES

470R
+3V3

BP

+5V-TUN

COM

1 3U26-1 8 RES

INH

1u0

470R
3U29-4

OUT

100n
2UB6

3UB2

IN

2UB5

3 3U29-3 6 RES

+5V5-TUN

470R

IU30

7UA5
LDS3985M50

RES

1u0

+3V3

470R
3U29-2

2UB7

6
RES
7U06-1
BC847BS(COL)
1

3U29-1

4K7

1
3U25-1

3
RES
7U06-2
BC847BS(COL)
4

30R
1

IU29

RESERVED
5UA0

1K0

4K7

3U25-2

100K RES

IUA6

SENSE+1V2

3U25-3

100K RES

100K RES

3U25-4

100K RES

3UB5

3UB4

100K

1K0

IUB0

2UB3

+5V
6

RES

22n
2UB4
330p
RES

RES

470R

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_024_110210.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 131

DC/DC

DC/DC

B03E

5UD0

IUD0

+12V

FUD3

4n7
3UD2

33K
1%

22u

100n
IU27

3U06

120K

RES

12

68K
3UD1

1%
3UD0

15

13

VIA

10

7U05-1
BC847BS(COL)
RES 1

10K

2UD7

IUD6
7UD0-2
ST1S10PH

RES 2U27

+1V1

220u 16V

SS36

RES 2UE9

+5V
3u6

VFB
GND
P HS

6UD0

IUD7

2UD6

SYNC

5UD1

22u

VIN

IUD3

SW

2UD4

INH

RES 1n0

2UD3

ENABLE-3V3-5V

22u
2UD5

SW

1
A

10u

2UD2

10u

2UD1

10u

2UD0

7UD0-1
ST1S10PH

+5V5-TUN

30R

B03E

14

11

5UD3

+3V3

7U05-2
RES
4

3U07

100n
IU28

RES

33K
1%

12

1M0
3UD5

3UD4

VIA

10

15

13

IUD2
7UD1-2
ST1S10PH

BC847BS(COL)

10K

RES 2U28

2UE4

22u

22u
2UE3

+1V1

220u 16V

FUD2

3u6

VFB
GND
P HS
8

5UD2

2UE2

SYNC

IUD4

SW

VIN

1% 100K

INH

2UE1

ENABLE-3V3-5V

4n7
3UD3

SW

7UD1-1
ST1S10PH

10u

14

11

7UD2
LD1117DT25
3

IN

S1D

OUT

+2V5
2UE6

100n

2UE5

COM

22u 16V

IUD5

+5V

() FOR 5000 SERIES ONLY


() NOT FOR 5000 SERIES

7UD3
LD1117DT33
IN

OUT

+3V3
2UE8

100n

COM

22u 16V

6UD1

2UE7

10u

2UD9

10u

2UD8

30R

IUD1

2UE0

+12V

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_025_110210.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 132

Temperature sensor & AmbiLight

B03F

Temperature sensor & AmbiLight

B03F

5UM1

IUM0

1UM0

+3V3
30R

FUM0

V-AMBI

T 1.0A 63V

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_026_110210.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 133

Fan control

Fan control

B03G
+12V

+12V

1K0

FAN-CTRL1

IUS3 3US5-3
3
6

IUT1

100n

7US1-1
LM339P
14

2US3

10K 7

10K
9

3US5-2

3US7

+12V

10K

3US2

1 3US4-1 8

+3V3

IUS6

10K

7US2
BC807-25W

12
+12V

IUS7

IUT2

7US1-2
LM339P
13

IUS4 3US5-4
5
4

10

FAN-CTRL2

10K

22R

BC807-25W
7US3

IUS8

12

3US6

IUS9
47R

11

+12V
3US3

10K

3US5-1

3US9

+3V3

10K

FAN-DRV
+3V3

10K

7US1-3
LM339P
2

10K

3US4-3
3

+12V

IUS5

3US4-4

+12V

4
12

TACH01

RES

+12V

10K

+12V
3US4-2

9US0
TACH02

7US1-4
LM339P
1

IUS0

12

B03G

TACHO

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_027_110210.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 134

Vdisp switch

Vdisp switch

B03H

1 9UU0-1
RES
2 9UU0-2
RES
3 9UU0-3
RES
4 9UU0-4
RES
1 9UU1-1
RES
2 9UU1-2
RES
3 9UU1-3
RES
4 9UU1-4
RES

7UU0
SI4835DDY

8
7
6
FUU0

47R
IUU1
3UU0-2
7
2

2
IUU2

1u0

3UU3-2

IUU3
7

47K RES
7UU3 RES
BC847BW

+3V3-STANDBY
47K

47K
3UU0-1

2
3

7UU2-1
PUMD12
1

47K

6
3UU0-3

22n

2UU2
1

47K RES
2UU1

3UU1

+VDISP-INT

IUU0

IUU4 3UU3-3 IUU5 3UU3-4


6
3
4
5
47K RES

VDISP-SWITCH

2UU0

3UU3-1

FUU1
3UU2

+3V3

47K RES
RES 100n

RES
7UU1
SI3441BDV

+12VD

4
PUMD12
7UU2-2

B03H

+3V3

4K7 RES

LCD-PWR-ONn

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_028_110210.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 135

10-4 B04 313912364954


Analogue externals A

Analogue externals A

B04A
FE70

3E37-4

AP-SCART-OUT-R

IE67

2EA4

AUDIO-OUT-L

470R 1
FEA0

7E01-1 6

1n0

2E87

1E00

CDS4C12GTA
12V

RES 6E01

100p

2E01

IEC0

3EA7-1

5 100R 4

8 16V
1u0
AP-SCART-OUT-L

IEC1
2
1
PUMH7

IE22

IEC2

3EA7-4

IE68

2EA5

AUDIO-OUT-R

470R 4
FEA1

7E01-2 3

1n0

2E88

1E31

CDS4C12GTA
12V

5
RES 6E03

1K0

100p

2E06

RES

FE71

3E07-4

AUDIO-IN1-R

5 16V
1u0
AP-SCART-OUT-R

5
4
PUMH7
RES
FE72

3E37-1

AP-SCART-OUT-L

IE23

1n0

2E90

1E53

IE05

1n0
100p

13

**

17

**

IE17

4E02
RES

IE96

18

5K6

3E06

1K0

3EB6-1

IE92

7E05
BC847BW

3EB6-4
4

RES
3E48

3E37-2

68R

2 100R 7

GND_A

CVBS-OUT-SC1

470R

**

4E01
RES

3E45
68R

20

MTJ-505H-01 NI LF

3E37-3

100p

RES 2E75

3
1E22

CDS4C12GTA
12V

RES

75R

3E43

6E29

2
1

1K0

1K0 6
3EA7-2

2 470R 7
3EA7-3

100p

2E44

1E25

RES 6E32

CDS4C12GTA
12V

3E62
27R

100R
3E07-2

3E07-3
3

IE52
AV1-CVBS

4K7

18p

2E98

39p

2E97

18K

100n

IE91
8

FE85

IE48

7E09-1
PUMH7

4K7

3E73
39K

1u0

3E18 2
1
2
3E19

CVBS-MON-OUT1

470R

19

FE84

100n

2E24

4K7

10u

+5V

16

9E09

21
3E44

5E80

15
2E74

100p

2E12

4E03
RES

14

RES 9E06

+3V3

AV1-BLK

IE59

12

FE83

* EU

2u2

IE14

FE82
1E19

CDS4C12GTA
12V

RES 6E28

RES

3EB3

10

RES 9E05

18R

18R

2E81

100p

RES

IE08
RES 9E08

IE51
AV2-BLK

4p7

IE70

BC847BPN(COL)

820R

** 4E04

2E99

FE81

150p

2E86

150p

1u8

7E06-1
2

9E10

5E76 3E79BEC5

IE55

IE60
1
1 3EB1 2

IE16

AV1-R

11

9E55
3E78

7E06-2

RES 9E07

AP
9E54

3 BC847BPN(COL)

9
2E14

150p

RES
YPBPR1-PR

** 4E05

FE80

1E18

1u8

18R

** 4E06

5
6

FE74

CDS4C12GTA
12V

3E77

RES 6E26

5E74
2E84

150p

2E83

IE54

IE61

100p

2E18

1E55

CDS4C12GTA
12V

FE73

FE75
AV1-G

IE89

**

330R

3E76 18R

RES 6E22

9E53

4K7

3E32

12K

+3V3

IE13

3E31

2EB3

* EU
IE18

9E52

3EA1

1
2

AV1-STATUS

AP

IE90

1E01
2EB1

2E15

1E12

(AV1)
9E01

RES

CDS4C12GTA
12V

150p

2E80

150p

2E79

18R

1R0

SCART1

1u8

YPBPR1-SYNCIN1

3EA2

3E17

2E91

1E54

AV2-STATUS
+5V

5E73 3E75
BEC3

RES 6E23

AV1-B

* EU

100n

3E74 18R

IE53

CDS4C12GTA
12V

6E09
RES

9E51

9E50

A-PLOP

2K2
RES

1K0 8

100p

2E04

AP

3E24

3E07-1

AUDIO-IN1-L

YPBPR1-PB

CDS4C12GTA
12V

RES 6E07

100p

2E10

8 100R 1

2E85

3 470R 6

*
1X06
EMC HOLE

3EB6-2
470R
3EB6-3

470R

1X02
REF EMC HOLE

100p

RES 2E76

1E23

CDS4C12GTA
12V

CVBS-OUT-SC1
RES 6E30

B04A

GND_A
4

* 3139803190010 - RSI SM 0402 JUMP 0R05 Col at 2E44 & 2E75 for Brazil

SPB SSB TV550


2K11 4DDR EU

** Provision for ESD

2010-12-10

3139 123 6495


19100_029_110210.eps
110210

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 136

Analogue externals B

Analogue externals B

B04B

GND_A

GND_A

3E89

CDS4C12GTA
12V

RES 6E46

30R

AV2-CVBS

IE75

1E07
MTJ-032-68B-46-NI-FE
1

FE59

2E22

IE73

5E06

2
FE41

AV3-PB
YPBPR1-PB

IE76

9E58

3E90

IE77

AV3-PR

18R

CDS4C12GTA
12V

1E39

100p

FE42

IE74

9E57

EU
RES 6E52

RES

2E68

4E22

IE15
SPDIF-OUT

18R

FE48

MTJ-032-21B-42 NI FE
2
1E04

AV3-Y

27R

CDS4C12GTA
12V

RES 6E51

1E28

100p

2E67

4E21

3E88

9E04

EU

1E03

IE72

YPBPR1-SYNCIN1

AP

FE51

MTJ-032-21B-45 NI FE (PBT)

3E87
18R

CDS4C12GTA
12V

RES 6E40

1E43

100p

2E27

1
GREEN

IE71

9E29

10p
1E44

EU

FE54

MSP-305H-BBB-732-03 NI
2

1E08-3

4E20

B04B

SPDIF out

YPBPR

YPBPR1-PR

GND_A

YPBPR AUDIO
+3V3

GND_A
MSP-305H-BBB-732-03 NI
4

CDS4C12GTA
12V

RES 6E38

1E42

1n0

2E40

GND_A

2E72

AV3-PR
RXD1-MIPS

9E19
9E12

RES
RES

AV3-PB
TXD1-MIPS

9E17
9E14

RES
RES

AUDIO-IN3-R
AV1-B

9E11
9E18

RES
RES

AUDIO-IN3-L
AV1-G

9E13
9E20

RES
RES

CVBS-OUT-SC1
AV1-R

9E21
9E22

RES
RES

AP-SCART-OUT-R
AV1-STATUS
AUDIO-IN1-R
AV1-BLK
AP-SCART-OUT-L
AUDIO-IN1-L

9E23
9E24
9E25
9E26
9E27
9E28

RES
RES
RES
RES
RES
RES

IE09
AUDIO-IN4-L

1K0
100p

2E35

CDS4C12GTA
12V

3E21

RES 6E19

1n0
1E37

2E36

V_NOM

FE02

2
3
1

RES
RES

AUDIO-IN3-L

1K0

VGA ( OR DVI ) AUDIO


1E09
MSJ-035-29D PPO

AV3-Y
AV1-CVBS

9E15
9E16

IE29

3E96

1E08-2

3
RES
4E24 WHITE

100p

FE49

100p

FE43

RES
1E32

AUDIO-IN3-R
IE31

1K0

2E71

RES

RES 6E06

RED

1E29

1n0

FE50
2E39

4E23

CDS4C12GTA
12V

3E97

MSP-305H-BBB-732-03 NI
6
1E08-1

100p

100R
100R

RES
1ECB
1481-702-06S-51

RES 3E58
+T

6
5
4

RES 3E56
RES 3E57

+5V

0R3

100R
100R
IE34

IE35
RES 3E36

RES 3E41

100R

IE36 RES 3E38 100R RXD2-MIPS


3D-VS
100R
TXD2-MIPS
3D-LR

FE53

FE52

BZX384-C5V1

RES 6E18

BZX384-C5V1

BZX384-C5V1
RES 6E17

RES 6E16

BZX384-C5V1

RES 6E15

1E79

100p
RES 2E26

100p
RES 2E25

1E78

100n
RES 2E23

1E76

100p
RES 2E21

RES 2E20

100p

FE46
FE45

1E77

FE47

FE44

1E75

AUDIO-IN4-R

1K0
2E38

CDS4C12GTA
12V

RES 3E54
RES 3E55

3
2
1

IE10

3E20

RES 6E20

V_NOM

1n0
1E38

2E37

FE03

31

DF50-30DP

FE01

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32

242202606017 - SOC CINCH V 3P 1L3 YEWHRDY at 1E08 for BRZ


FOR 3D

Provision for ESD


4

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_030_110210.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 137

Ethernet & Service

Ethernet & Service

B04C
3E53-2

IE49

47R
RXD1-MIPS

3E53-4

47R

+3V3

6E43

+3V3-ET-ANA

IE50
4

IE38

IE32
3E30

47R
3E53-3

FE56
1

1E06

2
3
1

FE57

MSJ-035-29D PPO (PHT)


FE58

RES
1E71

10u

2E48

100n

2E49

4n7

100n
2E53

2E52

1
2
3

TXD1-MIPS
RXD1-MIPS

25M

11
10
9
8
3E70
RES

10K
15
9E43

3E71
RES

10K

21

ETH-TXEN

22
23
24
25
18

ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)

ETH-TXD(3)
ETH-TXER

17
16

ETH-MDC
ETH-MDIO

1K5

27

12
IO

provision for BUH


P
RX
N

RST
TX

0
MODE
1
RMIISEL
PHYAD2
RXD<0:3>

P
N

TXCLK
RXDV

COL
CRS_DV
MODE2

RXER
RXD4
0
PHYAD
1
RXCLK

TXEN

REGOFF
1
LED
2
INTSEL

0
1
2 TXD
3
4
INT
TXER

CRS
RBIAS

31
30

ETH-RXP
ETH-RXN

29
28

ETH-TXP
ETH-TXN

20

ETH-TXCLK

26

ETH-RXDV

IE63

13

ETH-RXER

3E64

10K

IE64

+3V3

RES

3E65

ETH-RXCLK

10K

+3V3

RES

3
10K

3E34

10K

3E72

14

3E68
RES
3E35
RES

ETH-REGOFF

10K

+3V3
ETH-INTSEL

10K

+3V3

9E42

ETH-CRS

32
IE39

MDC
MDIO
VSS

+3V3

33

3E51

1A 2A
VDD

12K1
1%

19

CLKIN
1
XTAL
2

3E40

IE26

ETH-RXD(0)
ETH-RXD(1)
ETH-RXD(2)
ETH-RXD(3)

ETH-COL

10p

2E54

CR
5
4

3E69
RES
10K

502382-0370
7E10-1
LAN8710A-EZK

2E55

10K

10K

3E33

10p

10K
3E67 RES

3E66 RES

RESET-ETHERNETn

UART
SERVICE
CONNECTOR

47R

IE33

1M0
1E70
NX3225GA

+3V3

IE06

6E44

100n

100n
2E66

2E62

10u
2E63

30R

3E53-1

1E86

1E85

TXD1-MIPS

+3V3-ET-ANA

BZX384-C5V1

IE07

5E08
+3V3

BZX384-C5V1

B04C

7E10-2
LAN8710A-EZK
34
35

36
37

VIA

+3V3-ET-ANA

+3V3-ET-ANA

22R

22R
3E98

3E26

49R9
1%

3E99

3E95

49R9
1%

3E25

49R9
1%

3E22

49R9
1%

CONFIGURATION RESISTOR SETTINGS

ETHERNET CONNECTOR
ETH-TXP

1E87
3 ACM2012 2

FE27

1N00
FE60

ETH-TXN

FE28

ETH-RXP

FE29

1E88
3 ACM2012 2

ETH-RXN

FE31

1
FE30
FE61

22n

2E60

CDA5C16GTH
16V

6E47-4
4

CDA5C16GTH
16V
RES

6
6E47-3
3

CDA5C16GTH
16V
RES

7
6E47-2
2

CDA5C16GTH
16V
RES

RES

6E47-1

RES 27n

9 11
10 12
FE34

5450-323-183-H3

RES

15p

RES 15p
2E59

0 ohm

RES

5E04
2E58
RES

15p
3E39

2E09

RES 27n
RES 15p
0 ohm

3E29

15p

2E57
RES

RES

5E03
2E08

RES 27n

5E02
2E07

RES 15p
0 ohm

3E28

15p

2E56
RES

RES

RES 27n
RES 15p

2E05
3E27

RES

0 ohm

5E01

1
2
3
4
5
6
7
8

FE32

Resistor

POP

EMPTY

3E64

PHYADD(0) = 1

PHYADD(0) = 0

3E65

PHYADD(1) = 1

PHYADD(1) = 0

3E66

PHYADD(2) = 1

PHYADD(2) = 0

3E67

RMII mode selected

MII mode selected

3E68

Internal 1.2V reg. disabled

Internal 1.2V reg. enabled

3E69

MODE(0) = 0

MODE(0) = 1

3E70

MODE(1) = 0

MODE(1) = 1

3E71

MODE(2) = 0

MODE(2) = 1

3E72

INTERRUPT FUNCTION

INTERRUPT FUNCTION

DISABLED ON

ENABLED ON

nINT/TXER/TXD4 SIGNAL

nINT/TXER/TXD4 SIGNAL

ETH-INTSEL
ETH-REGOFF

FE33
4

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_031_110210.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 138

HDMI

HDMI

B04D
ARX2+

FEC3

MICOM-VCC33

ARX1ARX0+

3ECH

BRX2+

ARX0ARX0+

67
68

BRX2BRX1+

ARX1ARX1+

69
70

BRX1BRX0+

ARX2ARX2+

71
72

AIN-5V

BIN-5V
BRX-HOTPLUG

47K

3ECM-3

2
3ECN-2

10R

7
100K
1u0

BRX-DDC-SDA
BRX-DDC-SCL

IE43

2ECN

35
36
33
34

BRX-DDC-SCL
BRX-DDC-SDA

FECE
FECF

BIN-5V
47K

BRX-HOTPLUG

20
22

3ECA-1

BRX-DDC-SCL
BRX-DDC-SDA

BIN-5V

HDMI CONNECTOR 1

CIN-5V

3ECM-2

3
3ECN-3

10R

CRX-DDC-SDA
CRX-DDC-SCL

CRX2+

1u0

CIN-5V

PCEC-HDMI

47K

3E23
RES
7E02
BC847BW

100R

IEC4

3ECM-1

10R

BRX1BRX1+

5
6

BRX2BRX2+

7
8

IE44

41
42
39
40

2ECP

CRXCCRXC+

11
12

CRX0CRX0+

13
14

CRX1CRX1+

15
16

CRX2CRX2+

17
18

5
100K

1u0

DRX-DDC-SDA
DRX-DDC-SCL
5EC2

eHDMI+

30R
ARC-eHDMI+
2ECC

CIN-5V

7EC0
BC847BW

3ECD

+3V3-STANDBY

22K
RES

DIN-5V

4
3ECN-4

10p

20
22

47K

CRX-HOTPLUG

3ECA-3

CIN-5V

FECM
FECN

3
4

DRX-HOTPLUG

CRX-DDC-SCL
CRX-DDC-SDA
6

FECK
FECL

3ECA-4

FECA

CRXCPCEC-HDMI
ARC-eHDMI+
CRX-DDC-SCL
CRX-DDC-SDA

FECJ

CRX0CRXC+

BRX0BRX0+

6
100K

CRX2CRX1+
CRX1CRX0+

1
2

CRX-HOTPLUG

1P02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
23

BRXCBRXC+

IE45

2ECQ

45
46
43
44

DRXCDRXC+

19
20

DRX0DRX0+

21
22

DRX1DRX1+

23
24

DRX2DRX2+

25
26

IEC6
9EC0

CEC-HDMI

IEC5

100n

49

10K

CEC_D

N
R0X0
P

2EC3

38

37

9
27
64

DSCL4
DSDA4

48
47

VGA-SCL-EDID-HDMI
VGA-SDA-EDID-HDMI

51

9EC2
RES

CEC-HDMI

N
R0X1
P
N
R0X2
P
(CBUS) HPD1
R1PWR5V
DSDA1
DSCL1

TX2

N
P

TX1

N
P

TX0

N
P

TXC

N
P

3ECA-2

BRXCPCEC-HDMI

BIN-5V

BRX0BRXC+

R4PWR5V

N
R0XC
P

N
R1XC
P
N
R1X0
P

57
56

HDMIA-RX2HDMIA-RX2+

59
58

HDMIA-RX1HDMIA-RX1+

61
60

HDMIA-RX0HDMIA-RX0+

63
62

HDMIA-RXCHDMIA-RXC+
3ECJ RES

N
R1X1
P

TPWR_CI2CA

N
R1X2
P

CEC_A

(CBUS) HPD2
R2PWR5V

INT

55

50

52

4K7
IE12
FECR

RES
3ECK

MICOM-VCC33

4K7
9EC3
RES

FECY

PCEC-HDMI
3ECL RES

+3V3

4K7

DSDA2
DSCL2
N
R2XC
P

CSCL
CSDA

N
R2X0
P
RSVDL

N
R2X1
P

54
53

10
28

N
R2X2
P
(CBUS) HPD3
R3PWR5V
DSDA3
DSCL3
N
R3XC
P
VIA

N
R3X0
P
N
R3X1
P
N
R3X2
P

3EC3
3EC5

100R
100R

SCL-SSB
SDA-SSB

10p

ARXCARXC+

DSDA0
DSCL0

+5V-EDID
10K
3ECP-3

29
30

(CBUS) HPD0
R0PWR5V

2ECM

31
32

65
66

HDMI CONNECTOR 2

FECC
FECD

+3V3

30R

10p
RES 2ECY

1u0

ARX-DDC-SDA
ARX-DDC-SCL

IE42

RES 2ECX

10R

8
100K

3ECP-1

1
3ECN-1

SBVCC33

AIN-5V

3ECM-4

MICOM_VCC33

1
47K

3EC1-1

ARX-HOTPLUG

ARX-HOTPLUG

10u

RES 2ECW

100n

100n
2EC8

VCC33

AIN-5V

20
22

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FECG 21
23

100n
2EC7

2EC6
6
47K

3EC1-3
3

7EC1
SII9187B

ARX-DDC-SCL
ARX-DDC-SDA

FEC4
FEC5

RES
5EC3

FEC7
+3V3-HDMI

ARXCPCEC-HDMI
ARX-DDC-SCL
ARX-DDC-SDA

SII9187B = 0xB2

FECB

AIN-5V

ARX0ARXC+

FEC1
FEC2

I2C Address

10K

1u0

10u

2ECV

2EC0

FEC0

ARX2ARX1+

1P03

74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89

7EC1

3ECN

3ECF

NON-INSTAPORT

9187A

4 3K3

3K3

NON-INSTAPORT

9187B

4 100K

100K

INSTAPORT

9287B

4 100K

100K

73

EPAD

3ECE

22K

IEC7
FECW
+3V3-STANDBY

6EC1
+5V

+5V-VGA
BAT54
IE11

3ECG
3ECF

4R7

FECP

220u 16V

RES 2EC1

HDMI CONNECTOR 3
1P04
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FEC6 21
23

30R

2EC2

5EC0
+3V3

100n

B04D

FECZ

100K

DDCA-SDA

IE65

3ECU-2

+3V3

10K
2ECU

DDCA-SCL

IE66

4 3ECU-4 5
10K

1u0

+5V-EDID

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_032_110210.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 139

Headphone

Headphone

B04E
+3V3-STANDBY

4
PUMD12
7EE0-2
A-PLOP
3

A-STBY

FEE0
2

RESET-AUDIO

7EE0-1
PUMD12
1

2EE0

22K

3EE1-3

3EE1-4

22K

3EE1-2

22K

47p
3EE1-1

22K
2EE5

7EE1
TPA6111A2DGN

100n

2EE1

47p +3V3

IEE2
ADAC(4)

2EE3
1u0

IEE1
2EE4
1u0

3EE0-1
10K

IEE3
1

2
5

3EE0-4

10K

6
IEE4

5
2EE2

AMPLIFIER

3 3EE0-3 6

2EE6

IEE7

33R
3EE2-4

6
FE36

VO

SHUTDOWN
BYPASS

VIA
GND GND_HS

2EE7

IEE8

4V 100u

10
11

AMP1

33R

4V 100u

3EE2-3

3EE2-2
33R
3EE2-1

FE35
7

AMP2

33R

IEE5

10K
22K

A-PLOP

IN-

1u0

IEE6

VDD

IEE0
ADAC(3)

RES 3EE3

B04E

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_033_110210.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 140

10-5 B05 313912364954


DDR

DDR2-CLK_N
3B28
240R

DDR2-CLK_P
DDR2-CLK_N

G2
G3
G1

DDR2-BA2

DDR2-ODT
RES
240R

3B01
DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM2

F9
E8
F8
F2
G8
F7
G7
F3
B3

3B23

DQ

0
1
2
3
4
5
6
7

DQS

C8
3
C2
D7
1
D3
D1
D9 3B00-4 4
B1
B9 3B00-1 1

NU|RDQS

2
6 3B02-3
33R 3
8 3B02-1
33R 2
3B02-2
5
4
3B02-4
33R
8
33R

B7
A8

3B00-2

7
33R
6 3B00-3
33R
7
33R
5
33R

3B12
33R

3B13
2B44
RES

0
1 BA
2

2p2

DDR2-D16
DDR2-D17
DDR2-D18
DDR2-D19
DDR2-D20
DDR2-D21
DDR2-D22
DDR2-D23

DDR2-DQS2_P
DDR2-DQS2_N

33R

A2

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

G2
G3
G1

DDR2-BA0
DDR2-BA1
DDR2-BA2

DDR2-ODT

ODT

3B03

CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

NC

L3
L7

DDR2-A14

VSSQ

VSSDL

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM3

RES
240R

F9
E8
F8
F2
G8
F7
G7
F3
B3

3B24
33R

2B17
100n
2B37
100p
VDD

VDDL

VDDQ

E2

A9
C1
C3
C7
C9

E1

A1
E9
L1
H9

100n

100n
2B16

100n
2B15

100n
2B14

100n
2B13

100n
2B12

100n
2B11

100n
2B10

47u
2B09

E2

A9
C1
C3
C7
C9

E1

SDRAM

A3
E3
J1
K9

33R

2B41

2B36
100p
2B08
100n

DDR2-BA0
DDR2-BA1

B05A

VREF

0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

SDRAM
DQ

0
1
2
3
4
5
6
7

DQS

C8
C2
3B05-3
D7
3B04-3
D3
D1
D93B04-4
B1
B93B04-1

3
3

4
1

B7
A8
2B45

0
1 BA
2

NU|RDQS

3B04-2
2
7
33R
6
6 33R
33R
33R 2
7 3B05-2
1
8 3B05-1
33R
5
5 3B05-4
33R
4
8
33R
33R

3B15
RES
2p2

3B14
33R

DDR2-D24
DDR2-D25
DDR2-D26
DDR2-D27
DDR2-D28
DDR2-D29
DDR2-D30
DDR2-D31

DDR2-DQS3_P
DDR2-DQS3_N

33R

A2

ODT
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

+1V8

NC

L3
L7

DDR2-A14

VSSQ

VSSDL

A7
B2
B8
D2
D8

DDR2-CLK_P

7B03
EDE1108AGBG-1J-F

VREF

VDDQ

DDR2-VREF-DDR

E7

3B27
240R

VDDL

A3
E3
J1
K9

DDR2-CLK_N

VDD
0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

A7
B2
B8
D2
D8

DDR2-CLK_P

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

E7

3B22
240R

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

A1
E9
L1
H9

7B02
EDE1108AGBG-1J-F

AT T-POINT

+1V8

DDR2-VREF-DDR

100n

100n
2B07

100n
2B06

100n
2B05

100n
2B04

100n
2B03

100n
2B02

100n
2B01

47u
2B00

+1V8

2B40

B05A

DDR

+1V8
DDR2-VREF-DDR

3B25
33R

DQ

0
1
2
3
4
5
6
7

DQS

C8
C23B08-4 4
D7
D3 3B08-2 2
D1
D9 3B07-4 4
B1
B9 3B07-1 1

B7
A8
2B46

0
1 BA
2

NU|RDQS

2
5
33R
7
33R
5
33R
8
33R

3B17
RES
2p2

3
1
3

3B07-2

7
33R
6 3B07-3
33R
8 3B08-1
33R
6 3B08-3
33R

3B16
33R

DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D4
DDR2-D5
DDR2-D6
DDR2-D7

DDR2-DQS0_P
DDR2-DQS0_N

33R

A2

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

G2
G3
G1

DDR2-BA0
DDR2-BA1
DDR2-BA2

DDR2-ODT

ODT

3B09

CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

NC

VSSDL

L3
L7

DDR2-A14

VSSQ

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM1

RES
240R

3B26
33R

F9
E8
F8
F2
G8
F7
G7
F3
B3

2B35
100n
2B39
100p
VDD

VDDL

VDDQ

E2

A9
C1
C3
C7
C9

E1

A1
E9
L1
H9

100n

100n
2B34

100n
2B33

100n
2B32

100n
2B31

100n
2B30

100n
2B29

100n
2B28

47u
2B27

2B43

2B26
100n
2B38
100p
E2

E1

SDRAM

VREF

0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

SDRAM
DQ

0
1
2
3
4
5
6
7

DQS

C8
C2
3B11-3 3
D7
3B10-3 33R 3
D3
D1
D93B10-4 4
B1
B9 3B10-1 1

B7
A8
2B47

0
1 BA
2

NU|RDQS

6
6 33R

2 3B10-2 7
33R

2
1
5 3B11-1
33R
4
8
33R

3B19
RES
2p2

7 3B11-2
8 33R
33R
5 3B11-4
33R

3B18
33R

DDR2-D8
DDR2-D14
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D9
DDR2-D15

DDR2-DQS1_P
DDR2-DQS1_N

33R

A2

ODT
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

NC

VSSDL

L3
L7

DDR2-A14

VSSQ
A7
B2
B8
D2
D8

180R 1%

3B21

DDR2-VREF-DDR

F9
E8
F8
F2
G8
F7
G7
F3
B3

0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

E7

180R 1%

3B20
FB00

RES
240R

3B06
DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM0

7B01
EDE1108AGBG-1J-F

VREF

A3
E3
J1
K9

DDR2-BA2

DDR2-ODT

VDDQ

A7
B2
B8
D2
D8

G2
G3
G1

DDR2-BA0
DDR2-BA1

VDDL

E7

+1V8

VDD

A3
E3
J1
K9

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

A1
E9
L1
H9

7B00
EDE1108AGBG-1J-F

A9
C1
C3
C7
C9

100n

100n
2B25

100n
2B24

100n
2B23

100n
2B22

100n
2B21

100n
2B20

100n
2B19

47u
2B18

2B42

DDR2-VREF-DDR

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_034_110210.eps
110210

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 141

10-6 B06 313912364954


Display interfacing-Vdisp

Display interfacing-Vdisp

B06A

1G03
T 3.0A 32V

5G01

FG0H

1G00

+VDISP-INT
100n

T 3.0A 32V
RES

2G43

+VDISP
30R
RES
5G02

22u
RES

30R
RES
2G44

B06A

RES
3G28
2K2

IG11

RES
6G00
LTST-C190KGKT

For Development use only

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_035_110210.eps
110210

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 142

Video out - LVDS

Video out - LVDS

B06B

2G94

100n

FG2J

2G95

100n

FG30
FG31
FG32
FG33

FG11
FG1J

PX3DPX3D+
PX3EPX3E+

FG1K
FG1L
FG1M
FG1N

PX4APX4A+
PX4BPX4B+
PX4CPX4C+

FG12
FG13
FG14

PX4CLKPX4CLK+
PX4DPX4D+
PX4EPX4E+

FG15
FG16
FG17
FG18
FG19
FG1A
FG1B
FG1Q
FG1P

100R
100R
100R
100R
100R
100R

FG35
FG2R
FG2K

FG04

47p

47p

60 61
58 59
56 57
54 55
52 53

2G27

2G26

47p
2G25

47p
2G24

2G7A

47p

47p
2G79

47p

47p
2G78

2G76

47p

FI-RE51S-HF

FG2L
FG2M

PX1APX1A+
PX1BPX1B+
PX1CPX1C+

FG2E
FG2F
FG1Y
FG1Z
FG20
FG21

PX1CLKPX1CLK+

FG22
FG23

PX1DPX1D+
PX1EPX1E+

FG24
FG25
FG26
FG27

PX2APX2A+
PX2BPX2B+
PX2CPX2C+

FG28
FG29
FG2A
FG2B
FG2C
FG2D

PX2CLKPX2CLK+

FG1R
FG1S

PX2DPX2D+
PX2EPX2E+

FG1T
FG1U
FG1W
FG1V

2G28
2G29

47p
47p

FG2P

RES 9G0G

FG2N

+VDISP

1G50

TO DISPLAY

EMC 100n
RES 2G9C

PX3CLKPX3CLK+

RES 3G38
RES 3G37
RES 3G2Z
RES 3G36
RES 3G30
RES 3G31

BACKLIGHT-BOOST
3D-LR
3D-VS-DISP
CTRL-DISP
CTRL-DISP

41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

FG1C
FG1D
FG1E
FG1F
FG1G
FG1H

CTRL-DISP

EMC 100n
RES 2G9E

PX3APX3A+
PX3BPX3B+
PX3CPX3C+

47p
47p
47p
47p

FG34
FG2H
FG2G

EMC
RES 2G9F

2G96
2G99
2G97
2G98

100R
100R
100R

100n

100n

RES 3G32
3G2W
3G2Y

100n

2G93

CTRL-DISP

SDA-DISP
SCL-DISP

FI-RE41S-HF
51
50
49
48
46
47
44
45
42
43

2G91

100n

EMC 100n
RES 2G9D

2G92

2G75

47p
2G77

RES 3G35

RES 3G34

9G0K-4
9G0K-3
9G0K-2
9G0K-1

RES 3G33

5
6
7
8

RES

10K

10K

+VDISP

10K

+3V3

4
3
2
1

B06B

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

1G51

TO DISPLAY

1X05
REF EMC HOLE

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_036_110210.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 143

AmbiLight CPLD

AmbiLight CPLD

B06C

B06C

5GA0

FGA0

+3V3

VINT

5GA1

100n

100n
2GA2

2GA1

1u0

2GA0

30R

DEBUG ONLY

FGA1

+3V3

VIO

+3V3

100n

10K
RES

4
3
2
1

5
6 100R
7 100R
8 100R
100R

26

IGA2
CPLED3

IXO4_19
IXO4_20
IXO4_21
IXO4_22
IXO4_23
IXO4_27
IXO4_28

PNX-SPI-CSBn
BACKLIGHT-PWM
3D-LR
3D-VS-DISP
BL-SPI-SDO
BL-SPI-SDI
BL-SPI-CSn
BACKLIGHT-PWM_BL-VS
BL-SPI-CLK

9GA1 RES

3GA1

4
3G10-4
2
3G10-2

19
20
21
22
23
27
28

3G12
3
3G11-3

RES
47R
5
3
33R
7 3G10-3
33R
3G13
10R
1
6 3G10-1
33R

TCK
TDI
TDO
TMS

IGA3
GCK2
+3V3
3
5

GCK3

AMBI-SPI-CS-EXTLAMPSn
AMBI-SPI-CLK-OUT
AMBI-SPI-SDI-OUT_G1
AMBI-SPI-SDO-OUT
AMBI-LATCH2_DIS

33R
8
33R

GTS1

3
5

GTS2

7GA2-2
BC847BS(COL)
4

4
17
25

330R 3

3GA6-3

3GA6-1

FGA3
+3V3

SD51022

BACKLIGHT-PWM

9GA0

6GA3

FGA5
FGA2

LTST-C190KGKT

FGA4

6GA2

FGA6
LTST-C190KGKT

1
2
3
4
5
6

6GA1

100R
100R
100R
100R

LTST-C190KGKT

8
7
6
5

6GA0

1
2
3
4

LTST-C190KGKT

2GA4

100n RES

3GA2-1
3GA2-2
3GA2-3
3GA2-4

330R 2

RES
1G36
1
2
3
4
5
6

7GA2-1
BC847BS(COL)
1
3GA6-2

DEBUG ONLY

6
2

+3V3

GSR

RES
1G35

7GA1-1
BC847BS(COL)
1

+3V3

GND

+3V3

7GA1-2
BC847BS(COL)
4

+3V3

AMBI-PROG_B1
AMBI-BLANK_R1

6
33R

3GA6-4

IXO2_29
IXO2_30
IXO2_31
IXO2_32
IXO2_37
IXO2_38

5
6
7
8
12
13
14
16
18

5 330R 4

IXO2_36|GTS1
IXO2_34|GTS2
IXO2_33|GSR

IGA1
CPLED2

330R 1

11
9
24
10

IXO3_5
IXO3_6
IXO3_7
IXO3_8
IXO3_12
IXO3_13
IXO3_14
IXO3_16
IXO3_18

10p

29
30
31
32
37
38

3GA5-4
3GA5-3
3GA5-2
3GA5-1

SD51022

10p
2G19 RES

33R
2
33R

10p

10p
2G12 RES

10p
2G11 RES

10K

2G10 RES

3G14
1
7
33R
3G11-2

8
3G11-1

IXO1_2
IXO1_3
IXO1_39
IXO1_40
IXO1_41
IXO1_42

10p
2G18 RES

36
34
33

GTS1
GTS2
GSR
AMBI-SPI-CS-OUTn_R2-R
AMBI-PWM-CLK_B2
AMBI-SPI-CS-OUTn_R2
AMBI-LATCH1_G2
AMBI-TEMP
CPLED3
CPLED2

3G15

33R

GCK3
GTS1
GTS2
GSR

AMBI-SPI-CLK-OUT-R
AMBI-SPI-SDI-OUT_G1-R
AMBI-SPI-SDO-OUT-R

10p
2G16 RES

3GA3

VCCIO

10p
2G15 RES

PNX-SPI-CS-BLn
PNX-SPI-SDO
PNX-SPI-SDI
PNX-SPI-CLK

2
3
39
40
41
42

VCCINT
IXO1_43|GCK1
IXO1_44|GCK2
IXO1_1|GCK3

10p
2G14 RES

43
44
1

2G13 RES

PXCLK54
GCK2
GCK3

15
35

7GA0
XC9572XL-10VQG44C0100

VIO

1
2
3
4
5
6

+3V3

10p
RES

VINT

2GA6

3GA4

RES
1G37

10p
2G17 RES

2GA5

1u0

2GA3

30R

BACKLIGHT-PWM_BL-VS

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_037_110210.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 144

SPI buffer

SPI buffer

B06D

+3V3

20

3GE2

3EN1
3EN2
G3
PNX-SPI-CLK

PNX-SPI-SDO

PNX-SPI-CSBn

7GE0
74LVC245A
1
IGE0

19

1
2

17
16
15
14
13
12
11

3GE0-3
47R

3
4
5
6
7
8
9

3GE1-3 6

3
47R RES
3GE3
47R

3GE4

BL-SPI-CLK
1

3GE0-1

8
47R
4 3GE1-4
47R RES

BL-SPI-SDO
AMBI-SPI-CLK-OUT-R
AMBI-SPI-SDO-OUT-R
PNX-SPI-SDI

RES

47R

10

AMBI-SPI-SDI-OUT_G1-R
BL-SPI-SDI

18

7GE1
PDTC114EU

10K

100n

+3V3

2GE0

B06D

PNX-SPI-CLK

9GE0-2

BL-SPI-CLK

PNX-SPI-SDO

9GE0-3

BL-SPI-SDO

9GE1

BL-SPI-SDI

9GE2
PNX-SPI-CS-BLn

IGE1

5 9GE0-4

PNX-SPI-SDI

BL-SPI-CSn

Buffer
Direct

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_038_110210.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 145

10-7 B07 313912364954


DVBS-FE

DVBS-FE

B07A

7R01-1

STV0903BAC

100n

10n

2R15

100n

2R14

10n

2R09

+3V3-DEMOD

130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165

VDD1V0

21
38
54
76
80
92
96
106

+3V3-DEMOD

10n

10n

2R52

10n

2R51

100n

2R50

100n

2R49

100n

2R48

2R47

100n

2R46

22u

2R16

30R

VIA

VDD3V3

2
3
100n

2R17

+1V-DVBS

11
12

VDDA2V5

8
7

IM
IP

60
56
RES 2R21

DISECQ-DET
F22-DISECQ-TX

128
20
126
NC
107
NC
IR04
47p
97
98
3R00 IR03
19
18

1n0

RES 2R22
SCL-SSB
SDA-SSB

100R
RES 2R23

3R01
100R
47p

SCLT
SDAT

RESET-DVBS
9R00
RES

3R11
+3V3-DVBS
10K

IR02

62
58
26
23
24
29
27

FR02
FR03
FR04
FR05
FR06

FR07

XTALO

AGCRF1

I2C-ADDRESS : D0
DIRCLK
CLKI
CLKI2
CLKOUT27
N
I1
P

N
Q1
P

0
1
2
3
D
4
5
6
7
CLKOUT
STROUT
DPN
ERROR

0
CS
1
DISEQCIN1
DISEQCOUT1
FSKRX_IN
FSKRX_OUT
NC
SCL
SDA
SCLT
1
SDAT

RESETB
STDBY
TCK
TDI
TDO
TMS
TRST

0
COMP
1
1
2
3
4
5
6
GPIO 7
8
9
10
11
12
13

52

SENSE+1V0-DVBS

63
64
65
67
68
70
71
73
74
75
78
79
82
83
84
86
87
89
90
91
94
95
108
109
111
115
116
119
120

AGC

2R53

1K0

47n

* To be drawn near PNX85500


3R03
3R04
3R05
3R06

47R
47R
47R
47R

NC

NC
NC
NC

TS-DVBS-DATA 4
TS-DVBS-CLOCK
TS-DVBS-SOP 2
TS-DVBS-VALID 1

9R03-4 * 5
9R04 *
9R03-2 * 7
9R03-1 * 8

TS-FE-DATA
TS-FE-CLOCK
TS-FE-SOP
TS-FE-VALID

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

40
41
101
50
49
47
46
44
43
37
35
34
32
30
55

FR00

3R02

16

IR05

3R07
120K
DISECQ-RX

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

100n

2R26

100n

2R25

100n

2R24

100n

100n

2R19

+2V5-DVBS
2R18

VDDA1V0

5
9
13
114
118
123
127

NC

QM
QP

129

GND_HS

IR00

5R00
+3V3-DVBS

NC

59
104
103
100

VS

6p8

GNDA

NC

124

MAIN

XTALI

2R20 RES

10n

100n

2R13

10n

2R12

100n

2R11

10n

2R06

2R05
2R08

100n

2R07

+1V-DVBS

1
4
6
10
14
113
117
121
125

1K0

100n

10n

2R10

100n

2R03

10n

2R02

100n

2R01

2R00

100n

2R04

+1V-DVBS

POWER_VIA

3R10

15
17
22
25
28
31
33
36
39
42
45
48
51
53
57
61
66
69
72
77
81
85
88
93
99
102
105
110
112

+1V-DVBS

122

XTAL

10K

7R01-2
STV0903BAC

3R13

B07A

+3V3RF
3R12

IR06

10p

9R02
RES
NC

16
23
24

XTAL_CMD
SCL
SDA

SYN
XTAL_OUT
IP
IN

SATELLITE
TUNER
I2C-ADDRESS : C6

QP
QN
RF_OUT

AGC
AS
NC

5R01

2R43

+3V3RF

IR01

VIA

RF_IN

18
19

10u

3R09

2R40

1K0

100p
3
3R08-3

21
20
7
34
35
36
37
38
39
40
41
42

XTAL

2
3R08-2
NC

4
6 3R08-4
100R
1
7 3R08-1
100R

5
100R

QP
QM

8
100R

IP
IM

SYN HS
29 33

0p56

2R62

32

100p

2R45

1n0

2R29

SM15T

FR01

6R00

LNB-RF1

GND
RF LNA LT MIX DIG BB VCO
5
3
9 10 15 17 25 26

27n

5R02

10n

2R28

2R27

220u 6.3V

27p
10u

2R61

28

1R01

+3V3-DVBS

1n0

1n0
2R35

1n0
2R34

1n0
2R33

VCO

10p

AGC

27

10p

12
13

22

2R55

10p
IR08

14

MIX DIG BB
VSS

2R56

11

XTAL_IN

1 2

2R39

10p

NC

16M

2R38

31

IR07

SCLT
SDAT

LNA LT

10p

7R02
STV6110AT

3 4
30

10K

3R15 RES

10K

3R14 RES

10p

2R54

+3V3RF

2R41

1R10
NX3225GA

2R37
+3V3RF

1n0
2R32

2R31

4R7

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_039_110210.eps
110210

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 146

10-8 B08 313912364954


DVBS supply

DVBS supply

B08A
5T00

IT00

SYNC
A
4

5T01

+1V-DVBS

VFB

GND
P HS
8
9

3T00 RES

15

14

1%

IT24

SENSE+1V0-DVBS

4n7
3T21

100n

2T06

11

+3V3-DVBS

4n7
2T36

3K3

12

22K
3T02

VIA

IT20

47K

1K0 1%
2T10 RES

IT02
13

10
3T03

FT06

IT18

2u0

RES 3T01

7T00-2
ST1S10PH

IT01

SW

VIN

22u

INH

RES 1n0

2T03

+2V5-DVBS

22u
2T05

1
A

2T04

7T00-1
ST1S10PH

22u

22u

2T02

22u

2T01

2T00

30R

SW

+5V-DVBS

1K0 1%
LD3985M25
7T01
IN

BP

FT07

5
4

+2V5-DVBS
IT19

COM
2

5T02

INH

30R

100n

2T07

OUT

1u0

1u0

IT03

2T39

BAS316

2T08

6T02 RES

BAS316

10n

6T00 RES

BAS316

2T09

6T01 RES
+5V-DVBS

7T02
LD1117DT33
OUT

FT08

+3V3-DVBS
16V

IN

2T12

100n

2T11

COM
1

22u

+24V

220n
2T17

100u 35V

IT05

5T03

FT00

2T16

47n
2T14

3R3

2T13

220n

IT04

100u 35V
2T15

3T04

10K

3R3

10K

5T04

4u7

RES 2T22

4u7

RES 2T38

10u

1n0

IT11

RES 2T37

10u

2T24

2T23

6T04

SS24

22R

3T11

33u

100u 25V

+V-LNB
IT32

GND_HS

IT17

1n0

IT12

3T29
3T08

3T10

IT09

15

10u

2T35

GND

7T04-1
BC847BS(COL)
1

13
12
6
8

2T26

1n0

2T25
2

IT10

47n

16
17
18
19
20
21
22
23
24
25
26

ILIM2
SEQ
BP

100K

3T06
IT21

BOOT2
SW2
EN2
FB2

IT27

6
3T07

IT26

VIA2

IT08

+3V3

PVDD2

2T27

9
10
11

BOOT1
SW1
EN1
FB1

1K0

1n0

2T21

2
3
5
7

IT07

+24V

10K

PVDD1

2T20

14

7T03
TPS54283PWP
IT25

IT06

22R

3T05

22u

6T03

SS24

33u

220u 16V
2T19

2T18

+5V-DVBS

RES
3T31

IT29

3T23

IT13

33K

2T41
RES
2T28

1n0
FT04

RES

+V-LNB

4u7

RES
3T24

SENSE+1V0-DVBS

15K

220p

2T40
2T31 RES

RES
2T29

47K
5%
RES

47K

3T16

3K3
5%

3T15

IT14
2T30 RES

3T17

7T04-2
BC847BS(COL)
4

22n
3T12

3K3

5
IT23

22n

3T14
2K2

BZX384-C
13V

1K0

IT22

6T05
+24V

3T13

IT15

3T25

3K3

V0-CTRL

330K
3T28
100K

RES 10n

RES
IT16

RES 10K

100n
RES

3T26
2T43

RES 2T34

IT30

2T42

22n

RES
3T19

33K

3K3
5%

3T18

18K
5%
22u

22u

2T33 RES

22n
3T20

RES 3T09

+5V-DVBS

2T32 RES

B08A

SPB SSB TV550


2K11 4DDR EU

FT05

2010-12-10

3139 123 6495


19100_040_110210.eps
110210

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 147

DVBS supply

B08B

DVBS supply

B08B
+12V

+12V

+3V3-DVBS

3T22

220R

22u

RES

5T50

100R

3T50

100n

2T51

2T50

RES

100u 35V

IT50

IT28

220n

2T52

V0-CTRL

IT60
5T52

6T50

220n

2T53

BAT54 COL

18
NC

BYP

A_GND
7T50-2
LNBH23Q
34
35
36

2K2

DISECQ-DET

IT64
6T54 RES

RES
7T51
BC817-25W

IT68

BAS316

IT69

IT59
9T52 RES

VIA
VIA

IT55

10n

10u

3T58 RES

2T62 RES

1R0

2T60

2K2

STPS2L30A

6T51

+3V3-DVBS
10K

2T61

20

3T57 RES

RES

VUP

1
2
3
7
8
16
17
23
24
25
26
31
32

IT66

IT67

150R

VCTRL

11

3T62

22R

TTX

15R

3T59 RES

VCC_L

DSQOUT

EXTM

470n

VIA

DISECQ-RX

39
40

VIA
37
38

2T59

470n

15
2T58

100u 35V

IT58

DSQIN

22

3T27

27

2T57

470n

RES

VOTX

LNB-RF1

3T53

21

3T54 RES

IT57

5T51

DETIN

22K

1n0

14
30

30R
2T56

100u 35V

2T55

12
13

+V-LNB

VORX

3T52

IT54
29

IT63
9T51

IT65

RS1D

RES

9T50
RES

ADDR

28

IT52

220u

RES

IT56

F22-DISECQ-TX
6T53

STPS2L30A

6T52

RS1D

6T55

10K

ISEL

GND_HS

DISECQ-DET

10

10K 3T55 RES


2T54 RES
IT61
IT62
10K
3T56 10n

IT53

LX

P_GND

LNB-RF1

100R

SCL
SDA

3T60 RES
+12V

9
6

3T61

SDA-SSB

33

100R

IT51

41
42

SCL-SSB

VCC

3T51

19

7T50-1
LNBH23Q

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_041_110210.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 148

10-9 B09 313912364954


Connectors comp

Connectors comp
5C55
30R

1M59

FC77

FC76
FC78
3C70

100R

FC79

100n

2C70

FC81

GND_AL
NC

FC83

FC82

1C86

AMBI-POWER

+24V

+12V_AL

100n
RES

2C95

1C87

100n

FC84

2C94

T 2.0A 63V

27

2C96
T 2.0A 63V
RES

28

100R

2C77

3C76

100p

IC73

100R

2C78

IC74

3C77

100p

2C93
RC

47n RES

LED-2

TO
LED PANEL

100R

FC90
FC91
FC92
FC93

2C79
LED-1

3C78

100p

100R

2C80

FC94
+5V

100p
FC95

KEYBOARD

1
2
3
4
5
6
7
8

FC89

+3V3-STANDBY

IC75

1M19

FC88

100n

AMBI-BLANK_R1
AMBI-PROG_B1
AMBI-LATCH2_DIS
AMBI-TEMP

100p

2C81

V-AMBI

3C75

6C02

FC75

FC87
LIGHT-SENSOR

3C79
10R

100p

FH34SJ-26S-0.5SH(50)

2C82

100n
RES

RES

FC74

6C05

AMBI-SPI-CS-OUTn_R2
AMBI-LATCH1_G2

2C76

RES
BZX384-C5V6

FC73

AMBI-PWM-CLK_B2

BZX384-C5V6

FC72
V-AMBI

6C03 RES

FC71

BZX384-C5V6

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

100K
RES

FC70

AMBI-SPI-CLK-OUT
AMBI-SPI-SDO-OUT
AMBI-SPI-SDI-OUT_G1

B09A

+3V3

3C74

B09A

GND_AL GND_AL

1M21 RES

FAN-CTRL1

+3V3
FC61

RES 3C90
10K

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

RES 3C91
100R

3C97

RES
RES

47R
47R
47R

10K

FAN-DRV

1u0

100R

RXD2-MIPS

RES

1u0
2C91

2041145-4

TEMPERATURE
SENSOR

3C96

RES

10p

RES 3C93

TXD2-MIPS

3C95

2C90

+3V3

RES 3C92

SDA-SET

+3V3-STANDBY
+5V

47R

10p
2C89 RES

FC64

19
20
FH52-18S-0.5SH

FC99

HOTEL TV

RES 5C53
+12V

30R

T 1.0A 63V

30R

IC78

Dreamcatcher

1u0

RES 5C54
+3V3

RES
1C85

FAN-CTRL2

1
2
3
4

3C94

10p
2C88 RES

100R

FC98

9C00
RES
9C01
RES
9C02
RES
9C03
RES

10p
2C87 RES

100R
RES 3C83

FC86

FC97

SCL-SET

2C86 RES

RES 3C82 100R

FC96

RES 2C85

SDA-BL

FC63

RES
1M71

100p

TACH02

FC85

100R
RES 3C81

100p
RES 2C84

SCL-BL

RES 3C80

RES 2C83

TACH01

FC62

RESERVED
4

SPB SSB TV550


2K11 4DDR EU

2010-12-10

3139 123 6495


19100_042_110210.eps
110210

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 149

10-10 313912364954 SSB Layout

2G43

IUS9

2UD9
3U26

5UD3

2UE4

9UU1 9UU0

5T01

2T19

3GA6

1G37

2UU2

5G02

2T32

2T33

6GA1

3UD3

2UD6 6UD0

3US3

3US2

IUS6

2UE1

3UD4

2UD4 2UD5

7GA2

1G00

1X08

3US9 3US6

2U15

3UD5

2UE2

5U01

5C53

3U29

IU15

2UE3

5C54

2U16

2UE6

6U00

IU17

2C85

3C82

2UD8

7US3

2U09
3C93

3C92

1C85

7US2

2C83
2C84

3U24

2US3

IU18

IUD2

2U18

3C90

2U11

3C91

IUT1

IUS5

2U17

3C81
3C83

5U00

IU23

2T00

2T18

5UD0

IUD4

7UD1

IUT2

2T01

2T12

6GA2

2UD2

IUD1

5T03

6GA3

2UD1

6GA0

2U27

3UD2

3U06

2UD7

3UD0

2U28

3U07

7UD0

3US7

3C80

5UD1

2UE0

3US5

7US1

7U05

5UD2

9US0

3US4

3U23

7U01 7U04 7U02

7UU0

1M71

IUS4

2UE9

IUS3

IU57

2UD3

3UD1

5U03

5U02

2U19

2U25

2U23

2U24

2UE8

7UD3

2UE7

2U20

2UD0

2T22

7T03

7T00
5T00

3U81

IUD0

2T17 5T04

2T11

3C70

2C70

2C96

2G13
3G12

3G13

2C95

3G10

3G14

3G11

6T03

2T14

1C87
1C86

1UM0

5UM1

2U56

3U56

3U44

2U43

2U52

2U51

3U66

3U84

3U67

2U72
3U76

2U48

2U54

3U71

2U47

2U68

2U49

3U45

2D30

2U53

2U45

3U43

2U44

2U58

4U00

3U64

2C94

5C55

3U42

3U65

4U01

2U46

1M59

1M99

CXXX

2U50

1M95

7T02

Overview top side

3GA5

1P00

7GA1

1X07

5G01

1G36

2G44
1G03

3GA2

3G15

6G00

3G28

1G35

IG11

2GA4

7GA0

3B11

IGA3

3B18

IGA2

3S3Y

3S28

3S24

3S29

3S2A

9F27

3B00

3S1C

5D07

2R28
2R32

2R45

2R33

9R02

2R29

3R14
3R15

1R01
5R02

2R31

7R02

2R40

1R10

3R09

2R38

2R35

2R61

2R39

2R62

2R43

1X04

6T55

2T50

3S1B

9F28

3S3N

3S3R

3B13

3S1L

3S3T

2S4D

3S1J

3B12

2T55
6T52
3T22

3S1K

3B23

2R27

2R37

3S3S
2S4E

2B44

3S23

3S62
3S21

3S3Q

3S03

9S01

7R01

2R34

2T57

3S02 3S01

3B02

7S00

2S09
3S04

7S02

3S31

7B02

2R46
3R06

3R08

3R05

9S00

2D20

1X05

3R04

3B17

2R54

2R20

3R03

3B25
3B16
2B46

7B00

5R01

2R55

9S93

9S90

3B08

9S92

3B10

7F20

3B07

2D05

5D08

2D19

2G96

9S91

2S4P

2G97
2G99

2R56

2G98

2R41

IGA1

3R12

3B19

2F01

7B01

3GA1

3B26
2B47

1G50

9GA0

7T50

3S3L

2T56

2S87
3S59

2S7L

2S7P

2S7N

2S7U

2S8G
9S18

9S20

3S4T

3S4P

2S7R
9S19

3S4R

2S7E
9S21

BS10

3S4J 2S7J

2S7K

2S7H

3S4L

3S4K

3S3W

3S4A

3S84

2G29
2G28

1E22

1E54

1E31

5T50

1E25

2F29

3F37

3F36

7F25

2F33

2F35 3F28 2F34

5F73

1FD3
2FDD
2FDC

3F64

2F9A

2E37

3E20

6FD3
6FD2

9C03

9C02

1T01

1E38

6EC1

2F98

9E15

1E09

6E20

1E43

6E16

3E41

3FC3

3FC4

2F81

6E15

1ECB

3FC5

3FC6

9FC5
2FC2

3FC1

2FC1

2FC6

2FC3

6FC7
6FC5
6FC3
6FC4
6FC2
6FC1
6FC6
6FC8

1P05

2FC8

1FC1

1P02

9FC4

1FC3 1FC4 1FC2

1FC5

1P03

9FC6
2FC5

1E78

2FC7
3FC2

1FC6
1E76

1E07

1E75

1E77

2FC4

2ECC

1E79

1P04

3FC7

2E25

3E56

2E20

2E23

2E26

3E58

9FC3

1N00

3F623F63

2F97

3E57

5EC2

3E38

6E17

2ECM

3ECM

IEE3

1E44
9EC3

1329

IE35

2F60

3E54

2EE5

2ECP

2EC1 7EC1

IE36

2ECN

3E55

3ECF

3E36

2E67

3ECN IE42

1F52

6E18

IE34

IEE6
2EE2

7EE1
2EE1

3ECP

3EC5

2E21

3EE2

9E17 3E89
9E50

3EC3

9E57

6E51

6E46

IEE4
IEE5

4E24

4E21
3EE3

4E20

2EE7

2EE4

2C88

2EE0

3C96

2C89

3EE0

3C97

2C81

2EE3

3EE1

3C95

5E06

3C94

1E42

1E29

3E27

IC74

2E22

2C90

2C86

2C87

IE11

1328

2F99

2ECU

6C05
2C91

1E03 1E04

1E08

2E05

5E01

1E87

1E88

2E62

2E60

6E47

2EE6

3C79

3E26

6C03
2C82

2E07 5E02
3E28

3E98

5E08

3C77

IC75

2C78

3ECG

3E25 3E22
2E57 2E56

3C78

1E39

2E66

2C93

2C80

1E37

1E28

3C74

6C02
3C76

3E40

2C76

3E34 3E68
3E35
3E72
2E63

7EE0

IE07

2G77

3C75

3FDG

1FD2

IE10

2G75

2C77

1F51

2F86
3F75

3E21

2E38

6E19

2E35

2E36

2E54

3F65

2F9B

IE09

9F71

2E27

5F72

4E23

4E22

6E40

2F88

1X06

3E87
3E88
9E52 9E29

2E40

6E38

3E96
9E13

2E72

9E11

2E55

2E71

7E10

2G76

2E39

3E33

2G27

3E30

3G38

2G78

6E06

1E70

3E51

2G25

1E32

3E97

9E04

3E65

3E66

2F93

2E53
2E52

2G24

2G26

3E67

3E69

3E70

2E49

2E48

3E64

9E42

3E71

9E43

2F9C

2G79

1M21
1M19

IF86

2F91
3F72

1F25

9F04

2G7A

1X02

1P08

2F9D

1E06

1E18

1E55

5F70

1E85
2F32

1E01

5D05

3F31

7F70

IF89

1E23

1E19

6F72 3F78

9F05 9F06

1E12

1F75

9F00 9F01

9E22

4E01

9E21

4E03

4E04 2E14

1F24

IF61

2F92 2F94
2F90 3F71

9E18

9E05
4E02

6E26

1E86

1E53

5E74

2E84 3E77 3E76

6E22

1E00

2E83

1E71

3E31

7F58

2F58
3F58

2S4M

3F59
3F60

3S83

BS13

9E20
9E24 3E32

4E05 2E18

1P09

2F40

2S77
2S78

1F10

3S12

3S6H

3S42

2S2Z
2S2Y

2S30

2S33

2S2W
2S2V

IS13

2S32

3E17

2S7M

3S13

2S41

5D02 5D01

2S31

4S14

7S08

3S6J
3S53

2S2S

3S26

2D09

2S34

3S2M

3S3G

2S2R
2S2T

3S3M

3S43
3S44

3S3U

9S06

3S3H

DBS8

1S02

5T51

6T51
6T53

3B14

2D06

2D12 2D11

DS50

5T52

3S3F

BS15

2S4G

3B04

2B45

2D07

2S4F

3B15

3S27

2D10

IF62

3B05

2D24

2D17

2D23

7B03

7D10

5D04

1G51

IS14

3B24

3S00

1D52

2D08

1735 1D38

1D50

3S6K

3S4B

3S81
3S80
3S52
3S54
3S50

1X01

1E05

LAYOUT
SSB TV550 2K11 4DDR EU

2011-01-27

3139 123 6495


19100_800_110127.eps
110217

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 150

Overview bottom side

2G17

IUM0

2G16

2G14

2G12

FU61

FU66

FU63

FU75

IU03
IU49

7U06
3UB6

IU26

3U13

3F41

AF72
FF56
IF53

C000

2UB3

3UB4

7U41

3S39

3U02

CU02

CU01
2UU0
3UU2

FC99

7UU2

FG1C

FG33

9G0K
3D01

2D21

2E10

3E24

2G94
2G95

3D06

3D16

3D10
ID07

ID05

6E01

9E27

FE72

IEC1

2G91

FE70

2E15

FEA1

3FE7

2FF3

3FG4

3FG2

2FE6

DFE8

2E88

9G0G

FG20

FG21

3G34

6E03

FE73

4E06

9E28 3E07 2E06


IE23 2E04
9E25

IE71
FE54
IE51

2E91

6E09

IE14

9E07

9E10

2E75

6E29

IE72

9E26

FG1Y

FG1Z

FG2E

FG2F

IE26
IE22

IE64

FE50

3G30
IE63

IE38
FE49

3G36

IE29

FG2L

3G2Z

IE31

IE73

2FE4

IE32

FG2R

3G37
FG2G

3G2Y

FG35
3G2W

DFE7

FG04
IE33

BFE2

3G32

FG34

FG2H

3G35

IE39

DFE6
FE31
FC89

2FG6
IF17

2FG4

FE34

FE33
FE29

IF18
FE42

FC87

DFF2

2FH3

3E29

5FA4

2FF9

FE27

2FA4

IF69

2FG1

2FH4

2FF1

2FA3

5E03 5E04

3E39

FC88

FC90

IEE8

FE02

FFAF

FE30

FECZ

FEC3

2ECX

9E58

IE76

2ECY
FECR

3ECJ

IE43

2EC3
FECY

5EC3

2EC7

FE53

FEC7

3ECL

FE46
FE44

FE48

IE44
IE45

2ECW

FE01

2ECQ

2EC2

2FA2

FE47
FE45

FE52

3ECH

FE03

FECB
FFA2

FE59

2C79

FC91

FE61
FC92
IE77

FE60
FE51

3E90 9E19
9E54

IE74

IE75

2E68

FFB5

6E52

IEE0

7FA3

FE28

IC73
IEE7

5FA3

3E99

2E58 2E59
2E08

2FF4

3FE8

3FE9

2FG0

2FF2

2FF7

3E95

FE32

2FF8
IF68

FF61

FF63

7FE3

FF62

2FE3

IF67

DFF1

IF49
5FE5
FF03

2E09

2FE8
FF81

5FE8

2F84 3F76

FG24

FG22

3G33

FG2K

IE48

FE71

IE06

7FE0

7E09

FE82

3FG7

BFE3

3E43

3E62
FE84

IE52

2E44

IE16

6E32

9E16

2FF5
2FF0

2FH7

2FH2

FG29

FG25

FG2M
IF29

DFE9

FFDB

FG28

FG23

3G31

2FH6

2F59

2D22

2D26

FG2B
ID08

FG26

2FG8

FF74

FG2A

FG27

3E73

2FH5

2FG7

FF76

FG1R

FG2D

ID06

2E24

2FE0

5FE3

2FG9

5FE9

FG1T

FG1S

IF82

3E44

5FE0

IF65

FFDA

3D14

IF27

3FG6

2FG3

IF63

IF48

5FE7

IE50

FG1U

FG2C

5FG0

5FG2
2FG2

5FE4
FF00

FFDC

FG1W

FG1V

FG2P

6E43

2F79
3F77
3FE5

2FE5

IF28

FF82

2F61

2D16
CD10

2G9D

2F75
IF74

3F80
3F81

1FE0

IF66

FF64

3FBF

7D03

3D09
2B36

2E90

6E23
FE74

7E01

3E37

FEA0
9E23

3E74

6E07

9E51

BEC3

2E87

BEC5
2E86

9E53

3E79

2E85

6E28

9E55

IE08

2E80
3E75
9E08

3EA7 2E01

IEC2
FE75

3E53
IE49

IF64

2FF6

FFC9

3D02

2B12

2B11

2B07

2B06
2S42
FE81

3E78

9E09

2E12

2E76

9E06

FE43

2E99 2E98 3E19

3E48

FE80

IEC0

IE68

2E79

5E73

5E76

IE17
IE92

6E30

3EB6

IE96

IE55

FE58

AF70

FFB1

CU04
CU03
2D31

3B21
2B26

2B14

2B16

2S24

IS50
2S39

2S38

2S3A

3S51

3S34
FE83

FE85
FE56
IF76

6E44

2F66

5F66

IF78

IF14

IF41

FFB6

3U80

2B39

2B23

2B19

3B20

3S07

3S6Q

2S4R

2S4Q

C001

2S3E

2S3F
2S3D

2S3B

2S2H

7E05

2E74

3E18

9E01

3EA1
IE60

IE91

3E45

2E97

IE59

IE13

FG2N

IF12

2F63
2F64

2FH8

FF65

2E81
5E80

IE61

3EB1

9E12

9E14

2EB3

IF15

2F25
3F30

FF66

2S2G

3S1D
IE89

FE57

3F35

9F03
9F02

AF71

2F28

IF33

3S49

IE53
2EB1

IF73

7F75

IF10

IF11
IF13

IF34

IF44

IE15

2EA4

2EA5
IE18
IE90

2F96

IE70

2F78
2F74

FF75

2F30

FF01

IF30
IF32

FD06

3S0Z

IF80

IF59

2F71

IF77

2F85
9F25
9F26

2D14

2D13

ID10

IF81

FF71

IF39

FF36

2D01

5D03

FD14

3F79

FF57

IF75

IF31

FD05
ID32

ID09

ID31

IF54

IF90

FF37

2B41

IS1D

3EA2

IF40

ID28

2B00

3B03

5F71

IF58

3F52

IF36

IF42

2F31

ID29

IS12

2F49

3F34

2F27
2F26

IF43

ID19

FS57

3EB3

IF72
IF37

ID37

FS52

7E06

IF52

ID15

ID30

ID18

2B01

3S38

FS53

2F95

3E06

IF35

3S36

IS0R

3B28

2D27

7F52

IF50

IF79

2F52

3F32

IF45

FF33

IS1H

7D15

3FE6

FF32

IS11

5F74

2F73 2F80
2F72 2F82
2F77
2F76 AF73

FF55
FF29

3S5E

IS1P
3S3P

FF30

2F65
3F82

9F30
9F29

FF39

2F62
2F70

3F43
FF38

FF42

7S05
IS02

5F76

FD08

2D29

FD09

IS07

IS1Q
IF16

FD01

ID27

IS03

FS03

FF46

FF41

2UB4

FG0H
IS1J

IS0V

2D28

FD02

3S47

IF47

2S3J

3S16 3S17

IE54

3F40

3S20

2S68

2S3G

2S3H

3S09

2S2L

3S10

3S32

IE67

2S2J

FS50

3S37

IS06

IE05

FF48

IS1N

ID33

2B09

FD03

3S72

2S16
IS5C

2S8A

9S24

IS3E

3B01

2B40

IS1S

3S5B

3S5T

IS5G
IS3F

IS2V

2D02
ID14

FS08

IS1M
IS4V

IS44

FF45

3S6P

2S60
5S93

2S23
2S45

IS5J

3S08

2S40

2S19

IS2Z

3F45

FF49

2B27
2B29

3S06
2S5P

2S4S

2S64

2S5J
5S89
5S87
5S81
5S90

2S53
3S75

IS19

FD07

ID11

2B13

2S36

IS5H

3S46
3S2S

FS49

FS44

IS1A

2S3C

IS3D

2B17
FS02

3S22

IS1B

ID12

2B37

2B15

IS4W

2S18

2S14

FS11

2S85
2S86
2S84

2S76
2S75

3S5S

IS42

2S6G

IS5E

5S84

2S13

IS3B

3S2L

3S1H

3S05

3S25

IS5D

3S1G

2S22

3S18

2S3M

IS1K

3D15

2B10
3S0V

2S46

IS20

IS1E

FF50

FF44

IS1G

3S19

3S11

3S6M

2S3Q

2S52

2S37

2S51

3S76

3S5V

7S09

2S6E
2S6D

2S20

2S50

2S15

3S40

2S10

FS10

ID35

7D11
ID34

2S65

IS5F

FS45

2B18

3B22

2SHW

IS3L

3B06

3S30

2S6N

2S4U
DS52

FG31

2G9C

2B20

2S26

2S67
2S63

5S88

2S5H

2S6P
2S6F
5S92

2S5A

2S6M

2S59

2S55

2S11

2S4V

2S6A

2S28

2S58

2S6K

2S6H

2S5C

2S5K
5S95

IS4Z

FG32

3S33

3S6L

IS2U

2S21

5S83

FG30

2B24

2D03

2S4Y

2S5G

FS51

3F42

2S4W

2S2K

2S4K

3S2H

FS0Z

3S55

5S94

2S43

9S0D

IF51
FF04

IT51

IS1L

3F44

3S0W

3S64
3S45

IS16

3S1P

IT67

3T53

FF43

2S6B

9S09

3S2K

3S41

9S0E

IT54

IS05

FC95

2S3K

IT53

6T50

3T62

IT69

2S3L

2T58

3T60
3T52

2T37

2T60

3T55

IT61

2T53

IT60

IT62

3T58
2T54

IT57

2S5B
IS01

2S27

2S4T

7S20

7T51

IT50

5S80

2S6C

3S2V

IT68

2S6L

2S57

IS3Q

IS10
FS64

3S1F

3T50

IS3S

IS04

9R04

3T27

3T61

FF47

5S82

3S82

2S5D

3S1R

3S1U

3S1T

3S1S

IT28

3T54

2T51

IT65

2T38

5S85

5S04

2R22

2T61

2T52

3T51

IT59

9R03

2T59

6T54 9T52

IT58

IT64

3T59
2T62

3S1X

2R15

2R26

2R25

2R21

3T56
9T50
9T51
IT63

IT52

3S69

3S6V

2S62

IS3K

2S5M

3S1E
IS58

3T57

IT55

3S6W

3F06

IR04

2R09

IS25
3S1W

2S56

3S57
3S56

3S2F

2S4Z

2R23

3S2G
3S6A

IR03
3R01

2R14

IT66

IT56

IS26

3S5Y

2R52

2R17

3S6F
3S6D

2R51

3R00

FR01

3S15

3S60
3S5Z

2R08

IR00

2B22

2S17

3S1V

3S6E

IF88
IS40

5R00

2S66
2S61

2S25

3S6G
2R07

FG1F

FG1D

2G93

FS01

2S4N

2R00

FG1E

2B42 3B27
2B38

3S5W

9S08

2B25

2S89 3S58

IS00

2B03

3S6C

IF87

3S61

FG1G

2G92

2B02

3S6B

9C00

2B31

2B21

9S96

9S97

3S67
9S12

2R13

2R16

2B35

2B33

9S95

9S94

IS08

9S11
3S65

2B04

9C01

FG1L

FG1J

FG11

FG1H
2B28

3GE3
3S68

FG1K

2S29

3F19

FG1M

2G9F

2S12

3F20

IF22

FG12

FG1N

3B09

2B08

3GA3
3S66
9S10
9S13

3F22

3R13

2R06

2R05

2R03

2R04

2R12

2R49

FG14

FG13

2B34

FB00

2GA1

IS09

2R11

FR07

2R02

2R24

2UB2

5GA1
2GE0
5GA0
2GA0

2B32

FGA0

FG16

FG15

3GE4

7S01

2F20

2R50

IR01

2UB1

2GA3

2GA5

7GE0

2GA6

3GA4

3F21
2R10

IF23

3F12

FG18

FG17

2B43

2B30

3F23
IF21

3R11

2F21

3GE2

3F24

2R48

FG1A

FG19

FS31

2S2E

IR06

CUA0

FGA3

FGA6

7F02

2F03

9GE1

FG1Q

FG1B

2R01

2R19

FG2J

FGA1

IGE0

FF31

2R18

FUU0

FG1P

IS15

9R00

IR07

3UU0

FGA5

7GE1

IR08

7UU3

FUU1

3GE0

IS17

3R10

IUU3

2G9E

3GE1

2GA2

3F07

FR02

7UU1

3UU3
IUU4

FGA4

IGE1

FR03

IUU2

IUU5

IUU0

9GE2

FR06

IUD5

FUA3

IUU1

IF07

FR04

FUD2

2UE5

9GA1

FR05

IC78

2U14

FU03

FGA2

3F05

3R02

2UB6

IUB1

9GE0

2R53

FC97

2UU1

IUB6

7UA5

3F03

2U29

IU40

2UB0

5UA0
3U41

7UA3

IU44

3U15

7U42

FC98
3U21
IU19
2U10

FUA4

2UB7

2UB5

3F02

3F01

2F02

7F01

3F10

IF05

FR00

7U48

3U20
IU01

IUB2

3U12

7UA6

7UD2

IU47
IU43

9U41

IUB3

7U43

3U59

FUD3

IU21

CU05

7UC0

IUB4
IUB5

3U16

IU30

6UD1

3U70

IU45

3U69

IF03

6R00

3UB1

2U71

FU00

2U13 2U12

2UB8
7UA7

3U74

7F00

2F00

3F11

2F06

7F05

IF02

IF01

IR02

7UA4

3UB2
3UA0
9U42
3U75

3U53

IF08

IR05

IUA6

3UB7

3U68

3R07

3U03

IU29

IF04

3F04

FC96

2U04

IU64

IU41

3U25

IF06

FU06

IU14
IU25

IU02

3U83

3UB5
IUS7

FU05

2U05

IU09

3U61

3UB0

IUA5

IU07

IU12

FU02

IU50

3U82

2UA4

3F08

2R47

3UB3

7UA0

IF55

3F09

7U03

IU10
FU04

2U00

FU07

2F04

7F03

7F04

IFD1
3FD6

9FD1

6FD1

3FD7

9FD5

3F53

2FD1
IFD3

FUA0

IU06
2U02

IU61

IU52

3U17

IU13

IUS8
IUB0

3U18

3U14

3U63

FS2Y

3U19
2U08

3U09

IU20

IU04

IU08

FC63

2B05

FF58

3F54
3F66

9FD2

9CH0

IFD5

7F53
3F67

3FD1

7F54

IF57

3FD2

3F69

2F53

IF56

IFD2

7FD1

IFD4

3F68

3FD3

3FD4

2F05

FC62

3U10
2U07

3U22

IU16
IU11

3U60

FU76

2U03

IU24

2U21

FU72

IUD7

FS2W

FU62

3U27

FU73

IU62

FU55

CU00

3UU1

FC86

2U01

IU05

IU63
IU28

FU53

IU55

FU08

FU09
3U01

3U05

3U73

IUD6

IU48

3U62

IU27

FU52

IU56

3U00

2U55

FC85

FU51

FU67

2U06
FU01
IU22

2U22

IUD3

IT06

IT16

FU60

3U72

6U40

2U57

IU51

FU68

7U00

FU59

FU74
FU57

IUS0

3U08

3T20

FU56

FU58

3U28

2T31
IT15

FU54

7U40

IT07

FU50

FC61
FC64

3U04

3T24

FU49

IT05

1U40

3T31

2G10

2G15

3U11

IT14

3T07

3T14
3T17
3T04

3T05

2T28

FC79

FU48

2T21

2T29

3T12

FC70
FC72

IT21

IT17

FUM0

FC71

FC78

3T08

6T05

2T27

IT13

2G11

2T26

2T16

2T15

IT25

FT05

3T29

2T23
2T24

IT08

FC73

2G19
FC76
FC82

IT04

2T13

IT26
IT27

2T40

IT32

FT00

7T04

3T06

2T25

3T23

IT29

2G18
FC77

IT23
IT22

FC74

FC75

FC84

FC83

IT12

2T20

IT10

2T35

IT11

3T13
2T34
3T09 3T15
3T19 3T16
3T18

2T41

2T07

IT30

FT04

3T10

IT09

2T43

IT03

6T02

IT24

6T00

2T10 2T36

FT06

6T04

FT08

FT07

3T11

3T03
5T02

3T00 3T21

7T01

2T09

2T39
2T08

3T02

6T01

2T04

IT18

2T05

3T01
IT02

IT20

2T06

2T30

IT19

2T03

3T25
3T28
3T26
2T42

2T02

FC81

IT00

IT01

FC93

FEE0

3ECK

FC94
IE12

IEE1
FE41

9EC2

FFC2

5EC0
IE65

IE66
FEC0

3ECU

FE36

2EC6

FFC7
2EC8

9FC1

9FC2

FFC5
FFB4

FFC4

2EC0

FFC3

FFB3

2ECV

IEE2

FFC1
FFC6

IEC7

FECA

FECW

FFC8

IEC6

IEC5

9EC0

3ECE

FECJ

7EC0 7E02 3E23

FE35
FEC2

3ECD

FFB2

IEC4

FECE

FEC4
FEC5
FEC1

FECM

3ECA
FECF

3EC1

FECD
FEC6

FECK
FECL

FECP

FECC

FECN

FECG

LAYOUT
SSB TV550 2K11 4DDR EU

2011-01-27

3139 123 6495


19100_801_110127.eps
110127

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 151

10-11 B01 393912364955


Common Interface

Common Interface

B01A

+3V3
2F00

TRANSPORT STREAM FROM CAM

19
CA-MOCLK
CA-MOVAL
CA-MOSTRT

3F03-1

IF02

CA-DATAENn

3
4
5
6
7
8
9

8
100R

IF03

1
2

18

MOCLK

17
16
15
14
13
12
11

MOVAL
MOSTRT

CA-DATADIR

CA-ADDENn
MOCLK
MOVAL

10

MOSTRT

MDO0
+3V3
2F02

19

MDO1
RES
MDO2

100n

20

7F01
74LVC245A
1

MDO3

3EN1
3EN2
G3

MDO4

IF05
CA-MDO0

3F04-1 1

8 100R

2
IF06

CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7

3F04-3 3
3F05-1 1
3F05-3 3

3F04-2
6 100R
3F04-4
8 100R
3F05-2
6 100R
3F05-4

7 100R

5 100R

7 100R

5 100R

3
4
5
6
7
8
9

1
2

18

MDO0

17
16
15
14
13
12
11

MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7

MDO5
MDO6
MDO7

CA-RDY

10

IF07

CA-WAITn
+3V3

CA-INPACKn
2F03

15-BIT ADDRESS
3EN1
3EN2
G3

XIO-A01
XIO-A02
XIO-A03
XIO-A04
XIO-A05
XIO-A06
XIO-A07

17
16
15
14
13
12
11

CA-WP

1
2

CA-VS1n

1
19

CA-ADDENn

CA-A00

3
4
5
6
7
8
9

CA-A01
CA-A02
CA-A03
CA-A04
CA-A05
CA-A06
CA-A07

10

XIO-A00

18

RES

100n

20

7F02
74LVC245A

XIO-A09
XIO-A10
XIO-A11
XIO-A12
XIO-A13
XIO-A14

17
16
15
14
13
12
11

20
1
2

1
19

CA-ADDENn

CA-A08

3
4
5
6
7
8
9

CA-A09
CA-A10
CA-A11
CA-A12
CA-A13
CA-A14

10

18

RES

100n

3EN1
3EN2
G3
XIO-A08

+3V3
2F05

8-BIT DATA
3EN1
3EN2
G3
18

XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07

17
16
15
14
13
12
11

1
2

CA-DATADIR

19

CA-DATAENn

CA-D00

3
4
5
6
7
8
9

CA-D01
CA-D02
CA-D03
CA-D04
CA-D05
CA-D06
CA-D07

10

XIO-D00

RES

100n

20

7F04
74LVC245A

+3V3
2F06

CONTROL
7F05
74LVC245A

18

XIO-D09
XIO-D08
XIO-OEn
XIO-WEn
XIO-D14
XIO-D15
CA-WAITn

17
16
15
14
13
12
11

RES

100n

3EN1
3EN2
G3
XIO-D11

3F07-4

5
10K
7
10K
3F07-3
3
6
10K
3F07-1
1
8
10K

3F07-2

+3V3

3F08-1

8
10K
7
10K
3F08-3
3
6
10K
3F08-4
4
5
10K
2

3F08-2

1 3F09-1 8
10K
2 3F09-2 7
10K
3F09-3
3
6
10K
3F09-4
4
5
10K
1

IF04

3F10-1

8
10K
3F10-2
2
7
10K
3F10-3
3
6
10K
3F10-4
4
5
10K
3F12
10K
2 3F11-2 7
10K
3 3F11-3 6
10K
4 3F11-4 5
10K
8 3F11-1 1
10K

+3V3

IF08

+5VCA

+3V3

1P00

+5VCA
2F04

7F03
74LVC245A

B01A
100K

CA-D03
CA-D04
CA-D05
CA-D06
CA-D07
CA-CE1n
CA-A10
CA-OEn
CA-A11
CA-A09
CA-A08
CA-A13
CA-A14
CA-WEn
CA-RDY

+3V3

20

22u 16V

RES 2F01

+T 0R3

1
7

100R

3EN1
3EN2
G3

100R
3F03-2 2

+5VCA

CA-CD2n

1
2

1
19

CA-ADDENn

CA-REGn

3
4
5
6
7
8
9

CA-MIVAL
CA-MICLK
CA-A12
CA-A07
CA-A06
CA-A05
CA-A04
CA-A03
CA-A02
CA-A01
CA-A00
CA-D00
CA-D01
CA-D02
CA-WP

CA-CD1n
MDO3
MDO4
MDO5
MDO6
MDO7
CA-CE2n
CA-VS1n
CA-IORDn
CA-IOWRn
CA-MISTRT
CA-MDI0
CA-MDI1
CA-MDI2
CA-MDI3
+5VCA
CA-MDI4
CA-MDI5
CA-MDI6
CA-MDI7
MOCLK
CA-RST
CA-WAITn
CA-INPACKn
CA-REGn
MOVAL
MOSTRT
MDO0
MDO1
MDO2
CA-CD2n

CA-CE1n
CA-CE2n
CA-OEn
CA-WEn
CA-IORDn
CA-IOWRn
XIO-D10

10

3F01
+5V

IF01

3F02

CA-CD1n

100n

20

7F00
74LVC245A
1

3F06

CA-RST
RES

71
72

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70

1X07
REF EMC HOLE

1X04
EMC HOLE

1X08
REF EMC HOLE

1X01
REF EMC HOLE

92789-055LF

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_001_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 152

Flash

Flash

B01B

12

7F20
H27U4G8F2DTR-BC

37

100n

100n
2F21

2F20

+3V3

VCC

[FLASH]
4G 16
3F20-1 1

3F20-3 3

3F21-1 1

3F21-3 3

100R
3F20-2
100R
3F20-4
100R
3F21-2
100R
3F21-4

100R

100R

100R

100R

3F22-2
+3V3

XIO-OEn
XIO-WEn
NAND-WPn

3F23
3F22-4

7
100R
3F22-3 3
10K
3F22-1 1
5 100R

100R

100R

16
17
9
8
18
19
7

IF22
3F24

+3V3

NC

2K2

CLE
ALE
CE
RE
WE
WP
R
B

IF23
VSS
13

3F19

10K

NAND-RDY1n

0
1
2
3
IO
4
5
6
7

IF21

NAND-CE1n
NAND-CLE
NAND-ALE

29
30
31
32
41
42
43
44

36

XIO-D00
XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07

1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
25
26
27
28
33
34
35
38
39
40
45
46
47
48

+3V3

B01B

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_002_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 153

USB Hub

B01C

USB Hub

B01C
IF44

100n

2F25

+3V3

26
11

10K
IF32
+3V3
3F30
3 3F31-3 6
10K

IF41

12K IF40
IF39
4 3F31-4 5

31
30
27
35
22
24
25

100n

100n
2F33

100n
2F32

100n
2F31

100n
2F30

1u0
2F29

2F28

IF35

OSC1
USBDP_DN1|PRT_DIS_P1
USBDM_DN1|PRT_DIS_M1
BC_EN1|PWRTPWR1

13
2
1
12

3F37

9F25

USB-DP2

USB-DM

9F26

USB-DM2

RES 9F29

USB-DP3

RES 9F30

USB-DM3

10K

IF36

RESET
OSC2
USBDP_DN2|PRT_DIS_P2
USBDM_DN2|PRT_DIS_M2
SUSP_IND|LOCAL_PWR|NON_REM0BC_EN2|PWRTPWR2
TEST

DP
USBUP
DM
VBUS_DET

OSC3
USBDP_DN3|PRT_DIS_P3
USBDM_DN3|PRT_DIS_M3
BC_EN3|PWRTPWR3

RBIAS
SDA|SMBDATA|NON_REM1
SCL|SMBCLK|CFG_SEL0
HS_IND|CFG_SEL1

NC

17
4
3
16

USB-OC2n
USB-DP2
USB-DM2

+5V

IF37
19
7
6
18

USB-OC3n
USB-DP3
USB-DM3

8
9
20
21

GND_HS

3F34-4

FF33

+5V-USB2

100K
3 3F34-3 6

USB-OC2n

10K
VIA
38
39
40
41

IF31

28

XTALOUT

37

USB-DP
USB-DM

IF42

XTALIN|CLKIN

USB-DP

0R3

32

+3V3

+T

IF30

33

VDD_3V3

USB HUB

3F32

10p

2F35

IF33

RESET-USBn

36
23
15
5
10
29

CR PLL
FILT

IF34

3F31-2

34

1u0

100n
2F27

7F25
USB2513B-AEZG

24M

10p

3F35

10K
2F34

4
2

1F25

14

3F28

+3V3

1M0

2F26

IF43

3F36

+3V3

2
USB-OC3n

100K
3F34-2

100K

10K

3F34-1

SIDE USB

100K

1P08
USB-DM2
USB-DP2

+5V-USB2

FF36
FF37

FF32

1
2
3
4 IF45

5401

FF38
USB-DM3
USB-DP3

+5V

FF39

FF30
FF31

RES
1F24
1
2
3
4
5

7
6
502382-0570

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_003_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 154

SD Card

SD-Card

B01D

3F40

FF45

+3V3
22u 16V

+T
2F40

B01D

+3V3-SD

0R3

+3V3

3F41-4

IF47

47K

SDIO-DAT3
3

3F41-3

SDIO-DAT3

3F44-2

SDIO-CMD

FF47

100R

SDIO-CMD

3F43-3

1P09-1
6

FF48

100R

47K
3F45 RES

SDIO-CLK

3F44-1

+3V3-SD

SDIO-CLK

SDIO-DAT0

2 3F43-2 7

FF49

100R

10K
2 3F41-2 7

SDIO-DAT0

47K

1 3F41-1 8

1 3F42-1 8

47K

SDIO-DAT1
SDIO-DAT2

SDIO-DAT1
SDIO-DAT2

47K

FF41

100R

1 3F43-1 8

3 3F44-3 6

100R

FF42

3F42-2

FF46

SCDA7A0200

1P09-2
7

SDIO-CDn

SDIO-CDn

FF44

SDIO-WP

SDIO-WP

FF50

47K
3 3F42-3 6

14
16

FF43

100R

13
15

1
2
3
4
5
6
7
8
9

10
11
12
SCDA7A0200

47K

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_004_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 155

PNX85500 Control

PNX85500 Control

B01E

+3V3-STANDBY

IF50

512K
FLASH

BACKLIGHT-BOOST
7F53 RES
PDTA114EU

PNX-SPI-SDO
IF52

10K
RES

10K

3F67

3F66

IF53
1

PNX-SPI-CSBn
IF54

HOLD

+5V

PNX-SPI-CLK

PNX-SPI-WPn
+3V3-STANDBY
FF29

VSS

IF55

BOOST-PWM

IF61

47K

+3V3

+3V3

3F68 RES

PNX-SPI-SDI

3F52

7F52
M25P05-AVMN6

VCC
IF51

+3V3

100n
RES

100p

2F52

2F49

+3V3-STANDBY

10K

+3V3-STANDBY

7F54-1 RES
BC847BPN(COL) 6

7F54-2 RES
BC847BPN(COL)

SPI-PROG

IF56
4

IF57

2
1

FF04

IF62
SDM

FF58

1K0
RES

RES

3F69

10K

1u0

2F53

MAIN NVM

+3V3

RES

9CH0

10K

3F54

3F53

DEBUG ONLY
IF58

2F58 RES

IF59

1
2
3

0
1
2

WC

ADR
SDA

100R
FF62

FF63

SCL

3F63

100R

SCL

1
2
3

SDA
5

7
6
5

3F59

FF55

100R

FF56

3F60

SCL-UP-MIPS
SDA-UP-MIPS

100R

3F58

(8K 8)
EEPROM

RES
1F52

3F62

SDA-SSB

7F58

FF61

SCL-SSB

100n

10K

B01E

FF57

LEVEL

DEBUG / RS232 INTERFACE

TXD-UP
RXD-UP
RESET-STBYn
SPI-PROG

FF65

3F64

FF66

100R

SHIFTED

RES
1F51
FF64

3F65
100R

1
2
3
4
5

UP

FOR
DEBUG
USE ONLY

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_005_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 156

Tuner

Tuner

B01F

B01F

IF10
IF11

AF73

15p

2F65 RES
1p0

2F70 RES

2F73

220R

820R

AGC CONTROL

VAGC

IF16
330n
3F82 RES

10n

RES 5F76

10n

3F79-4

2F62

220R
IF80

5F74

2F79

2F72

9F03

9F02

IF78

*
AF72

3F79-1

2F82

PNX-IF-N
IF79

3F81

IF-

10n
IF14

2F64

IF15

IF+

10n

* For BR NIM Tuner Only

3K3

3F78

470n

5F70

TUN-IF-P

5F73

IF13

2F90

IF86

2F63

15p

220R

220R

TUN-IF-N

IF12

680n
2F66

10n

1K0
2F92

3F72

BA591

4K7

6F72

3F71

9F05

9F06

47n

+5V-TUN-PIN

5F66

3F80

IF72
2F85

100p
RES 2F95

IF76

10n

10n
+5V-TUN-PIN

2F75

3F77
4K7

FF82

OUTPUT2

IF74

2p2
2F77

INPUT2

RES
2F76

OUTPUT1

5F71

IF77

INPUT1

2F80

IF81

GND

10n
2F78

GND2

5
4

IF73

FF01

IF-AGC

100n

2F93

IF82

PNX-IF-AGC

IF-AGC

FF75

FF81

TUN-P6
TUN-P7

TUN-IF-N
TUN-IF-P

100p

2F61

* 9F04

O1
O2

2F74

VCC

IF75

X7251M
36M17

RES 2F96

100n

AF71
AF70
FF00

2F60

4n7
RES 2F59

RES 2F81

4n7

FF76

I
ISWI

RES 2F9D

RES 2F9C

RES 2F9B

RES 2F9A

RES 2F99

RES 2F98

RES 2F97

FF74

10n

GND1

6p8

6p8

6p8

6p8

6p8

6p8

6p8

1
2
3

2F91 RES

ATB2012
10n
IF89

47R

2F86

3F75

15p

47R

IF87

SCL-TUNER

IF88

SDA-TUNER

IF90

SELECT-SAW

2F94

TUN-P6

TUN-P7

7F70
PDTC114EU

10n

3F76

15p

RES

2F84

* For EU Hybrid Tuner Only


9F71
5F72 RES
+5V-TUN-PIN

+5V-TUN

* Remarks
Item No.
1T01
2F61
2F62
9F02
9F03
9F04
9F05
9F06
2F73
2F82
2F72
2F80
2F77
5F71
5F74

Component
Europe
Brazil
TH26X3
FA23X7
4u7
RES
5p6
10p
Used
RES
Used
RES
RES
Used
RES
Used
RES
Used
1p0
RES
1p0
RES
15p
12p
15p
12p
18p
22p
680n
560n
680n
820n

22u

30R
2F88

TUN-P1

+5V-TUN-PIN
7F75
UPC3221GV-E1

1F75

PNX-IF-P

2F71

9F01

9F00

NC

IF_OUT2

IF_OUT1

13

12

11

4MHZ_REF

14

10

B+_TUN

I2C_SDA

I2C_ADR

TUN

B+_LNA

RF_AGC
3

RF_IO

16

I2C_SCL

TUNER

15

FF71

1T01

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_006_110622.eps
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2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 157

Toshiba Supply

Toshiba supply

B01G

+1V2-BRA-DR1

+3V3

30R

10u

OUT

30R

IN

5FA4

100n

7FA3
LD1117DT12

2FA4

5FA3

+1V2-BRA-VDDC

FFAF

2FA3

100n

COM
2FA2

B01G

FFA2

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_007_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 158

HDMI

HDMI

B01H

HDMI CONNECTOR SIDE


1P05
DRX2+

DIN-5V

DRX2DRX1+
DRX1DRX0+
DRX0DRXC+
DRXCPCEC-HDMI
FFB1
FFB2
FFB3
FFB4
20
22

DRX-DDC-SCL
DRX-DDC-SDA

DRX-DDC-SCL
DRX-DDC-SDA

47K

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FFB5 21
23

1 3FBF-1 8

B01H

2 3FBF-2 7

DIN-5V

47K
DIN-5V
DRX-HOTPLUG

FFB6

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_008_110622.eps
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2011-Nov-04 back to

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 159

VGA

VGA

B01I

FFC1
CDS4C12GTA
12V

RES 6FC1

100p

1FC1

RES 2FC1

3FC5

CDS4C12GTA
12V

RES 6FC2

100p

1FC2

G-VGA

18R

100p

RES 6FC3

FFC4

1FC3

RES 2FC3

FFC3

CDS4C12GTA
12V

3FC7

9FC5

H-SYNC-VGA

9FC6

V-SYNC-VGA

4K7

3FC3

CDS4C12GTA
12V

RES 6FC4

47p

FFC6
1216-02D-15L-2EC

B-VGA

18R

FFC5

1FC4

CDS4C12GTA
12V

RES 6FC6

47p

2FC6

10K

RES
3FC2

FFC9

RES 6FC7

47p

2FC7

10K

4K7

3FC4

CDS4C12GTA
12V

RES 6FC5

47p

FFC8

CDS4C12GTA
12V

RES
3FC1

1FC5

2FC5

FFC7

9FC1

VGA-SDA-EDID-HDMI

9FC2

VGA-SDA-EDID

RES

9FC3

VGA-SCL-EDID-HDMI

9FC4
RES

VGA-SCL-EDID

RES 6FC8

1FC6

47p

+5V-VGA
CDS4C12GTA
12V

17

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

2FC4

VGA
CONNECTOR

3FC6

RES 2FC2

1E05

R-VGA

18R

FFC2

2FC8

B01I

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_009_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 160

Temp sensor & headphone

Temp sensor & headphone

B01J

SCL

A2

1K0

3FD2

9FD2 RES

9FD1 RES

100n

IFD3
IFD5

RES

A1

9FD5

+VS

SDA

1K0

2FD1

1K0
IFD4

IFD1

A0

100R

100R

OS

1K0
3FD7

SCL-SSB

3FD4

3
1

3FD6

SDA-SSB

IFD2

7FD1
LM75BDP

GND

3FD3

LTST-C190KGKT

RES

RES
3FD1

+3V3

6FD1

RES
1329

1
2
3

502382-0370

1328
MSJ-035-12D-B-AG-PBT-BRF

FFDA

AMP1

2
3
1

22n

FFDB
22n
2FDD

CDS4C12GTA
12V
2FDC

RES

6FD3

CDS4C12GTA
12V
1FD3

1FD2

6FD2
RES

1K0

1K0
3FDG-1

3FDG-2

AMP2

B01J

FFDC

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_010_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 161

Tuner Brazil

B01K

Tuner Brazil

B01K

5FE0

IF63

IF64
+1V2-BRA-VDDC

+2V5-BRA

+3V3-BRA-FLT

1u0

100n
2FF1

100n
2FF0

100n
2FE5

100n
2FE4

2FE3

1u0

2FE0

30R

AGND
5FE3

IF65

IF66

+3V3-BRA-FLT

5FE4
+3V3-BRA
30R

1u0

100n
2FF6

100n
2FF5

100n
2FF4

100n
2FF3

2FF2

1u0

2FE6

30R

AGND
5FE5

IF67

IF68
+1V2-BRA-DR1
IF48

5FE7

+3V3-BRA

+3V3

1u0

100n
2FF9

100n
2FF8

2FF7

1u0

2FE8

30R

30R

5FE8

IF69

+2V5-BRA
7FE3
LD3985M25

5FE9

+5V
30R

18p

2FG3

18p

2FG2

25M4
4 2

1u0

2FG0

1FE0

100n
2FG1

30R
1

IN

OUT

INH

BP

FF03

+2V5-BRA

10n
2FG6

2FG7
AGND

2FG9

100n
2FG8

10n

100n

IF17
IF18

30
29

BFE2

28
27

BFE3

100n
2FH6

100n

24
25

2FH7

100n

26

AGND

39

AGND

0
XSEL
1

PBVAL
RERR
RLOCK

P
ADI_AI
N

RSEORF

P
ADQ_AI
N

SBYTE
SLOCK

P
AD_VREF
N

SRCK

AD_VREF

SRDT
STSFLG1

DTCLK

21
58
53
54
55

33R

TS-BR-VALID

9F27-1

TS-FE-VALID

3FG6-3

33R

TS-BR-SOP

9F27-2

TS-FE-SOP

TS-FE-CLOCK

TS-FE-DATA

DFE8

DFE9
5FG0
3FG7

60

3FG6-2

11
SCL-SSB
SDA-SSB

3FE8

100R
3FE9

IF49
100R

45
46

AGCI
0
SLADRS
1

CKI
SCL
SDA

AGND

PLLVSS

TN
VSS

SCL
SDA

33R

TS-BR-CLOCK

33R TS-BR-DATA

9F28
4

9F27-4

30R
5FG2

DFF1
30R

3FE5
18K

10
51

1u0

DFE7

DFF2

IF28
IF-AGC

AGND

42
6
5
12
14

3FG2-1

RESET-SYSTEMn
10K

3FG2-2
10K

3FG4-2
4K7

3FG4-1
4K7

+3V3-BRA-FLT

4
15
33
37
44
47
50
57
62

10K IF29

SYRSTN

17

3FE7

STSFLG0

0
TSMD
1

AD_DVSS

1
41

10K

31

3FE6

AGCCNTR

S_INFO

AD_AVSS

AGCCNTI

DTMB

23

+3V3-BRA-FLT

10n

DFE6

61

38

3FG6-4

IF27
40

AGND

1n5

59
52

2FH4

* To be drawn near PNX85500

2FH3

2FH5

1u0

43
FIL

2FH2

VDDS

DR2VDD

34
48

16
36
56
63

22

13
35
49
64

DR1VDD

VDDC

10n

2FG4

IF+
IF-

2FH8

3
2

PLLVDD

19
18

32

AGND

AD_AVDD

AGND

AD_DVDD

AGND

20

COM
7FE0
TC90517FG

AGND

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_011_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 162

10-12 B02 393912364955


NANDflash - conditional access

PNX85500: NANDflash - conditional access

B02A

7S00-5
PNX85500

D22
ALE
C21
NAND
CLE

XIO-A00
XIO-A01
XIO-A02
XIO-A03
XIO-A04
XIO-A05
XIO-A06
XIO-A07
XIO-A08
XIO-A09
XIO-A10
XIO-A11
XIO-A12
XIO-A13
XIO-A14
XIO-A15

J25
J26
H21
H22
H23
H24
H25
H26
G21
G22
G23
G24
G25
G26
F22
F23

IS25

00
01
02
03
04
05
06
07
XIO_A
08
09
10
11
12
13
14
15

XIO-D00
XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07
XIO-D08
XIO-D09
XIO-D10
XIO-D11

XIO

B22
OE_
C22
WE_

XIO-OEn
XIO-WEn

CLK_BURST
CE1_
CE2_
NAND RDY2
RDY1
WP_

INPACK
XIO-D14
XIO-D15

IS26

INPACK

3S15
10K

+3V3

B21
E21
D21
A20
F21
A21

NAND-CE1n

NAND-RDY1n
NAND-WPn

9S08

10K
RES

NAND-ALE
NAND-CLE

D25
D26
C24
D23
C23
B23
A22
E22
F24
F25
F26
E23
E24
E25
E26
D24

00
01
02
03
04
05
06
07
XIO_D
08
09
10
11
12
13
14
15

3S1V

FLASH

10K

3S1W

+3V3

IS00

7S00-11
PNX85500
3S01-1 8
33R
3S01-3 6

CA-MDI0
CA-MDI1
CA-MDI2
CA-MDI3
CA-MDI4
CA-MDI5
CA-MDI6
CA-MDI7

7 3S01-2 2
3 33R
33R 5 3S02-4 4
33R
7 3S02-2 2
33R 8 3S02-1 1
6
3 33R
3S02-3
33R 5 3S01-4 4
33R

P21
P22
P23
P24
P25
P26
N21
N22

CA-ADDENn

J22

CA-DATADIR

K25

CA-DATAENn

K26
3S03

CA-MICLK

N23
10R
L25

CA-MOCLK

N24
3S31
CA-MIVAL
33R

N25

CA-MOSTRT

L22

CA-MOVAL

L23
J21

CA-RDY

L24

CA-RST

L26
J23

RES
9S01

CA-MISTRT

J24
+3V3

VIDEO_STREAM

0
1
2
3
MDI
4
5
6
7

0
1
2
3
MDO
4
5
6
7

10K

3S1X

+3V3

N26
M21
M22
M23
M24
M25
M26
L21

CA-MDO0
CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7

ADD_EN
DATA_DIR

VS

K23
1
K24
2

CD

K21
1
K22
2

DATA_EN
I
MCLK
O

9S00

CA-VS1n
CA-MOCLK
CA-CD1n
CA-CD2n

CA

+3V3

MISTRT
MIVAL

TS-FE-DATA

3S1R

MOSTRT

TS-FE-CLOCK

3S1S

MOVAL

TS-FE-VALID

3S1T

OOB_EN

TS-FE-SOP

560R
560R

3S1U RES
RES

560R
560R

RDY
RST
VCCEN
VPPEN

T21
DATA
T23
ERR
T22
TNR_SER1 MICLK
R23
MIVAL
R22
SOP

TS-FE-DATA

TS-FE-DATA

3S23

TS-FE-CLOCK
TS-FE-VALID
TS-FE-SOP

TS-FE-CLOCK

3S24

TS-FE-VALID

3S28

TS-FE-SOP

470R
3S29 RES

TS-FE-ERR

470R
470R

100n

7S02
5

33R

RES 470R

3S04
2S09

B02A

1
4
2
3

SPB SSB TV550


2K11 4DDR EU

74LVC1G08GW

2011-04-27

2010-12-10

3139 123 6495


19104_012_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 163

SDRAM

PNX85500: SDRAM

B02B

F3
C2
F2
C3
B4
F1
C1
E1
F4
B2
E5
C5
A4
G5
B3
F5
U3
P2
U2
P3
N1
U1
P1
T1
V4
R5
U5
P5
N3
V3
R4
V5

180R 1%

3S07

180R 1%

3S22

DDR2-VREF-CTRL2

2S12

N
P

DQS0

N
P

DQS1

N
P

DQS2

N
P

DQS3

N
P

CASB
CKE
CSB
ODT
PCAL
RASB
WEB
1
VREF
2

N5
N4

DDR2-CLK_N
DDR2-CLK_P

3S30
10R

3S33
10R

E2
E3

DDR2-DQS0_N
DDR2-DQS0_P

D3
D4

DDR2-DQS1_N
DDR2-DQS1_P

R1
R2

DDR2-DQS2_N
DDR2-DQS2_P

T3
T4

DDR2-DQS3_N
DDR2-DQS3_P

K3
K4
L5
M4
M1
M5
H3

DDR2-CAS
DDR2-CKE
DDR2-CS
DDR2-ODT
DDR2-RAS
DDR2-WE

A2
V1

DDR2-CKE

3S6Q
10K

DDR2-ODT

3S6P
10K
RES

DDR2-VREF-CTRL2
DDR2-VREF-CTRL3

3S0V

FS01

DDR2-VREF-CTRL3

CLK

2S24

FS02

100u 2.0V

180R 1%

3S06

180R 1%

3S20

+1V8

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DQ
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

M0

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13
DDR2-A14

IS42
261R

DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D6
DDR2-D5
DDR2-D4
DDR2-D7
DDR2-D8
DDR2-D9
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D14
DDR2-D15
DDR2-D16
DDR2-D17
DDR2-D19
DDR2-D18
DDR2-D22
DDR2-D23
DDR2-D20
DDR2-D21
DDR2-D24
DDR2-D30
DDR2-D26
DDR2-D25
DDR2-D28
DDR2-D31
DDR2-D27
DDR2-D29

0
1
DM
2
3

J1
J3
K1
G4
L3
G3
L2
H5
L1
J5
J2
M3
J4
M2
K5

1%

D1
D5
R3
T5

0
1
2
3
4
5
6
7
A 8
9
10
11
12
13
14

100p

DDR2-DQM0
DDR2-DQM1
DDR2-DQM2
DDR2-DQM3

MEMORY

0
1 BA
2

100n
2S25

DDR2-BA2

H1
H2
G1

DDR2-BA0
DDR2-BA1

100n
2S17

7S00-8
PNX85500

100p
2S20

B02B

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_013_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 164

Digital video in

PNX85500: Digital video in

B02C

7S00-6
PNX85500
T25
T26

HDMIA-RX1+
HDMIA-RX1-

U25
P
RX1_A
U26
N

P
RX0_A
N

HDMIA-RX0+
HDMIA-RX0-

Y26
SCL
DDC_A
Y25
SDA
V25
P
RX2_A
T24
V26
N
HOT_PLUG_A

HDMIA-RXC+
HDMIA-RXC-

W25
P
RXC_A
W26
N

DDCA-SCL
DDCA-SDA
IS10

IS01

3S0W

W24

RREF

12K
10u

+3V3

HDMI_DV

HDMIA-RX2+
HDMIA-RX2-

RES
2S2E

B02C

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_014_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 165

Audio

B02D

PNX85500: Audio

B02D
3S0Z
+2V5-AUDIO

3S53-1

+24V-AUDIO-POWER
4R7

100R

220n

2S3J
2S2S

10u RES

1u0 RES

2S34

+AUDIO-L

IS1B

100u 4V

1u0

2S41

3S3F

AF5

100n

56R

DBS8

AE5

IS03

ADAC(2)

10

4
IS1S

3S3G-4

7S05-3
LM324 8

3S39

-AUDIO-R

100R
11

3S3G-2
2
7

ADAC(3)

33R
ADAC(4)

33R

3S36-3

10K

6
5

10K

3S3H

ADAC(5)

33R

AE1
1
AD8
AF2
VREF_AADC
2
AE3
I2S_OUT_SD 3
AC8
AF3
VCOM_AADC
4

IS1A

3S36-1
2S2G

3S3U

3S36-4
2S2H

47p

ADAC(6)

+24V-AUDIO-VDD

33R

SPDIF_OUT

2S3D

1u0

AD7
AE7
AF7
AD6
AE6
AF6

AD4
OSCLK
AD1
SCK
AD2
WS

I2S_OUT
AB9
POS
VR_AADC
AB8
NEG

ADAC(2)

SPDIF_IN1

1n0

2S2L

AF8
L
AIN5
AE8
R

1n0
2S38

3S10
100R

3S3G-3

1n0
2S39

1u0

IS07
3

ADAC(5)

7S05-1
LM324

AUDIO-OUT-L

2
11

3S37

3S6L

10K

22K
2S2K

+3V3

47p

+3V3-ARC

+24V-AUDIO-VDD
3S11

IS1L

1R0
5

ADAC(6)

IS06

7S05-2
LM324 7

AUDIO-OUT-R

14

1 3S18-1 8

IS1G

SPDIF-OUT

220R

3S18-2

100n

+3V3

220R

2S3K

3
+3V3

3S18-3

&

&
6

14

+3V3-ARC
7S09-3
74LVC00APW
9

&

8
+3V3

10

2S3L

180R

100n

3S6M

IS1K

2S3M

IS44
eHDMI+

100n

68R

3S25

IS1E

22K
2S2J

+3V3-ARC
7S09-4
74LVC00APW
12

14

SEL-HDMI-ARC

3S32

10K

47p

+3V3-ARC
7S09-2
74LVC00APW
4

3S34

7S09-1
74LVC00APW
1

IS1D

SPDIF-OUT-PNX

&
11

+3V3

13

SPDIF-OUT-PNX

11

10u
2S3G

10K

ADAC(1)
3

1n0
2S3A

AD9
L
AIN4
AC9
R

2S32

IS19

1
2
3
ADAC
4
5
6

14

7
10K

3S36-2

33R

3S17-2

33R

100n

IS1Q

3S38
100R

11

1 3S3G-1 8
IS1N

1u0

AC6
P
ADACR
AB6
N

AE9
L
AIN3
AF9
R

1u0
2

7S05-4
LM324 14

13

47p

1n0
2S3B

2S33

3S13-2
22K

8
10K

100n
2S3H

3S17-1

10u
2S3E

AUDIO-IN4-R

22K

2S3F

AD10
L
AIN2
AC10
R

1u0

3S13-1

AUDIO-IN4-L

IS02

+24V-AUDIO-VDD

1n0
2S3C

2S30

22K
1

4
12

ADAC(1)

10K

2S36

AUDIO
AE10
AC7
L
P
AIN1
ADACL
AF10
AB7
R
N

1u0

IS1P

+2V5

7S00-2
PNX85500

2S31

6
10K

4R7
2S42

1u0

5
10K

3
3S17-3

4S14

2S2Y

3S51

IS0V

3S17-4

COM

IS1M

2S3Q

22K

INH

IS13

1u0

3S13-3

BP

FS03

2S2Z

10K

AUDIO-IN3-R

IS0R

3S13-4

IN

100R

10K
3S16-4 5
4
10K

OUT

2S2V
1u0

3S16-3 3

5
IS12

3S53-4

7
10K

22K

AUDIO-IN3-L

FS08

2S2T

2
3S16-2

100R

220R

IS1J

2 3S12-2

1u0

3S19

AUDIO-IN1-R

100R
3S53-3

100n

22K

2S2W

2S2R

10u

1 3S16-1 8
10K

IS1H

3S12-1

7S08
LD3985M25

9S06
RES

1
AUDIO-IN1-L

+24V-AUDIO-VDD

+3V3

3S53-2

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_015_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 166

MIPS

PNX85500: MIPS

B02E

B02E
+3V3

7S00-3
PNX85500

CONTROL

RES 3S21
+3V3
10K
3S62

10K
10K

FS10 TXD2-MIPS
FS11 RXD2-MIPS
IS04

GPIO6

PNX-SPI-CS-BLn

+3V3

GPIO6
PNX-SPI-CS-BLn
BOOST-PWM
SELECT-SAW

+3V3

FS64

SELECT-SAW

5K6

3S64

3S55

10K

TRSTN
TMS
TCK
TDO
TDI

RESET_SYS
BL_PWM

10K
CLK_54_OUT

3S83
+3V3

RXD1-MIPS
3D-VS

10K
3S84
+3V3
10K

1
100R

B24
SDA
4
A23
SCL

R26
DN
R25
USB
IS4Z R24 DP
RREF

USB-DM
USB-DP

3S60

1
100R

2 3S5W

SDA-SET
SCL-SET

3S5Z

SDA-SSB
SCL-SSB

3S61

SDA-TUNER
SCL-TUNER

2
1
100R

AA25
AA24
AA23
AB26
AB25

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TDI-PNX85500

3S00

AE4

RES
1F10

3S69

SDA-UP-MIPS
SCL-UP-MIPS

3S6A

SDA-SET
SCL-SET

3S6C

SDA-SSB
SCL-SSB

3S6B

4K7

3S6D

2K2

3S6F

2K2

4K7

3S6E

SDA-TUNER
SCL-TUNER

4K7

4K7

2K2

3S6G

FS44

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDI-PNX85500

FS49
FS50
FS51
FS52

EJTAG-DETECTn

FS53
10 9

1
2
3
4
5
6
7
8

FOR FACTORY
USE ONLY

2K2
3S6K

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TDI-PNX85500

1
10K

8 3S6H-1
10K
3
6 3S6H-3
10K
2
10K

FS57

+3V3-STANDBY

+3V3

BM08B-SRSS-TBT

7 3S6H-2
5 3S6H-4
4
10K

RESET-SYSTEMn

33R

AD5

BACKLIGHT-PWM

AC5

IS14
+3V3

TXD1-MIPS

3S72
3S4A

BACKLIGHT-PWM

+3V3
IS40
PXCLK54

47R
100R
IS15

3D-VS-DISP

3S4B
100R
RES

RES

+3V3
2S89
100n

+3V3

10K

1
100R

1 3S5Y 2
100R

B25
SDA
3
A24
SCL

SDA-UP-MIPS
SCL-UP-MIPS

7S01
PCA9540B

VDD

SCL-SET

SCL

SDA-SET

SDA

INP
FIL

I2 C
-BUS
CTRL

SC0

SCL-DISP

SC1

SCL-BL

SD0

SDA-DISP

SD1

SDA-BL

SCL-DISP
SCL-BL
SDA-DISP
SDA-BL

3S65

1
4K7
1
4K7
3S67
2
1
4K7
3S68
2
1
4K7
2

3S66

VSS
6

+3V3
+3V3

3S80
3S81

9S09

2 3S57

10K

BOOST-PWM

+3V3

IS17

1
100R

3S58
1
2
100R

B26
SDA
2
A25
SCL

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_10
GPIO_11

3S27

3D-LR

DS52

10K
3S82

Y21
IS16 Y22
Y23
Y24
W21
W22
W23
V22
V23
U23

3S56

10K

+3V3

BOOTMODE
3D-LR
RXD1-MIPS
TXD1-MIPS
RXD2-MIPS
TXD2-MIPS

1
100R

3S6J

10K
3S40

C25
SDA
C26
SCL

3S26

BOOTMODE

RES 10K

IS05

3S45
+3V3

FS31

9S10
IS08
SCL-SET

SDA-SET

IS09

SCL-BL

9S11

FS2W

SCL-DISP

9S12

FS2Y

SDA-DISP

9S13

SDA-BL

7S00-4
PNX85500

ETHERNET

ETH-RXCLK

AA3

ETH-RXD(0)
ETH-RXD(1)
ETH-RXD(2)
ETH-RXD(3)

Y5
0
Y6
1
AB4
RXD ETH
2
AC1
3

ETH-RXDV
ETH-RXER
SDIO-DAT3
SDIO-CLK
SDIO-CMD
SDIO-DAT0
SDIO-DAT1
SDIO-DAT2
SDIO-CDn
SDIO-WP

IS50

RXCLK

TXCLK

0
1
AC2
TXD
RXDV
2
Y4
RXER
3
ETH
TXEN
W2
CC_DAT3
TXER
W1
CLK
COL
W6
CRS
CMD
W5
0
MDC
W4
SDIO
1 DAT
MDIO
W3
2
U6
SDCD
V6
SDWP

SPB SSB TV550


2K11 4DDR EU

AA2

ETH-TXCLK

AA1
AA4
AB1
AB2
AA5
AB3
AC3
Y2
Y3
Y1

ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)
ETH-TXD(3)
ETH-TXEN
ETH-TXER
ETH-COL
ETH-CRS
ETH-MDC
ETH-MDIO

2011-04-27

2010-12-10

3139 123 6495


19104_016_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 167

Video out - LVDS

B02F

PNX85500: Video out - LVDS

B02F

7S00-7
PNX85500
PX1APX1A+

A7
B7

PX1BPX1B+

C8
B8

PX1CLKPX1CLK+

9S90
9S91

N
A
P

LVDS

N
B
P

C10
N
CLK
B10
P

N
P

N
P

CLK

D7
E7

PX3APX3A+

E8
D8

PX3BPX3B+

E10
N
D10
P

9S94
9S95

PX3CLKPX3CLK+

N
P

D9
E9

PX3CPX3C+

A11
N
B11
D
P

D11
N
E11
P

PX3DPX3D+

PX1EPX1E+

C12
N
B12
E
P

E12
N
D12
P

PX3EPX3E+

PX2APX2A+

A14
N
B14
A
P

D14
N
E14
P

PX4APX4A+

PX2BPX2B+

C15
N
B15
B
P

E15
N
D15
P

PX4BPX4B+

CLK

E17
N
D17
P

D16
N
E16
P

PX4CPX4C+

D18
N
E18
P

PX4DPX4D+

E19
N
D19
P

PX4EPX4E+

PX1CPX1C+

A9
B9

PX1DPX1D+

PX2CLKPX2CLK+
PX2CPX2C+
PX2DPX2D+
PX2EPX2E+

9S92
9S93

N
C
P

LOUT1 LOUT3

C17
N
B17
CLK
P
A16
B16 N
C
P
A18
B18 N
D
P
C19
B19 N
E
P

LOUT2 LOUT4

9S96
9S97

PX4CLKPX4CLK+

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_017_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 168

Standby controller

PNX85500: Standby controller

B02G
POL

+1V1

B02G

2S13

100n

1u0
2S10

30R

RES
5S04

IS3B

10K

+3V3-STANDBY
3S1H
10K

3S1G

RXD-UP
TXD-UP

10K
3S2A

RXD-UP
TXD-UP
DETECT2

AE21
0
AF21
1
AA22
2
P3
AB22
3
AC22
4
AD22
5

RESET-SYSTEMn
AV2-BLK
AV1-BLK
KEYBOARD
LIGHT-SENSOR
AV1-STATUS
AV2-STATUS

AD23
0
AE26
1
P5
AE25
2
AE24
3

DETECT2

10K
RES
3S1K
10K
RES

RESET-SYSTEMn
3S1J
100K
RES

KEYBOARD
2S4E
100n

3S1L
10K

SPI-PROG

SPI-PROG
PNX-SPI-WPn

AF22
4
P6
AE22
5

AF26

AC17

EA
ALE
PSEN
MC

EA

AB23

AC23
SDA
AC24
SCL

AD26
0
PWM AC25
1

100R

3S2G

SDA-UP-MIPS
SCL-UP-MIPS

100R

3S2K

3S2H
100R

LED1
LED2

3S44
10K

3S43

IS3D

10K 3S42

10K

PSEN

PSEN
3S2F
100R

AE23
SDO
AF25
SDI
SPI
AF24
CLK
AF23
CSB
AB17
0
AA18
1
AD18
2
AE18
3
P0
AF18
4
AA19
5
AB19
6
AC19
7

ALE

ALE

AC26

IS3F
IS3E

EA

RES

SDA-UP-MIPS
SCL-UP-MIPS

3S6V
4K7
RES

LED1

10K

LED2

IS2V

CTRL-DISP
RESET-DVBS
RESET-USBn
RESET-ETHERNETn
SEL-HDMI-ARC
RESET-AVPIP
RESET-AUDIO
AUDIO-MUTE-UP

RES

3S41
10K

PNX-SPI-SDO
PNX-SPI-SDI
PNX-SPI-CLK
PNX-SPI-CSBn

IS2Z

3S6W
4K7

3S1P

RES
10K
RES 3S3Y
10K

CTRL-DISP
RESET-DVBS
RESET-USBn
RESET-ETHERNETn
SEL-HDMI-ARC
RESET-AVPIP
RESET-AUDIO
AUDIO-MUTE-UP

10K

3S2L

3S2S
RES
3S3W
4K7

RES
10K
RES
10K
10K

3S46
+3V3-STANDBY

3S47
3S2M
RES
3S49

4K7

+3V3-STANDBY

+3V3-STANDBY

7S20
NCP303LSN28
2

FS45
1

IS2U
5

INP
OUTP
CD

1K0

10K
3S3T

STANDBY

1 3S2V 2

10K
RES 3S3S

AC20
0
AD20
1
AE20
2
AF20
3
P2
AA21
4
AB21
5
AC21
6
AD21
7

RESET-STBYn

AB24

FS0Z

RESET-STBYn

NC GND
3

3S3P

LCD-PWR-ONn
EJTAG-DETECTn
LAMP-ON
STANDBY
FAN-CTRL1
FAN-CTRL2
POWER-OK
ENABLE-3V3n

AA26

10K

LCD-PWR-ONn
EJTAG-DETECTn
LAMP-ON
STANDBY
FAN-CTRL1
FAN-CTRL2
POWER-OK
ENABLE-3V3n

RESET_IN

100n

3S3M

RES
10K
3S3N RES
10K
3S3Q RES
10K
3S3R
10K RES

XTAL_OUT

+3V3-STANDBY

10p

AF17

2S4K

10K

1
AE17

10p
2S4F

9S0E

3S3L

2
4

RES

+3V3-STANDBY

RC
TACHO
CEC-HDMI
BACKLIGHT-PWM-ANA-DISP
SDM

7S00-9
PNX85500
XTAL_IN

2S4G

9S0D

3S1E
10K

RC
TACHO
CEC-HDMI
BACKLIGHT-PWM-ANA-DISP
SDM

DS50

VDD_XTAL

10K
3S1D
27K

RES
10K
RES
3S1F

AD17

3S1C

AD19
0
AE19
1
AF19
2 P1
AA20
3
AB20
7

VDDA_ADC2V5

2S4D
1n0

3S1B

VSS_XTAL

+3V3-STANDBY

VDDA_1V1_DCS

AA17

IS20

54M

100n

1S02

9S24

1u0
2S11

RES

2S37

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_018_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 169

Power

B02H

2S5A

RES 10u

100n

2S6A

+1V1

B02H

5S80

IS3Q

PNX85500: Power

30R

5S81

2S5B

RES 10u

100n

2S6B

+2V5
30R

5S82

IS3S

100n

+3V3

VDD_3V3_SBY

2S5D

2S4M

100n

1
10u

2S4P

100n

2S4N

VSSA_USB

VDDA_2V5_VADC
VDDA_2V5_VDAC
VDDA_3V3_USB

100n

2S4Y

10u

2S50

100n

2S4Z

6.3V
10u

100n

+1V2
30R
c000

SENSE+1V2

Y17
D13
POL

T20
Y13

+2V5-AUDIO

Y10

100n

VDDA_2V5_USB

30R

R21

R20

100n

2S45

+2V5-AUDIO

5S87
+2V5
1u0

2S56

100n

2S55

30R

5S88
30R

10u

100n
2S57

2S5M

+2V5-LVDS

5S89
100n
2S58

10u

100n
2S6K

2S6H

+2V5
30R

5S90
+2V5
10u

100n
100n

2S53

2S4T
2SHW

30R

5S92
1u0

100n
2S59

+3V3
30R

100n
2S6L

IS58
2S6M

VDD_1V1_DDR

VSSA_1V1_LVDS_PLL

VDDA_2V5_LVDS_BG

AA7

+2V5

30R

5S84

AA9

2S46

VDDA_2V5_DCS

5S95

Y12

RES 1u0
2S4W

+1V1
IS3L

2S52

VDDA_2V5_ADAC

5S83

B13

2S51

VDDA_2V5_AADC

10u

100n

Y19
Y18

AA15
Y15
VDDA_1V2
AA13
VDDA_2V5

2S6P

100n

100n
2S6C

2
100n
2S6N

+3V3-STANDBY

IS3K
VDDA_1V1_LVDS_PLL

+3V3

30R

W20
P20
M20
K20
V7
Y8

2S6F

5S85

10u
2S4U

VDD_1V1

C7
C9
C11
C14
C16
C18

2S4V

VDD_3V3

+2V5-LVDS

N6
N7

100n
1 2S6G 2

VDD_2V5_LVDS

U22

VDD_2V5

220u 6.3V

100n
2S6E 2

U20
U21

2S6D

HDMI_VDDA_2V5

+2V5

30R

HDMI_VDDA_1V1

V20
V21

HDMI_VDDA_3V3_TERM

VSSA_2V5_LVDS_BG

1u0

2S21

100n

2
2S5P
1

VDD

C13

J7

30R

VDD_1V8

A13

2S29

220u 2.5V

100n

5
100n
2S5J-4
4

3
5S94

+1V1

10u
RES

VSS

2S4S

VSS

VSS

M7
N2
N20
P10
P12
P14
P16
P18
P4
P6
P7
T10
T12
T14
T16
T18
T2
T6
T7
U4
V10
V12
V14
V16
V18
V2
Y20

AF1
AE2
AD3
AC4
AB5
H20
F11
G11
F13
G13
F15
G15
F17
G17
F19
G19
J9
J11
J13
J15
J17
L9
L11
L13
L15
L17
N9
N11
N13
N15
N17
R9
R11
R13
R15
R17
U9
U11
U13
U15
U17
J6
AA6
Y7
W7
F9
G9

U24
V24 HDMI_AGND

100u

2S23

5
100n

100n
2S5H-4

100n
2S5H-3
3

100n
2S5J-2

8
100n
2S5J-1

6
100n
2S5J-3

4
3

8
100n
2S5H-2

6
6

AA16
AA8
Y11
Y14
Y16
Y9

VSS

G14
G16
G18
G2
G20
G8
H4
H6
H7
J20
K10
K12
K14
K16
K18
K2
K6
K7
L20
L4
M10
M12
M14
M16
M18
M6

A1
A10
A12
A15
A17
A19
A26
A3
A8
B1
B20
C20
C4
D2
D20
E13
E20
E4
F10
F12
F14
F16
F18
F20
F8
G10
G12

100n
2S5K-4

100n
2S5K-3

100n
2S5K-2
2

2S5K-1

100n
2S5H-1

100n
2S5G-4

100n
2S5G-3

7
2

100n
2S5G-2

2S5G-1
1

22u

22u
2S4R

100n

2S4Q

100n

2S27

2S28

100n

2S43

+1V1

30R

5S93
L6
L7
R6
R7
U7
A5
A6
B5
B6
C6
D6
E6
F6
G6
F7
G7

7S00-10
PNX85500

VSSA

RES 10u

c001

SENSE+1V1

7S00-12
PNX85500

100n

2S5C

100n
2S68

100n
2S67

100n
2S66

100n
2S65

100n
2S64

100n
2S63

100n

2S62

100n
2S61

100u
2S60

2S26

+1V8

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_019_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 170

Analog video

PNX85500: Analog video

B02I
2S87

AV1-CVBS

Y-SVHS

2S8A

47R

3S5B

22n

56R

Connectivity

3S59

47R

22n

3S05

B02I

2S7J

AV1-R

C-SVHS

2S22

3S4J

56R

22n

22n

EU: SCART1

CVBS-MON-OUT1
22n

560R

3S5E

2S7K

AV1-B

56R

3S4L

AP:

3S08

560R

47p

2S7H

2S40

IS4V

22n

8K2

IS4W
3S09

56R

3S4K

AV1-G

2S7M

YPBPR1-SYNCIN1

10n
2S7L
56R

3S4P

AV3-Y

22n

2S7N

AP:

56R

YPBPR1
YPBPR1

3S4R

AV3-PR

EU:

22n
7S00-1
PNX85500

ANALOG_VIDEO

2S7P

2S8G

AV2-CVBS

9S18

22n

AB14
AF14
AE14
AC14
AD14

2S7R

AV4-Y

SCART2
YPBPR2

22n
9S19

EU:
AP:

AF15
AE15
AC15
AD15

AF16
AD16
AE16
AB18
AC18
AF4
AD24
AD25

AF11
AE11
AB10
AA11
AC16
AB16
AB13
AB12
AA12
AA10
AD12
AB11
AE12
AF12

IS5E

3S5S
10K

IS5D
IS5F
IS5G
IS5H
IS5J

3S75
BS15

PNX-IF-AGC

10K

BS10

IS11

3S76
10n

2S76

AA14

PNX-RF-AGC

47K

9S20

22n

2S14

BS13

AGND
2S7U

2S15
22n

AD11
AC11

+CVBS
AV4-PR

2S16
22n

22n

22n

IS5C

2S18
22n

AC12
AF13

2S19

CVBS_Y1 ATV_CVBS_Y3
R
C3
B AV1
CVBS_Y7
G
C7
SYNCIN1
Y_G1
CVBS1_OUT
CVBS2_OUT
PR_R_C1
PB_B1
RESREF
CVBS_Y2
CURREF
SYNCIN2
Y_G2
1
PR_R_C2
2
PB_B2
3
REF
4
R
5
6
G VGA
B
HSYNC_IN
IF_AGC
IN
RF_AGC
VSYNC
OUT
SCL VGA_EDID
P
TUNER N
SDA

10n

AB15
AC13
AD13
AE13

22n

2S75

56R

3S4T

AV3-PB

2S77

PNX-IF-P

10n

2S7E

AV4-PB

2S78

9S21

22n

PNX-IF-N

10n

2S84
56R

3S50

R-VGA
22n

2S85
56R

3S52

G-VGA
22n

2S86

100R

3S5V-2

5
100R

3S5V-4
4

100R

100R

3 3S5T-3 6

100R

V-SYNC-VGA

3S5T-2

3S5T-1

H-SYNC-VGA

AP: VGA

22n

3S5T-4

56R

EU: VGA

3S54

B-VGA

100R

VGA-SCL-EDID

VGA-SDA-EDID

RES

RES

3S5V-3
100R
3S5V-1

100R

* 319803104790 - RST SM0402 47R PMS Col R at 9S18 for BRZ

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_020_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 171

10-13 B03 393912364955


Audio

Audio

B03A

+AVCC

7D03-1
BC847BS(COL)

+24V-AUDIO-POWER
FD14

3D09

+24V-AUDIO-POWER

B03A

220R

GND-AUDIO

1u0

3
6

3D02-3

7D15-2
BC847BS(COL)
4

4K7

ID19
ID18

6
5
18
17

2D16

GND-AUDIO
2D17

ID29

11
7
4
2

1u0
ID30

1u0
AUDIO-MUTE-UP

1
3
L

AVCC

47n

ID37

IN
L

2D26
RES

2D22
220n

3D14-1
220n

7
3D14-2
22K
2

7D10-1
TPA3123D2PWP

R
PVCC
BSR

CLASS-D
AUDIO AMP

3D14-3
22K

5
3D14-4
22K

22K

2D08

GND-AUDIO

10
12

2D23

ID15

19
20

2D29

4K7

FD03

3D02-1
8
1

+AUDIO-L

220n

5D07

2D19

7D15-1
BC847BS(COL)
1

4K7

ID28
220u 35V

7 3D02-2 2

47n

ID27

2D07

FD08

3D02-4

A-PLOP

4K7

1u0

220u 35V

2D24

ID14

2D20

2D28

FD01

GND-AUDIO

220n

2D05

10u 35V

22K

-AUDIO-R

220R
5D08

ID12

220n

3D16
ID11

2D06

4R7

R
OUT
L

0
GAIN
1

BSL

16

ID32

2D10
5D05
ID06

22u

22
21

5D02

ID10
220n

15

5D01

ID09
ID31

2D09

22u

ID05

2D12

220R

ID08

35V 220u

5D04

ID07

2D11

220R

RIGHT-SPEAKER

LEFT-SPEAKER

35V 220u

220n
VCLAMP
BYPASS
MUTE
SD
PGND

3D01-4

2D21
220n

3D10-1
220n
1

2D27
RES

7
3D10-2
22K
2

3D10-3
22K

4n7

DETECT2

GND-AUDIO

GND-AUDIO

LEFT-SPEAKER

VIA
VIA

VIA

VIA

37
36
35
34

GND-AUDIO

10n

26
27
28
29

GND-AUDIO

V_NOM
2D14

7D10-2
TPA3123D2PWP

GND-AUDIO

GND-AUDIO

40
39
38

2D03

47K
100p

GND-AUDIO

GND-AUDIO

+3V3-STANDBY
ID35

GND-AUDIO

RES 2D31

ID34

7D11-2
BC847BS(COL)
4

EMC 4n7

1D50

22K

RES 2D30

CD10

25

23
24

EMC

4K7

47K

MAINS SWITCH DETECT

GND_HS

7D11-1
BC847BS(COL)
1

3D15

+3V3-STANDBY

3D01-3

3D10-4
22K

8
9

AGND

13
14

FD09

A-STBY

VIA
30
31
32
33

1735

LEFT-SPEAKER
3

100K

3D06-2

100K

100K

10n

4
RIGHT-SPEAKER
ID33
1D52

GND-AUDIO
3D06-4

2041145-3

2041145-4

100K

1
2
3

8 3D06-1 1

RIGHT-SPEAKER

FD02

1D38
1
2
3
4

2D02

V_NOM

3D06-3 FD07

GND-AUDIO

10n
2D13

GND-AUDIO

2D01

220R
3 7D03-2
BC847BS(COL)

FD05
FD06

5D03

5
10u
GND-AUDIO

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_021_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 172

DC/DC

B03B

DC/DC

B03B

5U03 RES
30R
5U02

FU05

IU22
+12V
1u0

2U20

10u

10u

7 8

IU10

12V/1V8 CONVERSION

3R3

3U11

2U19

2U25

7U02-1
SI4952DY

10u

10u

2U23

2U24

30R

FU02

2U21

5U00

FU03
22u

47u

2U16

47R

2U15

7
3U23-2

47R
3U23-1

47R

3u6

5 6
IU23

1n0

2U17

IU09

7U02-2
SI4952DY

3U23-4

47R
3U23-3

220p

+1V8
IU11

IU15

IU08

5 6 7 8

IU12

3U14
IU07

GND-SIG

20

VIN

3U28
GND-SIG

18
19

FU04

1u0

10u

2U05

10K

100n

2U14

RES 100u 2.0V

22u

2U13

IU17

IU25

GND

+1V1

IU18
1u0

2U10

GND-SIG

1n0

2U09

GND-SIG

3U21

FU00

SENSE+1V1

IU19

GND-SIG

2U07

RES 100p

22K

3U10

GND-SIG

FU08

100n

1% 330R
1% 1K0

CU00

5K6

FU09

IU04

3U19

3U22
1K0 1%
3U09

330R 1%

1K0 1%

3U08
+1V8

100p RES

IU20

RES
2U29

3U17
3U18

100R 1%

2U08

10K

V5FILT
VREG5

7
17

47u

1
2

2U12

TEST

10R
RES

1
TRIP
2

22
15

3U20

1
2

+1V1

47R

PGND

FU01

2u0
47R
3U24-1

1
VFB
2

5U01

FU06

24
13

3U24-2

1
2

47R

SW

12V/1V1 CONVERSION

1
12

47R
3U24-3

1
VO
2

1 2 3

3U24-4

1
2

5 6 78
4
IU14

1n0

IU02

DRVH

2U06

3U00

3U01

3U03
12K

1
EN
2

23
14

2U11

22K
GND-SIG

21
16

1
2

2U04

1
2

+3V3-STANDBY

5
8
IU01

DRVL

7U04
SI4778DY
IU16

6U00

1n0 RES

2U03
IU03

4
9

+1V1
+1V8

1
VBST
2

220p

STPS2L30A

3
10

ENABLE-1V8

3R3

2U01

100n

2
11

IU24

GND-SIG
3U02

3U05

7U03
TPS53126PW

IU13

10R

2U02
100n

7U00
BC847BW

3R3

2U22
IU06

IU05

RES

1 2 3

3R3

10u

2U00

10R

3U04

1n0

3U27

2U18

7U01
SI4778DY

IU21

CU01
CU02
CU03
CU04
CU05

GND-SIG

GND-SIG

GND-SIG

GND-SIG
GND-SIG

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_022_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 173

DC/DC

DC/DC

B03C

B03C

+3V3-STANDBY

+3V3

RES 10K

+5V +3V3-STANDBY

3U75

3U74

RES 10K

LED-2

IU43

3U59

LED2

10K RES

IU47
7U43
BC847BW

10K RES
+3V3

3U70

LED1

3U53

LED1

10K

10K

**

+12V_AL
4
FU07

3D-LR

100K
IU41

100R

100p

BL-SPI-SDO
BL-SPI-CSn

+3V3-STANDBY

3U71

STANDBY

7U48-2
BC857BS(COL)

100R

3U62-4

3U83-2

100K

IU40

100K

100R

FU53

3U42

BACKLIGHT-PWM_BL-VS

3U43

BACKLIGHT-BOOST

3U61

RES 10K

10K

2
7

3
5

7U41-2
BC847BS(COL)
8

22K

3U60-4
4

IU50

4K7

IU62

6
1
7U41-1
BC847BS(COL)
1

LAMP-ON

DETECT2

10K

3U60-1

IU57

ENABLE-3V3n

22K

IU52
RES 10K

1n0
RES

100R

3U73
+3V3-STANDBY
3K3

3U45

FU51

10K
6
3U62-1

ENABLE-1V8

FU72

IU63

10K

FU76

3U60-2

3U80

2U55
IU56

FU73

22K

3U63

GND-AUDIO

3U81

3 3U60-3 6

3U62-2

1K0

3U72

100p
RES

2U49
+24V

+3V3

IU49
6
7U40-1
BC847BPN(COL)

10n

+24V-AUDIO-POWER

FU67

2U50

FU66

3
IU61

22K

IU51
T 3.0A 32V

3U62-3

3
+12V

+12VIN

FU52

100R

4U01
RES
4U00
RES

FU55

IU55

3U64

POWER-OK

Optional table for 4U00 and 4U01

10n
2U46

1n0
2U45

100p
2U44

100K

Items

3U65

1n0

GND_AL

2U53

1K0

**

+12VIN

1U40

2U54

BZX384-C6V2

10n

1u0 RES

+3V3-STANDBY

6U40

FU58
FU59
FU60
FU61
FU63
FU75

2U58

1-2041145-4

IU48

3U83-3

10n

FU62

3
4

1u0
2U47

1
2
3
4
5
6
7
8
9
10
11
12
13
14

7U40-2
BC847BPN(COL)

10K

2U68

1M95

ENABLE-3V3-5V

BL-SPI-CLK

RES 100p

100R

RES
3U67
100R
RES
3U84
100R
RES
3U76
MAINS-OK
RES 100R

2U43

RES 100p
2U52

2U51

RES 100p

100p RES
2U72

1n0
2U48

1n0

RES 2U56

1-2041145-3
RES 2U57

3U66

FU56
FU57
FU74
FU68

2U71

+12VIN

7U48-1
BC857BS(COL)

3U44

FU54

3U83-4

10K

3U83-1

+3V3

FU50

GND_AL

1K0 RES

3U56

FU49

**

GND_AL

IU64

3U82

FU48

**

100n

GND_AL

1
2
3
4
5
6
7
8
9
10
11
12
13

LED2

7U42 RES
BC847BW

*
1M99

3U41

100K

3U69

9U42
RES

LED-1

To be connect directly to 1M59 with 3mm Track width

**

IU44
IU45

RES 10K

optionally 1M99 is a 9 pin connector

10K

3U68

9U41

If 1M99
is not mounted

If 1M99
is mounted

For non-Amblight sets

4U00

yes

no

no

4U01

yes

no

no

Dream Catcher
Core Range

2U44

3U43

1M95

0R

open

13 POLE

100p

100R

14 POLE

+12VD

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_023_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 174

DC/DC

B03D

DC/DC

+3V3

B03D

7UC0
LF25ABDT

+12V

IN

OUT

1u0

2UA4

2K2

3UA0

COM

FUA0
+2V5-REF

7UA0
TS2431

FUA4
+2V5

CUA0

IUB6

+2V5-LVDS

+5V-TUN

3UB0

1u0

2UB0

7UA3
PHD38N02LT

IUB4

IUA5

22R
4

FUA3

+5V

3U16-1

100R

100R
3U16-2

100R
3U15-3
100R
3U15-4

100R
3U16-3
100R
3U16-4

100R

+3V3

100R

1u0

2UB1

+3V3

3U15-2

+1V2

470R

2
470R
3UB7-3
6
3
3UB7-4470R
5
4

3UB7-2

3U15-1

IU26

7UA7-1
BC847BS(COL)
3U13

2UB8

7UA7-2
4
BC847BS(COL)

+5V

470R

+1V8

2UB2

22u

+2V5-REF

7
1K0 IUB2
3UB6-3
6
3
6
1K0
3UB6-4
4
5
1K0
IUB5
3 1

RES 1u0

3UB6-1
1
8
1K0
3UB7-1
8
1

3UB6-2

330R
1%

+12V

7UA6
BC817-25W
3U12
IUB3

330R
1%

+5V5-TUN

NOT FOR 5000 SERIES

ENABLE-1V8
5

+12V

RES
7UA4
TS431AILT

RES

NC

REF

470R

NC

470R
3U26-2

3U26-3
470R
3U26-4

IUB1

1
3UB3

RES

470R
+3V3

BP

+5V-TUN

COM

1 3U26-1 8 RES

INH

1u0

470R
3U29-4

OUT

100n
2UB6

3UB2

IN

2UB5

3 3U29-3 6 RES

+5V5-TUN

470R

IU30

7UA5
LDS3985M50

RES
7U06-1
BC847BS(COL)
1

RES

1u0

+3V3

470R
3U29-2

2UB7

3
RES
7U06-2
BC847BS(COL)
4

3U29-1

4K7

1
3U25-1

RESERVED
5UA0

1K0

30R
1

IU29

SENSE+1V2

4K7

7
3U25-2

IUA6

3U25-3

100K RES

100K RES

3UB1

100K RES

100K RES

3U25-4

3UB5

3UB4

100K

1K0

IUB0

2UB3

+5V
6

RES

22n
2UB4
330p
RES

RES

470R

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_024_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 175

DC/DC

DC/DC

B03E
5UD0

IUD0

+12V

33K
1%

3U06

120K

22u

RES

12

68K
3UD1

1%
3UD0

VIA

10

4n7
3UD2

15

13

7UD0-2
ST1S10PH

IU27

10K

2UD7

IUD6

7U05-1
BC847BS(COL)
RES 1

RES 2UE9

100n

+1V1

RES 2U27

SS36

220u 16V

FUD3
+5V

3u6

VFB
GND
P HS

6UD0

IUD7

2UD6

SYNC

5UD1

22u

IUD3

SW

VIN

2UD4

INH

RES 1n0

2UD3

ENABLE-3V3-5V

22u
2UD5

SW

1
A

10u

2UD2

10u

2UD1

10u

2UD0

7UD0-1
ST1S10PH

+5V5-TUN

30R

14

11

5UD3

FUD2
+3V3

7U05-2
RES
4

3U07

100n
IU28

RES

33K
1%

12

1M0
3UD5

3UD4

VIA

10

15

13

IUD2
7UD1-2
ST1S10PH

BC847BS(COL)

10K

RES 2U28

+1V1

220u 16V

2UE4

22u

22u
2UE3

3u6

VFB
GND
P HS

5UD2

2UE2

SYNC

IUD4

SW

VIN

1% 100K

INH

2UE1

ENABLE-3V3-5V

4n7
3UD3

SW

7UD1-1
ST1S10PH

10u

14

11

7UD2
LD1117DT25
3

IN

S1D

OUT

+2V5

2UE6

100n

2UE5

COM

22u 16V

IUD5

(*) FOR 5000 SERIES ONLY


(**) NOT FOR 5000 SERIES

7UD3
LD1117DT33
IN

OUT

+3V3

100n

COM

22u 16V

2UE8

6UD1
+5V

2UE7

10u

2UD9

10u

30R

IUD1

2UE0

* *
+12V

2UD8

B03E

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_025_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 176

Temperature sensor & AmbiLight

B03F

Temperature sensor & AmbiLight

B03F

5UM1

IUM0

1UM0

+3V3
30R

FUM0

V-AMBI

T 1.0A 63V

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_026_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 177

Fan control

Fan control

B03G
+12V

+12V

1K0

FAN-CTRL1

IUS3 3US5-3
6
3

IUT1

100n

7US1-1
LM339P
14

2US3

10K 7

10K
9

3US7

+12V

3US5-2

10K

3US2

1 3US4-1 8

+3V3

IUS6

10K

7US2
BC807-25W

12
+12V

IUS7

11

IUT2

7US1-2
LM339P
13

IUS4 3US5-4
5
4

10

FAN-CTRL2

10K

22R

BC807-25W
7US3

IUS8

12

3US6

IUS9
47R

3US3

+12V

10K

3US5-1

3US9

+3V3

10K

FAN-DRV
+3V3

10K

10K

3US4-3

7US1-3
LM339P
2

+12V

IUS5

3US4-4

+12V

4
12

TACH01

RES

+12V

10K

+12V
3US4-2

9US0
TACH02

7US1-4
LM339P
1

IUS0

12

B03G

TACHO

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19100_027_110210.eps
110211

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 178

Vdisp switch

Vdisp switch

B03H

1 9UU0-1
RES
2 9UU0-2
RES
3 9UU0-3
RES
4 9UU0-4
RES
1 9UU1-1
RES
2 9UU1-2
RES
3 9UU1-3
RES
4 9UU1-4
RES

7UU0
SI4835DDY

8
7
6
FUU0

47R
IUU1
3UU0-2
7
2

2
IUU2

1u0

3UU3-2

IUU3
7

47K RES
7UU3 RES
BC847BW

3UU0-1

3UU0-3
+3V3-STANDBY

47K

47K

2
3

7UU2-1
PUMD12
1

47K

22n

2UU2
1

47K RES
2UU1

3UU1

+VDISP-INT

IUU0

IUU4 3UU3-3 IUU5 3UU3-4


6
3
4
5
47K RES

VDISP-SWITCH

2UU0

3UU3-1

FUU1
3UU2

+3V3

47K RES
RES 100n

RES
7UU1
SI3441BDV

+12VD

4
PUMD12
7UU2-2

B03H

+3V3

4K7 RES

LCD-PWR-ONn

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_028_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 179

10-14 B04 393912364955


Analogue externals A

Analogue externals A

B04A
FE70

3E37-4

AP-SCART-OUT-R

IE67

2EA4

AUDIO-OUT-L

8 470R 1
FEA0

7E01-1 6

1n0

2E87

1E00

CDS4C12GTA
12V

RES 6E01

100p

2E01

IEC0

3EA7-1

5 100R 4

1u0 16V
AP-SCART-OUT-L

IEC1
2
1
PUMH7

IE22

IEC2

3EA7-4

IE68

2EA5

AUDIO-OUT-R

5 470R 4
FEA1

7E01-2 3

1n0

2E88

1E31

CDS4C12GTA
12V

5
RES 6E03

1K0

100p

2E06

RES

FE71

3E07-4

AUDIO-IN1-R

1u0 16V
AP-SCART-OUT-R

5
4
PUMH7
RES
FE72

3E37-1

AP-SCART-OUT-L

IE23

1n0

2E90

1E53

IE05

1n0

10

13

**

5K6

3E06

1K0

4K7

18p

CVBS-MON-OUT1
2E98

39p

2E97

18K

4K7

3E73
39K

1u0

3E18 2
1
2

10u

3E19

5E80

**

4E02
RES

IE96

18

3EB6-1

IE91
8

470R

19

FE84

IE92

7E05
BC847BW

3EB6-4

RES

CVBS-OUT-SC1

470R

** 4E01

3E45
68R

20

FE85

RES
3E48

MTJ-505H-01 NI LF
IE48

100n

2E74

100p

2E12

17
IE17

100n

2E24

4K7

3E44

IE59

+5V

16

9E09

21

GND_A

3E37-2

68R

2 100R 7

100p

1E22

3E37-3
RES 2E75

RES

75R

3E43

CDS4C12GTA
12V

7E09-1
PUMH7

6E29

AV1-BLK

2u2

15

RES 9E06

+3V3

4E03
RES

14

FE83

* EU

2E81

12

FE82
1E19

CDS4C12GTA
12V

RES 6E28

RES

IE51
AV2-BLK

IE14

RES 9E05

18R

18R

3EB3

RES

IE08
RES 9E08

BC847BPN(COL)

820R

** 4E04

2E99
4p7

IE70

IE60
1 3EB1 2
1

FE81

150p

2E86

150p

1u8

7E06-1
2

9E10

5E76 3E79BEC5

IE55

6
3 BC847BPN(COL)

IE16

AV1-R

11

9E55
3E78

7E06-2

RES 9E07

AP
9E54

IE61

100p

150p

RES
YPBPR1-PR

**

9
2E14

18R

4E05

FE80

1E18

1u8

** 4E06

5
6

FE74

CDS4C12GTA
12V

3E77

RES 6E26

5E74
2E84

150p

2E83

IE54

100p

2E18

1E55

CDS4C12GTA
12V

FE73

FE75
AV1-G

IE89

**

330R

3E76 18R

RES 6E22

9E53

4K7

3E32

12K

+3V3

IE13

3E31

2EB3

* EU
IE18

9E52

3EA1

1
2

AV1-STATUS

YPBPR1-SYNCIN1

IE90

1E01
9E01

2E15

100p

(AV1)
1E12

150p

RES

CDS4C12GTA
12V

18R
2E80

150p

2E79

1u8

1R0

SCART1

5E73 3E75
BEC3

AP

3EA2

3E17

1E54

2E91

AV2-STATUS
+5V

2EB1

IE53

RES 6E23

AV1-B

* EU

100n

3E74 18R

CDS4C12GTA
12V

6E09
RES

9E51

A-PLOP

2K2
RES

1K0 8

100p

YPBPR1-PB

2E04

9E50

3E24

3E07-1

AUDIO-IN1-L

AP

CDS4C12GTA
12V

RES 6E07

100p

2E10

8 100R 1

2E85

1X06
EMC HOLE

1X02
REF EMC HOLE

100R
3E07-2
1K0

3E07-3
3E62

100p

RES 6E32

2E44

27R

1E25

AV1-CVBS

CDS4C12GTA
12V

IE52

1K0 6
3EA7-2

2 470R 7
3EA7-3

*
GND_A

3EB6-2
470R
3EB6-3

3 470R 6

470R

100p

RES 2E76

1E23

CDS4C12GTA
12V

CVBS-OUT-SC1
RES 6E30

B04A

* 3139803190010 - RSI SM 0402 JUMP 0R05 Col at 2E44 & 2E75 for BRZ
** Provision for ESD

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_029_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 180

Analogue externals B

Analogue externals B

B04B
SPDIF out

YPBPR

GND_A

GND_A

3E89

CDS4C12GTA
12V

2E22

30R

AV2-CVBS

IE75

1E07
MTJ-032-68B-46-NI-FE
1

FE59

2
FE41

AV3-PB
YPBPR1-PB

IE76

9E58

3E90

IE77

AV3-PR

18R

CDS4C12GTA
12V

FE42

RES

IE74

9E57

EU
RES 6E52

1E39

100p

2E68

** 4E22

IE73

5E06

18R

FE48

MTJ-032-21B-42 NI FE
2
1E04

IE15
SPDIF-OUT

27R

CDS4C12GTA
12V

1E28

100p

2E67

** 4E21

3E88

9E04

EU

1E03

AV3-Y
YPBPR1-SYNCIN1

AP

FE51

MTJ-032-21B-45 NI FE (PBT)

IE72

18R

RES 6E46

3E87

10p
1E44

IE71

9E29

CDS4C12GTA
12V

RES 6E40

4E20

RES 6E51

**

1E43

100p

1
GREEN

2E27

EU

FE54

MSP-305H-BBB-732-03 NI
2

1E08-3

YPBPR1-PR

GND_A

YPBPR AUDIO
+3V3

CDS4C12GTA
12V
CDS4C12GTA
12V

RES 6E38

1E42

1n0

**

GND_A

2E72

RES
RES

AV3-PR
RXD1-MIPS

9E19
9E12

RES
RES

AV3-PB
TXD1-MIPS

9E17
9E14

RES
RES

AUDIO-IN3-R
AV1-B

9E11
9E18

RES
RES

AUDIO-IN3-L
AV1-G

9E13
9E20

RES
RES

CVBS-OUT-SC1
AV1-R

9E21
9E22

RES
RES

AP-SCART-OUT-R
AV1-STATUS
AUDIO-IN1-R
AV1-BLK
AP-SCART-OUT-L
AUDIO-IN1-L

9E23
9E24
9E25
9E26
9E27
9E28

RES
RES
RES
RES
RES
RES

IE09
AUDIO-IN4-L

1K0
100p

2E35

CDS4C12GTA
12V

3E21

RES 6E19

1n0
1E37

2E36

V_NOM

FE02

2
3
1

9E15
9E16

AUDIO-IN3-L

1K0

VGA ( OR DVI ) AUDIO


1E09
MSJ-035-29D PPO

AV3-Y
AV1-CVBS

IE29

3E96

1E08-2

3
RES
4E24 WHITE

100p

FE49

MSP-305H-BBB-732-03 NI
4

IE31

1K0

100p

GND_A

RES
1E32

AUDIO-IN3-R

2E71

FE43

RES

RES 6E06

RED

1E29

1n0

** 4E23

FE50
2E39

3E97

MSP-305H-BBB-732-03 NI
6
1E08-1

2E40

+T

6
5
4

RES 3E56
RES 3E57

+5V

RES 3E58
0R3

100R
100R
IE34

IE35
RES 3E36

RES 3E41

100R

IE36 RES 3E38 100R RXD2-MIPS


3D-VS
TXD2-MIPS
3D-LR

100R

FE53

FE52

BZX384-C5V1

RES 6E18

BZX384-C5V1

BZX384-C5V1
RES 6E17

RES 6E16

BZX384-C5V1

RES 6E15

1E79

100p
RES 2E26

100p
RES 2E25

1E78

100n
RES 2E23

100p
RES 2E21

1E76

100p

FE46
FE45

1E77

FE47

FE44

RES 2E20

100p

100R
100R

RES
1ECB
1481-702-06S-51

3
2
1

AUDIO-IN4-R

1K0
2E38

CDS4C12GTA
12V

RES 3E54
RES 3E55

31

IE10

3E20

RES 6E20

V_NOM

1n0
1E38

2E37

FE03

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32

DF50-30DP

FE01

1E75

B04B

* 242202606017 - SOC CINCH V 3P 1L3 YEWHRDY at 1E08 for BRZ


FOR 3D

** Provision for ESD

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_030_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 181

Ethernet & Service

Ethernet & Service

B04C
IE07

5E08
+3V3

+3V3-ET-ANA
7

3E53-2

IE49
1

47R
RXD1-MIPS

3E53-4

IE50
3

6E43
IE38

IE32
3E30

47R
3E53-3

FE56

1E06

2
3
1

FE57

MSJ-035-29D PPO (PHT)


FE58

RES
1E71

10u

2E48

100n

2E49

4n7

100n
2E53

2E52

1
2
3

TXD1-MIPS
RXD1-MIPS

25M

15
3E71
RES

21

ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)

22
23
24
25
18

ETH-TXD(3)
ETH-TXER

1K5

12

ETH-RXP
ETH-RXN

29
28

ETH-TXP
ETH-TXN

20

ETH-TXCLK

ETH-RXER

3E64

10K

IE64

ETH-RXCLK

10K

+3V3

RES

3
10K

3E34

10K

3E72

3E68
RES
3E35
RES

ETH-REGOFF

10K

+3V3
ETH-INTSEL

10K

+3V3

9E42

14

CRS

+3V3

RES

3E65

REGOFF
1
LED
2
INTSEL

0
1
2 TXD
3
4
INT
TXER

ETH-RXDV

IE63

13

RXER
RXD4
0
PHYAD
1
RXCLK

ETH-CRS

32

RBIAS

IE39

MDC
MDIO
VSS

+3V3

33

3E51

31
30

26

RXDV

TXEN

17
16

ETH-MDC
ETH-MDIO

P
N

TXCLK

COL
CRS_DV
MODE2

10K

ETH-TXEN

TX

0
MODE
1
RMIISEL
PHYAD2
RXD<0:3>

10K

9E43

provision for BUH


P
RX
N

RST

11
10
9
8
3E70
RES

IO

12K1
1%

19

1A 2A
VDD

3E40

IE26

ETH-RXD(0)
ETH-RXD(1)
ETH-RXD(2)
ETH-RXD(3)

ETH-COL

27

10p

2E54

10p

CR
CLKIN
1
XTAL
2

5
4

3E69
RES
10K

502382-0370
7E10-1
LAN8710A-EZK

2E55

10K

10K

3E33

10K
3E67 RES

3E66 RES

RESET-ETHERNETn

UART
SERVICE
CONNECTOR

47R

IE33

1M0
1E70
NX3225GA

+3V3

IE06

6E44

47R

+3V3

BZX384-C5V1

+3V3-ET-ANA

3E53-1

1E86

TXD1-MIPS

1E85

100n

100n
2E66

2E62

10u
2E63

30R

BZX384-C5V1

B04C

7E10-2
LAN8710A-EZK
34
35
36

VIA

VIA

40
41
42

VIA
37
38
39

CONFIGURATION RESISTOR SETTINGS

Resistor

22R

22R
3E98

3E26

3E99

49R9
1%

49R9
1%

ETHERNET CONNECTOR
ETH-TXP

FE27

1E87
3 ACM2012 2

ETH-TXN

FE28

ETH-RXP

FE29

1E88
3 ACM2012 2

ETH-RXN

FE31

1
FE30
FE61

3E64 (RES)

PHYADD(0) = 1

PHYADD(0) = 0

3E65 (RES)

PHYADD(1) = 1

PHYADD(1) = 0

3E66 (RES)

PHYADD(2) = 1

PHYADD(2) = 0

3E67 (RES)

RMII mode selected

MII mode selected

3E68 (RES)

Internal 1.2V reg. disabled

Internal 1.2V reg. enabled

3E69 (RES)

MODE(0) = 0

MODE(0) = 1

22n

2E60

CDA5C16GTH
16V

6E47-4
4

CDA5C16GTH
16V
RES

6
3

6E47-3

CDA5C16GTH
16V
RES

7
6E47-2
2

8
1

6E47-1

RES

9 11
10 12

3E70 (RES)

MODE(1) = 0

MODE(1) = 1

FE34

3E71 (RES)

MODE(2) = 0

MODE(2) = 1

3E72

INTERRUPT FUNCTION

INTERRUPT FUNCTION

5450-323-183-H3

DISABLED ON

ENABLED ON

nINT/TXER/TXD4 SIGNAL

nINT/TXER/TXD4 SIGNAL

15p

2E59
RES

5E04

RES 27n

CDA5C16GTH
16V
RES

1
2
3
4
5
6
7
8

RES 15p

2E09
15p
3E39

0 ohm

RES

RES 27n
RES 15p
2E58

0 ohm

RES

RES

5E03
3E29

15p

2E08

RES 27n
RES 15p
2E57

0 ohm

RES

RES

5E02
2E07
15p

2E56
RES

3E28

RES 27n

5E01
2E05

RES 15p
0 ohm

3E27

EMPTY

1N00
FE60

RES

POP

+3V3-ET-ANA

3E95

49R9
1%

3E25

3E22

49R9
1%

+3V3-ET-ANA

FE32

ETH-INTSEL
ETH-REGOFF

FE33

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_031_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 182

HDMI

HDMI

ARX2+

MICOM-VCC33

10K

1u0

10u

2ECV

100n

FEC3

3ECH

ARX1ARX0+

ARXCARXC+

65
66

BRX2+

ARX0ARX0+

67
68

BRX2BRX1+

ARX1ARX1+

69
70

ARX2ARX2+

71
72

AIN-5V

HDMI CONNECTOR 2

BRX1BRX0+

BIN-5V
BRX-HOTPLUG

47K

3ECM-3

2
3ECN-2

10R

7
100K
1u0

BRX-DDC-SDA
BRX-DDC-SCL

IE43

35
36
33
34

2ECN

FECC
FECD

BRX-DDC-SCL
BRX-DDC-SDA

FECE
FECF

BIN-5V
47K

BRX-HOTPLUG

20
22

3ECA-1

BRX-DDC-SCL
BRX-DDC-SDA

BIN-5V

HDMI CONNECTOR 1

CIN-5V
CRX2+

3ECM-2

3
3ECN-3

10R

CRX-DDC-SDA
CRX-DDC-SCL

1u0

CRX2CRX1+
CRX1CRX0+

CIN-5V

47K

3E23

100R

IEC4

DIN-5V

3ECM-1

4
3ECN-4

10R

1u0

DRX-DDC-SDA
DRX-DDC-SCL
5EC2

eHDMI+

30R

10p

ARC-eHDMI+
2ECC

CIN-5V

7EC0
BC847BW

3ECD

+3V3-STANDBY

22K
RES

RES
7E02
BC847BW

PCEC-HDMI

47K

CRX-HOTPLUG

3ECA-3

CIN-5V

20
22

BRX0BRX0+

3
4

BRX1BRX1+

5
6

BRX2BRX2+

7
8

6
100K

IE44

2ECP

41
42
39
40

CRXCCRXC+

11
12

CRX0CRX0+

13
14

CRX1CRX1+

15
16

CRX2CRX2+

17
18

DRX-HOTPLUG

FECM
FECN

CRX-DDC-SCL
CRX-DDC-SDA
6

FECK
FECL

3ECA-4

FECA

CRXCPCEC-HDMI
ARC-eHDMI+
CRX-DDC-SCL
CRX-DDC-SDA

FECJ

CRX0CRXC+

1
2

CRX-HOTPLUG

1P02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
23

BRXCBRXC+

5
100K

IE45

2ECQ

45
46
43
44

DRXCDRXC+

19
20

DRX0DRX0+

21
22

DRX1DRX1+

23
24

DRX2DRX2+

25
26

IEC6
9EC0

CEC-HDMI

IEC5

100n

DSCL4
DSDA4
CEC_D

N
R0X0
P

2EC3

38

49

10K

37

9
27
64

R4PWR5V

N
R0XC
P

48
47

VGA-SCL-EDID-HDMI
VGA-SDA-EDID-HDMI
9EC2
RES

51

CEC-HDMI

N
R0X1
P
N
R0X2
P
(CBUS) HPD1
R1PWR5V
DSDA1
DSCL1

TX2

N
P

TX1

N
P

TX0

N
P

TXC

N
P

3ECA-2

BRXCPCEC-HDMI

BIN-5V

BRX0BRXC+

DSDA0
DSCL0

+5V-EDID

N
R1XC
P
N
R1X0
P

57
56

HDMIA-RX2HDMIA-RX2+

59
58

HDMIA-RX1HDMIA-RX1+

61
60

HDMIA-RX0HDMIA-RX0+

63
62

HDMIA-RXCHDMIA-RXC+
3ECJ RES

N
R1X1
P

TPWR_CI2CA

N
R1X2
P

CEC_A

(CBUS) HPD2
R2PWR5V

INT

4K7

55

50

52

IE12
FECR

RES
3ECK

MICOM-VCC33

4K7
9EC3
RES

FECY

PCEC-HDMI
3ECL RES

+3V3

4K7

DSDA2
DSCL2
N
R2XC
P

CSCL
CSDA

N
R2X0
P
RSVDL

N
R2X1
P

54
53

10
28

N
R2X2
P
(CBUS) HPD3
R3PWR5V
DSDA3
DSCL3
N
R3XC
P
VIA

N
R3X0
P
N
R3X1
P
N
R3X2
P

3EC3
3EC5

100R
100R

SCL-SSB
SDA-SSB

10p

29
30

(CBUS) HPD0
R0PWR5V

2ECM

31
32

10K
3ECP-3

1u0

IE42

3ECP-1

10R
ARX-DDC-SDA
ARX-DDC-SCL

8
100K

1
3ECN-1

30R

10p
RES 2ECY

RES 2ECX

AIN-5V

3ECM-4

SBVCC33

MICOM_VCC33

1
47K

3EC1-1

ARX-HOTPLUG

ARX-HOTPLUG

10u

RES 2ECW

100n

100n
2EC8

VCC33

AIN-5V

20
22

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FECG 21
23

100n
2EC7

2EC6
6
47K

3EC1-3
3

7EC1
SII9187B

ARX-DDC-SCL
ARX-DDC-SDA

FEC4
FEC5

+3V3

+3V3-HDMI

ARXCPCEC-HDMI
ARX-DDC-SCL
ARX-DDC-SDA

RES
5EC3

FEC7

AIN-5V

ARX0ARXC+

FEC1
FEC2

B04D

SII9187B = 0xB2

FECB

ARX2ARX1+

1P03

74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89

73

EPAD
IEC7

3ECE

22K

FECP

2EC0

1P04
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FEC6 21
23

30R
220u 16V

HDMI CONNECTOR 3

RES 2EC1

+3V3

FEC0

2EC2

I2C Address
5EC0

7EC1

3ECN

NON-INSTAPORT

9187A

4X 3K3

3K3

NON-INSTAPORT

9187B

4X 100K

100K

INSTAPORT

9287B

4X 100K

100K

FECW

3ECF

+3V3-STANDBY

6EC1
+5V-VGA

+5V
BAT54
IE11

3ECG
3ECF

4R7

B04D

FECZ

100K

DDCA-SDA

IE65

3ECU-2

+3V3

10K
2ECU

DDCA-SCL

IE66

4 3ECU-4 5
10K

1u0

SPB SSB TV550


2K11 4DDR EU

+5V-EDID

2011-04-27

2010-12-10

3139 123 6495


19104_032_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 183

Headphone

Headphone

B04E
+3V3-STANDBY

4
PUMD12
7EE0-2
A-PLOP
3

A-STBY

FEE0
2

RESET-AUDIO

7EE0-1
PUMD12
1

2EE0

22K

3EE1-3

3EE1-4

22K

3EE1-2

22K

47p
3EE1-1

22K
2EE5

7EE1
TPA6111A2DGN

100n

2EE1

47p +3V3

IEE2
ADAC(4)

2EE3
1u0

IEE1
2EE4
1u0

3EE0-1
10K

IEE3
2

1
5

3EE0-4

10K

IEE4

5
2EE2

AMPLIFIER

3 3EE0-3 6

2EE6

IEE7

33R
3EE2-4

6
FE36
5

VO

SHUTDOWN
BYPASS

VIA
GND GND_HS

2EE7

IEE8

4V 100u

10
11

AMP1

33R

4V 100u

3EE2-3

3EE2-2
33R
3EE2-1

FE35
7

AMP2

33R

IEE5

10K
22K

A-PLOP

IN-

1u0

IEE6

VDD

IEE0
ADAC(3)

RES 3EE3

B04E

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_033_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 184

10-15 B05 393912364955


DDR

DDR

B05A

+1V8

+1V8

DDR2-VREF-DDR

DDR2-VREF-DDR

B05A

DDR2-CLK_P
DDR2-CLK_N

3B28

DDR2-CLK_P

240R

DDR2-CLK_N

DDR2-BA2

DDR2-ODT
RES
240R

3B01
DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM2

F9
E8
F8
F2
G8
F7
G7
F3
B3

3B23

0
1
2
3
4
5
6
7

DQS

NU|RDQS

3B00-2 2
6 33R
3B00-3 3
8 33R
7 33R
3B00-4 4
5 33R
3B00-1 1

C8
C2 3B02-3 3
D7
D3 3B02-1 1
D1 3B02-2 2
D9
B1 3B02-4 4
B9

3B12
3B13

B7
A8
2B44
RES

0
1 BA
2

7 33R

DDR2-D16
DDR2-D17
DDR2-D18
DDR2-D19
DDR2-D20
DDR2-D21
DDR2-D22
DDR2-D23

6 33R

5 33R
8 33R

33R
33R

DDR2-DQS2_P
DDR2-DQS2_N

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

2p2

A2

G2
G3
G1

DDR2-BA0
DDR2-BA1
DDR2-BA2

DDR2-ODT

ODT

3B03

CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

NC

L3
L7

DDR2-A14

VSSQ

VSSDL

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM3

RES
240R

F9
E8
F8
F2
G8
F7
G7
F3
B3

3B24
33R

1X22
HOOK1

1X23
HOOK1

1X24
HOOK1

2B17
100n
2B37
100p
VDD

VDDL

VDDQ

E2

E1

A9
C1
C3
C7
C9

A1
E9
L1
H9

100n

100n
2B16

100n
2B15

100n
2B14

100n
2B13

100n
2B12

100n
2B11

100n
2B10

2B41

E2

E1

DQ

A3
E3
J1
K9

33R

47u
2B09

2B36
100p
2B08
100n
G2
G3
G1

DDR2-BA0
DDR2-BA1

SDRAM

1X21
HOOK1

VREF

0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

SDRAM
DQ

0
1
2
3
4
5
6
7

DQS

C8
C2
D7
D3
D1
D9
B1
B9

3B05-2
3B05-1

2
1

3B05-4 4

3B14
3B15

B7
A8
2B45

0
1 BA
2

NU|RDQS

3B04-2 2
6 33R
3B04-3 3
7 33R
8 33R
3B04-4 4
5 33R
3B04-1 1

3B05-3 3

7 33R
6 33R

5 33R
8 33R

33R
33R

DDR2-D24
DDR2-D25
DDR2-D26
DDR2-D27
DDR2-D28
DDR2-D29
DDR2-D30
DDR2-D31

DDR2-DQS3_P
DDR2-DQS3_N

RES
2p2

A2

ODT
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

+1V8

NC

L3
L7

DDR2-A14

VSSQ

VSSDL

A7
B2
B8
D2
D8

3B27
240R

0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

E7

DDR2-CLK_N

7B03
EDE1108AGBG-1J-F

VREF

VDDQ

A3
E3
J1
K9

DDR2-CLK_P

240R

VDDL

A7
B2
B8
D2
D8

3B22

VDD

E7

AT T-POINT

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

A1
E9
L1
H9

7B02
EDE1108AGBG-1J-F

A9
C1
C3
C7
C9

100n

100n
2B07

100n
2B06

100n
2B05

100n
2B04

100n
2B03

100n
2B02

100n
2B01

47u
2B00

2B40

1X20
HOOK1

+1V8
DDR2-VREF-DDR

3B25
33R

DQS

NU|RDQS

3B07-2 2
5 33R
3B07-3 3
7 33R
8 33R
3B07-4 4
6 33R
3B07-1 1

3B08-4 4
3B08-2 2
3B08-1 1
3B08-3 3

B7
A8

3B16
3B17
2B46

0
1 BA
2

7 33R

DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D4
DDR2-D5
DDR2-D6
DDR2-D7

6 33R

5 33R
8 33R

33R
33R

DDR2-DQS0_P
DDR2-DQS0_N

RES
2p2

A2

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

G2
G3
G1

DDR2-BA0
DDR2-BA1
DDR2-BA2

DDR2-ODT

ODT

3B09

CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

NC

VSSDL

L3
L7

DDR2-A14

VSSQ

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM1

RES
240R

3B26
33R

F9
E8
F8
F2
G8
F7
G7
F3
B3

2B35
100n
2B39
100p
VDD

VDDL

VDDQ

E2

A9
C1
C3
C7
C9

E1

A1
E9
L1
H9

100n

100n
2B34

100n
2B33

100n
2B32

100n
2B31

100n
2B30

100n
2B29

100n
2B28

47u
2B27

2B43

2B26
100n
2B38
100p
E2

E1

DQ

0
1
2
3
4
5
6
7

C8
C2
D7
D3
D1
D9
B1
B9

VREF

0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

SDRAM
DQ

0
1
2
3
4
5
6
7

DQS

C8
C2
D7
D3
D1
D9
B1
B9

3B11-2 2
3B11-1 1
3B11-4 4

B7
A8

NU|RDQS

7 33R

6 33R

5 33R

8 33R

3B18
3B19
2B47

0
1 BA
2

3B10-2
6 33R
3B10-3
7 33R
8 33R
3B10-4
5 33R
3B10-1

3B11-3 3

33R
33R

DDR2-D8
DDR2-D14
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D9
DDR2-D15

DDR2-DQS1_P
DDR2-DQS1_N

RES
2p2

A2

ODT
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

NC

VSSDL

L3
L7

DDR2-A14

VSSQ
A7
B2
B8
D2
D8

3B21

180R 1%

DDR2-VREF-DDR

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM0

F9
E8
F8
F2
G8
F7
G7
F3
B3

SDRAM

E7

3B20

180R 1%

FB00

RES
240R

3B06

7B01
EDE1108AGBG-1J-F

VREF

A3
E3
J1
K9

DDR2-BA2

DDR2-ODT

VDDQ

A7
B2
B8
D2
D8

G2
G3
G1

DDR2-BA0
DDR2-BA1

VDDL

E7

+1V8

VDD
0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

A3
E3
J1
K9

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

A1
E9
L1
H9

7B00
EDE1108AGBG-1J-F

A9
C1
C3
C7
C9

100n

100n
2B25

100n
2B24

100n
2B23

100n
2B22

100n
2B21

100n
2B20

100n
2B19

47u
2B18

2B42

DDR2-VREF-DDR

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_034_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 185

10-16 B06 393912364955


Display interfacing-Vdisp

Display interfacing-Vdisp

B06A

1G03
T 3.0A 32V

5G01

FG0H

1G00

+VDISP-INT
100n

T 3.0A 32V
RES

2G43

+VDISP
30R
RES
5G02

22u
RES

30R
RES
2G44

B06A

RES
3G28
2K2

IG11

RES
6G00
LTST-C190KGKT

For Development use only

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_035_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 186

Video out - LVDS

B06B

Video out - LVDS

B06B

2G94

100n

FG2J

2G95

100n

FG30
FG31
FG32
FG33

FG11
FG1J

PX3DPX3D+
PX3EPX3E+

FG1K
FG1L
FG1M
FG1N

PX4APX4A+
PX4BPX4B+
PX4CPX4C+

FG12
FG13
FG14
FG15
FG16
FG17

PX4CLKPX4CLK+

FG19

PX4DPX4D+
PX4EPX4E+

FG18

FG1A
FG1B
FG1Q
FG1P

CTRL-DISP

RES 3G38
RES 3G37
RES 3G2Z
RES 3G36
RES 3G30
RES 3G31

100R
100R
100R
100R
100R
100R

FG35
FG2R
FG2K

BACKLIGHT-BOOST
3D-LR
3D-VS-DISP
CTRL-DISP
CTRL-DISP

FG04

47p

60 61
58 59
56 57
54 55
52 53

2G27

47p
2G26

47p
2G25

47p
2G24

47p
2G7A

47p
2G79

47p
2G78

47p
2G76

47p

FI-RE51S-HF

FG2L
FG2M

PX1APX1A+
PX1BPX1B+
PX1CPX1C+

FG2E
FG2F
FG1Y
FG1Z
FG20
FG21

PX1CLKPX1CLK+

FG22
FG23

PX1DPX1D+
PX1EPX1E+

FG24
FG25
FG26
FG27

PX2APX2A+
PX2BPX2B+
PX2CPX2C+

FG28
FG29
FG2A
FG2B
FG2C
FG2D

PX2CLKPX2CLK+

FG1R
FG1S

PX2DPX2D+
PX2EPX2E+

FG1T
FG1U
FG1W
FG1V

2G28
2G29

47p
47p

FG2P

RES 9G0G

FG2N

+VDISP

1G50

TO DISPLAY

EMC 100n
RES 2G9C

PX3CLKPX3CLK+

FG1C
FG1D
FG1E
FG1F
FG1G
FG1H

FG34
FG2H
FG2G

EMC 100n
RES 2G9E

PX3APX3A+
PX3BPX3B+
PX3CPX3C+

47p
47p
47p
47p

100R
100R
100R

EMC
RES 2G9F

2G96
2G99
2G97
2G98

41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

RES 3G32
3G2W
3G2Y

100n

100n

CTRL-DISP

SDA-DISP
SCL-DISP

100n

2G93

FI-RE41S-HF
51
50
48
49
46
47
44
45
42
43

2G91

100n

EMC 100n
RES 2G9D

2G92

2G75

47p
2G77

RES 3G35

RES 3G34

4
3
2
1

9G0K-4
9G0K-3
9G0K-2
9G0K-1

RES 3G33

5
6
7
8

RES

10K

10K

+VDISP

10K

+3V3

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

1X05
REF EMC HOLE

1G51

TO DISPLAY

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_036_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 187

AmbiLight CPLD

AmbiLight CPLD

B06C

B06C

5GA0

FGA0
VINT

+3V3

5GA1

100n

100n
2GA2

2GA1

1u0

2GA0

30R

DEBUG ONLY

FGA1

+3V3

VIO

+3V3

100n

29
30
31
32
37
38
11
9
24
10

10K
RES

4
3
2
1

5
6 100R
7 100R
8 100R
100R

26
IXO3_5
IXO3_6
IXO3_7
IXO3_8
IXO3_12
IXO3_13
IXO3_14
IXO3_16
IXO3_18

IXO2_36|GTS1
IXO2_34|GTS2
IXO2_33|GSR

IGA2

IXO4_19
IXO4_20
IXO4_21
IXO4_22
IXO4_23
IXO4_27
IXO4_28

IXO2_29
IXO2_30
IXO2_31
IXO2_32
IXO2_37
IXO2_38

IGA1
CPLED2

CPLED3
5
6
7
8
12
13
14
16
18
19
20
21
22
23
27
28

TCK
TDI
TDO
TMS

PNX-SPI-CSBn
BACKLIGHT-PWM
3D-LR
3D-VS-DISP
BL-SPI-SDO
BL-SPI-SDI
BL-SPI-CSn
BACKLIGHT-PWM_BL-VS
BL-SPI-CLK

9GA1 RES

3GA1

4
3G10-4
2
3G10-2
3G12
3
3G11-3

RES
47R
5
33R
3
7 3G10-3
33R
3G13
1
10R
6 3G10-1
33R

IGA3
GCK2
+3V3
3
5

GCK3

AMBI-SPI-CS-EXTLAMPSn
AMBI-SPI-CLK-OUT
AMBI-SPI-SDI-OUT_G1
AMBI-SPI-SDO-OUT
AMBI-LATCH2_DIS

33R
8
33R

GTS1

7GA1-1
BC847BS(COL)
1

+3V3
3
5

GTS2

7GA2-2
BC847BS(COL)
4

GND
4
17
25

+3V3

7GA1-2
BC847BS(COL)
4

+3V3

AMBI-PROG_B1
AMBI-BLANK_R1

6
33R

10p

33R
2
33R

3GA5-4
3GA5-3
3GA5-2
3GA5-1

SD51022

10p
2G19 RES

1
3G14
33R
7
3G11-2

10p

10p
2G12 RES

10p
2G11 RES

10K

2G10 RES

8
3G11-1

IXO1_2
IXO1_3
IXO1_39
IXO1_40
IXO1_41
IXO1_42

10p
2G18 RES

36
34
33

GTS1
GTS2
GSR
AMBI-SPI-CS-OUTn_R2-R
AMBI-PWM-CLK_B2
AMBI-SPI-CS-OUTn_R2
AMBI-LATCH1_G2
AMBI-TEMP
CPLED3
CPLED2

3G15

33R

GCK3
GTS1
GTS2
GSR

AMBI-SPI-CLK-OUT-R
AMBI-SPI-SDI-OUT_G1-R
AMBI-SPI-SDO-OUT-R

10p
2G16 RES

3GA3

VCCIO

10p
2G15 RES

PNX-SPI-CS-BLn
PNX-SPI-SDO
PNX-SPI-SDI
PNX-SPI-CLK

2
3
39
40
41
42

VCCINT
IXO1_43|GCK1
IXO1_44|GCK2
IXO1_1|GCK3

10p
2G14 RES

43
44
1

2G13 RES

PXCLK54
GCK2
GCK3

15
35

7GA0
XC9572XL-10VQG44C0100

VIO

1
2
3
4
5
6

+3V3

10p
RES

VINT

2GA6

3GA4

RES
1G37

10p
2G17 RES

2GA5

1u0

2GA3

30R

+3V3
6

3GA6-3

6 330R 3

3GA6-4

5 330R 4

3GA6-1

FGA3
+3V3

SD51022

BACKLIGHT-PWM

9GA0

6GA3

FGA5
FGA2

LTST-C190KGKT

FGA4

6GA2

FGA6
LTST-C190KGKT

1
2
3
4
5
6

6GA1

100R
100R
100R
100R

LTST-C190KGKT

8
7
6
5

6GA0

1
2
3
4

LTST-C190KGKT

2GA4

100n RES

3GA2-1
3GA2-2
3GA2-3
3GA2-4

8 330R 1

RES
1G36
1
2
3
4
5
6

7GA2-1
BC847BS(COL)
1
3GA6-2

DEBUG ONLY
RES
1G35

7 330R 2

GSR

BACKLIGHT-PWM_BL-VS

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_037_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 188

SPI buffer

SPI buffer

B06D

+3V3

20

3GE2

3EN1
3EN2
G3
PNX-SPI-CLK

PNX-SPI-SDO

PNX-SPI-CSBn

7GE0
74LVC245A
1
IGE0

19
2

1
2

17
16
15
14
13
12
11

3GE0-3
47R

3
4
5
6
7
8
9

3GE1-3 6

3GE4

3
47R RES
3GE3
47R

BL-SPI-CLK
1

3GE0-1

8
47R
4 3GE1-4
47R RES

BL-SPI-SDO
AMBI-SPI-CLK-OUT-R
AMBI-SPI-SDO-OUT-R
PNX-SPI-SDI

RES

47R

10

AMBI-SPI-SDI-OUT_G1-R
BL-SPI-SDI

18

7GE1
PDTC114EU

10K

100n

+3V3

2GE0

B06D

PNX-SPI-CLK

9GE0-2

BL-SPI-CLK

PNX-SPI-SDO

9GE0-3

BL-SPI-SDO

9GE1

BL-SPI-SDI

9GE2
PNX-SPI-CS-BLn

IGE1

5 9GE0-4

PNX-SPI-SDI

*
**

BL-SPI-CSn

Buffer

*
**

Direct

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_038_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 189

10-17 B07 393912364955


DVBS-FE

DVBS-FE

B07A

7R01-1

STV0903BAC

100n

10n

2R15

100n

2R14

10n

2R09

GND_HS

+3V3-DEMOD

+3V3-DVBS

+3V3-DEMOD

10n

10n

2R52

10n

2R51

100n

2R50

100n

2R49

100n

2R48

2R47

100n

2R46

22u

2R16

30R

VIA

VDD3V3

2
3
100n

2R17

+1V-DVBS

VDDA2V5

8
7

IM
IP

60
56
RES 2R21

DISECQ-DET
F22-DISECQ-TX

128
20
126
NC
107
NC
IR04
47p
97
98
3R00 IR03
19
18

1n0

RES 2R22
SCL-SSB
SDA-SSB

100R
RES 2R23

3R01
100R
47p

SCLT
SDAT

RESET-DVBS
9R00
RES

3R11
+3V3-DVBS
10K

IR02

62
58
26
23
24
29
27

FR02
FR03
FR04
FR05
FR06

FR07

XTALO

VS
AGCRF1

I2C-ADDRESS : D0
DIRCLK
CLKI
CLKI2
CLKOUT27
N
I1
P

N
Q1
P

0
1
2
3
D
4
5
6
7
CLKOUT
STROUT
DPN
ERROR

0
CS
1
DISEQCIN1
DISEQCOUT1
FSKRX_IN
FSKRX_OUT
NC
SCL
SDA
SCLT
1
SDAT

RESETB
STDBY

0
COMP
1

TCK
TDI
TDO
TMS
TRST

1
2
3
4
5
6
GPIO 7
8
9
10
11
12
13

52

SENSE+1V0-DVBS

63
64
65
67
68
70
71
73
74
75
78
79
82
83
84
86
87
89
90
91
94
95
108
109
111
115
116
119
120

AGC

2R53

1K0

47n

* To be drawn near PNX85500


3R03
3R04
3R05
3R06

47R
47R
47R
47R

NC

NC
NC
NC

TS-DVBS-DATA 4
TS-DVBS-CLOCK
TS-DVBS-SOP 2
TS-DVBS-VALID 1

9R03-4 * 5
9R04 *
9R03-2 * 7
9R03-1 * 8

TS-FE-DATA
TS-FE-CLOCK
TS-FE-SOP
TS-FE-VALID

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

40
41
101
50
49
47
46
44
43
37
35
34
32
30
55

FR00

3R02

16

IR05

3R07
120K
DISECQ-RX

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

100n

2R26

100n

2R25

100n

2R24

100n

100n

2R19

+2V5-DVBS
2R18

VDDA1V0

5
9
13
114
118
123
127

11
12

QM
QP

130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165

VDD1V0

21
38
54
76
80
92
96
106

NC

59
104
103
100

129

IR00

5R00

NC

124

6p8

GNDA

NC

MAIN

XTALI

2R20 RES

10n

100n

2R13

10n

2R12

100n

2R11

10n

2R06

2R05
2R08

100n

2R07

+1V-DVBS

1
4
6
10
14
113
117
121
125

1K0

100n

10n

2R10

100n

2R03

10n

2R02

100n

2R01

2R00

100n

2R04

+1V-DVBS

POWER_VIA

3R10

15
17
22
25
28
31
33
36
39
42
45
48
51
53
57
61
66
69
72
77
81
85
88
93
99
102
105
110
112

+1V-DVBS

122

XTAL

10K

7R01-2
STV0903BAC

3R13

B07A

+3V3RF
3R12

IR06

+3V3RF

IR01

NC

2R43

9
8
7
6
5
4
3
2

XTAL_OUT
IP
IN

SATELLITE
TUNER
I2C-ADDRESS : C6

QP
QN
RF_OUT

AGC
AS
NC

VIA

RF_IN

32
18
19

10u

3R09

2R40

1K0

100p

21
20
7
34
35
36
37
38
39
40
41
42

XTAL

3
3R08-3
2
3R08-2
NC

10p

SCL
SDA

2R61

SYN

4
6 3R08-4
100R
1
7 3R08-1
100R

5
100R

QP
QM

8
100R

IP
IM

0p56

SYN HS
29 33

100p

2R62

1n0

1n0
2R35

1n0
2R33

1n0
2R34
28

2R56

23
24

XTAL_CMD

GND
RF LNA LT MIX DIG BB VCO
5
3
9 10 15 17 25 26

27n

5R02
2R45

1n0

2R29

SM15T

FR01

6R00

LNB-RF1

16

VCO

27p

10n

2R28

2R27

220u 6.3V

10u

10p

2R39
5R01
+3V3-DVBS

9R02
RES

27

10p

AGC

22

10p

12
13

IR08

14

MIX DIG BB
VSS

XTAL_IN

1 2
1

11

2R55

31

10p

1R01
73356-5070
1

2R54

NC

16M

2R38

IR07

SCLT
SDAT

LNA LT

10p

7R02
STV6110AT

3 4
30

10K

10K

3R15 RES

3R14 RES

10p

2R41

1R10
NX3225GA

2R37
+3V3RF

+3V3RF

1n0
2R32

2R31

4R7

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_039_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 190

10-18 B08 393912364955


DVBS supply

DVBS supply

B08A

5T00

IT00

SYNC
A
4

5T01

+1V-DVBS

VFB

GND
P HS
8
9

3T00 RES

15

14

1%

IT24

SENSE+1V0-DVBS

4n7
3T21

100n

2T06

11

+3V3-DVBS

4n7
2T36

3K3

12

22K
3T02

VIA

IT20

47K

1K0 1%
2T10 RES

IT02
13

10
3T03

FT06

IT18

2u0

RES 3T01

7T00-2
ST1S10PH

IT01

SW

VIN

22u

INH

RES 1n0

2T03

+2V5-DVBS

22u
2T05

1
A

2T04

7T00-1
ST1S10PH

22u

22u

2T02

22u

2T01

2T00

30R

SW

+5V-DVBS

1K0 1%
LD3985M25
7T01
IN

BP

FT07

5
4

+2V5-DVBS
IT19

COM
2

5T02

OUT

INH

30R

100n

2T07

1u0

1u0

IT03

2T39

BAS316

2T08

6T02 RES

BAS316

10n

6T00 RES

BAS316

2T09

6T01 RES
+5V-DVBS

7T02
LD1117DT33
OUT

FT08

+3V3-DVBS
16V

IN

2T12

100n

2T11

COM
1

22u

+24V

100u 35V

2T14
IT05

5T03

FT00

2T16

47n

3R3

220n
2T17

2T13

220n

IT04

100u 35V
2T15

3T04

7T04-1
BC847BS(COL)
1

13
12
6
8

3R3

10K

5T04

4u7

RES 2T22

4u7

RES 2T38

10u

1n0

IT11

RES 2T37

10u

2T24

2T23

6T04

SS24

16
17
18
19
20
21
22
23
24
25
26

22R

3T11

33u

100u 25V

+V-LNB
IT32

IT17

1n0

IT12

GND_HS

3T29
3T08

3T10

IT09

15

10u

2T35

IT21

10K

GND

IT10

47n

2T26

1n0

2T25
3T06

100K

IT27

IT08
3T07

ILIM2
SEQ
BP

VIA2

6
+3V3

BOOT2
SW2
EN2
FB2

IT26

2T27

9
10
11

BOOT1
SW1
EN1
FB1

PVDD2

1K0

1n0

2T21

2
3
5
7

IT07

+24V

10K

PVDD1

2T20

14

7T03
TPS54283PWP
IT25

IT06

22R

3T05

22u

6T03

SS24

33u

220u 16V
2T19

2T18

+5V-DVBS

RES
3T31

IT29

3T23

IT13

33K

2T41
RES
2T28

1n0
FT04

RES

+V-LNB

4u7

RES
3T24

SENSE+1V0-DVBS

15K

220p

2T40
2T31 RES

RES
2T29

47K
5%
RES

47K

3T16

3K3
5%

3T15

IT14
2T30 RES

3T17

7T04-2
BC847BS(COL)
4

22n
3T12

3K3

5
IT23

22n

3T14
2K2

BZX384-C
13V

1K0

IT22

6T05
+24V

3T13

IT15

3T25

3K3

V0-CTRL

330K
3T28
100K

RES 10n

RES
IT16

RES 10K

FT05

100n
RES

3T26
2T43

RES 2T34

IT30

2T42

22n

RES
3T19

33K

3K3
5%

3T18

18K
5%
22u

2T33 RES

22u

22n
3T20

RES 3T09

+5V-DVBS

2T32 RES

B08A

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_040_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 191

DVBS supply

B08B

DVBS supply

B08B
+12V

+12V

+3V3-DVBS

3T22

220R

22u

RES

5T50

100R

3T50

100n

2T51

2T50

RES

100u 35V

IT50

IT28

220n

2T52

V0-CTRL

IT60
5T52

6T50

220n

2T53

BAT54 COL

18
NC

BYP

7T50-2
LNBH23Q
34
35
36

2K2

IT55
DISECQ-DET

IT64
6T54 RES

RES
7T51
BC817-25W

IT68

BAS316

IT69

IT59
9T52 RES

VIA
VIA

10n

10u

3T58 RES

2T62 RES

2T60

2K2

1R0

IT67

3T59 RES

STPS2L30A

6T51

+3V3-DVBS
10K

2T61

20

1
2
3
7
8
16
17
23
24
25
26
31
32

3T57 RES

RES

VUP

11

IT66

3T62

150R

VCTRL

15R

22R

TTX

22

3T54 RES

DSQOUT

EXTM

470n

VIA

DISECQ-RX

39
40

VIA
37
38

2T59

470n

15
2T58

100u 35V

IT58

DSQIN

LNB-RF1

3T53

21

3T27

27

2T57

470n

2T56

100u 35V

RES

22K

1n0

IT57

30R

VOTX

3T52

RES

30
5T51

VCC_L

VCC
14

+V-LNB
2T55

12
13

9T51

DETIN

28

IT52

220u

IT54
29

IT63

IT65

RS1D

RES

9T50
RES

VORX

A_GND

IT56

F22-DISECQ-TX
6T53

STPS2L30A

6T52

RS1D

6T55

10K

ADDR

GND_HS

DISECQ-DET

10

10K 3T55 RES


2T54 RES
IT61
IT62
10K
3T56 10n

ISEL
LX

P_GND

LNB-RF1

100R

SCL
SDA

IT53

33

3T60 RES
+12V

9
6

3T61

SDA-SSB

100R

IT51

41
42

SCL-SSB

19

7T50-1
LNBH23Q

3T51

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_041_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 192

10-19 B09 393912364955


Connectors comp

Connectors comp
5C55
30R

1M59

100R

FC79

100n

2C70

FC81

GND_AL
NC

FC83

1C86

+24V

FC82
AMBI-POWER

100n
RES

2C95

1C87

100n

FC84

2C94

T 2.0A 63V

+12V_AL

27

2C96
T 2.0A 63V
RES

3C76

100p

IC73

100R

2C78

IC74

3C77

100p

47n RES

LED-2

TO
LED PANEL

100R

FC89
FC90
FC91
FC92

+3V3-STANDBY
FC93

2C79
IC75

LED-1

3C78

100p

100R

2C80

FC94
+5V

100p
FC95

KEYBOARD

28

1M19

FC88

1
2
3
4
5
6
7
8

100n

FC78
3C70

RC

2C81

FC76

2C77

6C02

FC77

100R

2C93

3C79
10R

100p

FH34SRJ-26S-0.5SH(50)

2C82

100n
RES

RES

V-AMBI

AMBI-BLANK_R1
AMBI-PROG_B1
AMBI-LATCH2_DIS
AMBI-TEMP

100p

6C05

FC75

3C75

LIGHT-SENSOR

RES
BZX384-C5V6

FC74

AMBI-SPI-CS-OUTn_R2
AMBI-LATCH1_G2

2C76
FC87

BZX384-C5V6

FC73

AMBI-PWM-CLK_B2

6C03 RES

FC72
V-AMBI

BZX384-C5V6

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

FC71

100K
RES

FC70

AMBI-SPI-CLK-OUT
AMBI-SPI-SDO-OUT
AMBI-SPI-SDI-OUT_G1

B09A

+3V3

3C74

B09A

GND_AL GND_AL

1M21 RES

FC64
RES 3C93

FC98

1u0

47R

1u0
2C91

RES

47R

19
20
FH52-18S-0.5SH

2041145-4

TEMPERATURE
SENSOR

Dream Catcher

100R

10K
FC99
RES 5C54
+3V3

30R

RES 5C53
+12V

30R

T 1.0A 63V

FAN-DRV

RES 3C92

RES
1C85

+3V3

FC97

RES

47R

2C90

FC86

100R
RES 3C83

1
2
3
4

3C97

RES

10p

FC63

RES 3C82 100R

RES
1M71

FC96

3C96

RES

10p
2C89 RES

100R
RES 3C81

3C95

+3V3-STANDBY
+5V

47R

10p
2C88 RES

FC85

3C94

10p
2C87 RES

RES 3C80

100R
FAN-CTRL2

RXD2-MIPS

100R

FC62

9C00
RES
9C01
RES
9C02
RES
9C03
RES

IC78

1u0

SDA-BL

TXD2-MIPS

RES 3C91

RES 2C85

TACH02

100p

SCL-BL

10K

100p
RES 2C84

TACH01

SDA-SET

RES 3C90

RES 2C83

FAN-CTRL1

+3V3
FC61

SCL-SET

2C86 RES

* HOTEL TV

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

RESERVED

SPB SSB TV550


2K11 4DDR EU

2011-04-27

2010-12-10

3139 123 6495


19104_042_110622.eps
110622

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 193

10-20 313912364955 SSB Layout

5T01
5T00

6GA2

2UE4

6GA3

5UD3

2T33

6GA1

IUS9

2UD9
3U26

2UD6 6UD0

3UD3

2UD4 2UD5

5UD2

3US3

3US2

IUT1

IUS6

2UE1

3UD4

3GA6

1G37
7GA2

9UU1 9UU0

2UU2

5G02

1G00
2G43

3US9 3US6

2U15

3UD5

2UE2

5U01

5C53

3U29

IU15

2UE3

5C54

2U16

2UE6

6U00

IU17

2C85

3C82

2UD8

7US3

2U09
3C93

3C92

1C85

IUD2

7US2

2C83
2C84

3U24

2US3

IU18

2U17

3C90

2U11

3C91

IUS5

2U18

3C81
3C83

5U00

IU23

2T00

2T18

5UD0

IUD4

7UD1

2T01

2T12

2T19

2UD2

IUD1

IUT2

2T22

7T03

7T00

5T03
2T32

2UD1

6GA0

2U27

3UD2

3U06

2UD7

3UD0

3U07

7UD0

3US7

3C80

5UD1

2UE0

3US5

7US1

7U05

2UE9

9US0

3US4

3U23

7U01 7U04 7U02

7UU0

1M71

IUS4

3UD1

5U03

5U02

2U19

2U25

2U23

2U24

IUS3

IU57

2UD3
2U28

7UD3

2UE7

2U20

2UE8

IUD0

2UD0

2T17 5T04

2T11

3C70

2C70

2C96

2G13
3G13

3U81

3G12

3G14

2C95

3G10

3G11

6T03

2T14

1C87
1C86

1UM0

5UM1

2U56

3U56

3U44

3U66

2U43

3U67

3U84

2U52

2U51

2U72
3U76

2U48

3U71

2U68

2U47

2U54

2U49

2C94

5C55

3U42

3U65

3U64

4U00

3U45

2D30

2U58

3U43

2U53

2U45

2U44

4U01

2U46

1M59

1M99

CXXX

2U50

1M95

7T02

Overview top side

3GA5

1P00

7GA1

5G01

1G36

2G44

1G03

3GA2

3G15

6G00

3G28

1G35

IG11

2GA4
3GA1

3B11

7GA0
IGA3

3B26

IGA2

7S02

3S02 3S01

3S28

3S24

9F27

3B00

3S1C

5D07

2R28
9R02

2R33

2R45

2R32

2R29

3R14
3R15

2T50

3S1B

9F28

3S2A

3S3R

3S3N

2S4D

3B13

5R02

2R31

2R55

2R62

3R09

2R38

2R35

1R10

2R40

2R61

2R39

3T22

3S1K

3S3T

2R43

6T55

3S3S

3S1J

3B12

7R02
2R37

3S21

2S4E

2B44

3S29

3S62

3S23

3S03

9S01

3B23

3S1L

3B02

7S00

3S3Q

2D20

3S31

7R01

2R34

2T57

9S00

3S3Y

3S04

7B02

2R46
3R06

3B17

2R54

3R05
3B16

2S09

2R27

1R01

3R08

2R20

3R03
3R04

3B25

2B46

7B00

5R01

2R56

9S93

9S90

3B08

9S91

3B10

7F20

3B07

2D05

5D08

2D19

2G96

9S92

2S4P

2G97
2G99

2R41

IGA1

2G98

3R12

3B19

2F01

7B01

3B18

2B47

1G50

9GA0

7T50

2T55

2T56

6T52

3S3L

3S2M
3S3W

2S87

2S7L

2S7N

2S7U

2S8G
9S18

9S20

3S59

3S4P

3S4R

3S4T

2S77
2S78

3S84
3S83

2G28

1E22

1E54

1E31

2F29

3F36

2F33

3F37

1P08

2F9D

1F25

1E25

2F35 3F28 2F34

5F73

9F04

1FD3
2FDD
2FDC

2F9A

3E20

2E37

6FD2

6FD3

6E20

1T01

1E38

2F98

9E15

1E09

6EC1

6E16

2ECM

6FC7

3FC4

2F81

6FC5

1ECB

3FC3
3FC5

3FC6
2FC1

2FC6

2FC2

6FC1
6FC6
3FC1

9FC5
2FC4

2FC3

9FC4

1FC3 1FC4 1FC2

6FC8
2FC8

1FC5

1P02

1E76

1P03

9FC6
2FC5

2FC7
3FC2

1FC6

6FC2

1FC1

1E78

1E75

1E77

1P04

3FC7

2E25

2ECC

1E79

1P05

6FC3
6FC4

3E56

2E21

3E55

2E23

3E57

2E26

3E58

9FC3

1N00

3F623F63

2F97

3ECM

IEE3

5EC2

1329

IE35

2F60

1E44
9EC3

3E38

2ECN

2E20

7EC1

2ECP

2EC1

IE36

3E41

6E17

3E36

6E15

3ECN IE42

1F52

6E18

IE34

3E54

7EE1
2EE1

3ECF

9E57

3E89

3ECP

3EC5

IEE6
2EE2

2EE5

IEE5

IEE4

3EC3
2E67

6E51
3EE2

9E17

9E50

3EE3

6E46

4E24

4E21

4E20

2EE7

2EE4

2C88

2EE0

3C96

2C89

3EE0

3C97

2C81

2EE3

3EE1

3C95

1E07

3C94

2C87

3ECG

2E05

IC74

2E22

2C90

2C86

IE11

1328

2F99

2ECU

6C05
2C91

1E08

3E27

1E87

1E88

2E62

2E60

6E47

5E06

3C79

5E01

2EE6

2C82

3E26

6C03

5E02

3E28

3E98

3C77
5E08

3C78

2C78

IC75

2C80

2E63

2E56

2C93

1E28

2E57

7EE0

3E25 3E22

3E40

2E66

2E07
3C76

9C02

1E03 1E04

3E72
3C74

6C02

9C03

1E37

1E39

3E35
2C76

1E43

3E68

1E42

3E34

1E29

IE07

2G77

3C75

3FDG

1FD2

IE10

2G75

2C77

1F51

2F86
3F75

3E21

2E38

6E19

2E35

2E36
2E54

3F65

2F9B

IE09

9F71

2E27

5F72

6E40

2E40

3E96

6E38

6E06

2E55

2E71

7E10

9E13

3E33

2G27
2G76

3E30

3G38

2G78

2E39

9E11

1E70

2G26

3E51

2E72

2E52
2G25

3E88
9E29

4E23

2G24

3E87
9E52

4E22

3E97

9E04

2E53

3F64

1E32

2G79

2F88

2F93

3E65

3E66

3E67

3E70

3E69

2E49

2E48

3E64

9E42

9E43

3E71

2F9C

2G7A

1M19
1M21

5F70

1E85

1E06

1E18

1E55

7F70

2F32

1E01

5D05
2G29

3F31

3F78

IF89

1E23

1E19

6F72

9F05 9F06

1E12

1F75

7F25

4E01

9E21

4E02
9E22

1E86

1E53

9E05

2E14

IF86

9E18

3E76

4E03

4E04

1E00

3E77

6E26

2E18

2F91
3F72

5E74

2E84

6E22

9F00 9F01

2E83

1E71

3E32

3E31

1F24

IF61

2F92 2F94
2F90 3F71

2F58
3F58

2S4M

3F59
3F60

BS13

7F58

3S12

1F10

2S41

3S13

9E20
9E24

4E05

1P09

2F40

BS10

3S4J 2S7J

2S7P

2S7R
9S19

2S7K

2S7E
9S21

3S4K

3S4L

2S7H

2S2Y

3E17

2S7M

3S6H

3S42

2S2Z

2S30

2S2W
2S2V

2S31

2S33

IS13
4S14

2S2S

3S6J
3S53

5D02 5D01

2S32

2S34

7S08

3S26

2D09

3S44

3S3U

DBS8
9S06

3S3H

2S2R
2S2T

3S3M

3S43

3S3G

5T50

3S50

1S02

5T51

6T51
6T53

3S3F

3B14

3B04

2B45

2D07

3S54

2S4G

2D06

2D12 2D11

3S52
DS50

5T52

IF62

3S80
2S4F
BS15

3S27

2D10

3S4A

3B05

2D24

2D17

2D23

7B03

7D10

5D04

1G51

IS14
3S81

3B24

3B15

3S00

1D52

2D08

1735 1D38

1D50

3S6K

3S4B

1E05

LAYOUT
SSB TV550 2K11 4DDR EU

2011-01-27

3139 123 6495


19104_055_110628.eps
110628

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 194

Overview bottom side

2G10

IUM0

2G16

2G11

2G12

2G14

2G15

FU61

FU66

FU75

FU63

IU22

IU03
IU49

FU73

IU62

2UB8

7U06

IU26

3U13

3S58
3S5W

2S5P

3F41

AF72
FF56
IF53

C000

7U41

3U02

CU02

3D16

FC99

7UU2

CD10

FG1C
2G94

2G9D
ID07

6E01

FE72

2G91

FE85

IF74

2F79

3F80
3F81

3F77
3FE5

2D22

2D26

2FE6

DFE8

FE71

IE72

9E26

9E28

3E07

IE23

2E04

IE71
FE54

FG29

FG24

FG25

FG22

IE51

FG1Y

3G34

FG1Z

IE26
IE22

IE64

FE50

3G30
IE63

IE38

3G36

2E06
9E25

FG20

FG21

3G33

2E88

6E03

FE73

4E06
2E91

6E09

IE14

9E07

9E10

2E75

6E29

3E43

7E09

FE82
IE48

FE49

IE29

FG2E

FG2L

FG2F

3G2Z

IE31

FG2R

FG2K

7FE0

BFE3

2E44

9E16

FE84

3E62

IE16
IE52

2FF0

IE73

2FE4

IE06

2FH5

2FF5

3FG7

2FH7

IE32

3G37
FG2G

3G2Y

FG35
3G2W

DFE7

FG04
IE33

BFE2

3G32

FG34

FG2H

3G35

IE39

DFE6
FE31
FC89

2FG6

FE34

IF17

2FG4

FE33

DFE9

FE29

IF18
FE42

FC87

DFF2

2FH3

2FF4

FE27

2FA4

5FA4

2FF9

IF69

2FG1

5FE8

2FH4

2FF1

2FA3

5E03

2E59

5E04

3E39
FC88

FC90

IEE8

FE02

FFAF

FE30

FECR

9E58

2ECX

2ECY
2EC3
FECY
5EC3

3ECJ

FEC7

IE76

IE45

FEC3

2EC7

IE43

3ECL

FE53

2EC2

2ECQ

FE46
FE44

FE48

IE44

2ECW

2FA2

FE47
FE45

FE52
FE01

3ECH

FE03

FECB
FFA2

FE59

2C79

FC91

FE61
FC92
IE77

3E90

FE60
FE51

9E19

IE74

IE75

FECZ

6E52

2E68

FFB5

7FA3

FE28

3E99

IC73
IEE7

5FA3

2E58

3E29
2E08

DFF1

3FE9

3FE8

2FF2

2FF7

3E95

FE32
2FF8
IF68

FF61

FF63

7FE3

FF62

2FE3

IF67

2FG0

IF49
5FE5
FF03

2E09

2FE8
FF81

2FH2

9G0G

3FE6

3FE7

2FF3

IF29

IEE0

2F59

FG28

FG23

3E73

5FE3

2FG7

2F84 3F76

FG27

FG2M

2FH6
5FE7

3FG2

2FG8

FF76

ID08

FG26

3FG4

2E24

2FE0

2FG9

FF74

FG2A

ID06

3E44

5FE0

IF65

5FE9

FG1T

FG1R

FG2D

3G31

FF82

FFDC

3D14

FG2B

3FG6

2FG3

IF63

IF48

FFDB

IE50

5FG0

5FG2
5FE4

FF00

FF64

FFDA

IE49

FG1S

IF82

1FE0

IF66
2FG2

2FF6

FG1W

FG1V

FG1U

FG2C

IF27

2FE5

IF28

IF64

2F61

2D21

2E10

3E24
9E23

2E90
2E15

IEC1

FE70

FE74

FEA1

3E37

FEA0

6E07

6E23

9E27

9E08

9E51

9E53

IE08

3D10

ID05

FE75

3E74

FE58

AF70

3FBF

7D03

3D09
2B36

2B08

2S42

BEC5
2E86

9E55

3E78

3E79

FE81

BEC3

FG2P

6E32

2F66

5F66

2F28

IF78

IF14

2FH8

FFC9

CU01
2UU0
3UU2

9G0K
2B21
2B14

2B16
2B12

2B11
2B03

2B02

2B04
2B07

2B05

2B06
3S51

2S3J
6E28

2E76

2E80
3E75

7E01

3E53

6E43

IF76

2F75

IF12

2F63
2F64

FE56

7F75

3F35

9F03
9F02

IF41

FFB1

CU04
CU03
2D31

3B20

2B19
3S20

2S24

2S4Q
IS50

2S38

2S3A
3S39

2S2G

2S2H

9E09

FE80

2E01

FG2N

IF15

FFB6

3U80

2B39
2B35

2B26
2S17

2S25
3S6P

2S3F
2S3C

2S2J

3S32

2E85

2E74
3E48

5E73

5E76

2E87

3E19

9E06

2E12

2E98

IE55

IE17
IE92

FE43

2E99

3EB6

IE96

3EA7

IEC2

IF73

6E44

FF75

IF10

IF11
AF71

FF65

IEC0

IE68

2E79

IE70

2F78
2F74

IF42

2F30

FF01

2F25
3F30

FF66

IE59

2E97

7E05
6E30

IE60

IE91

FE83

7E06

3E06

5E80

IE13

3E45

IE61

2E81

2EB3

3EB3

9E12

9E14

FE57

2F27
2F26

3E18

IE89

2F71

IF77

IF13

IF33

3S1D

IE53
2EB1

IF81

FF71

IF30
IF32

FF36

2EA4

2EA5
IE18
IE90

2F96

IF59

IF75

IF31

IF34

3S49

IE15
IF80

FF57

IF90

2F85

IF44

3F79
IF54

3EA2

IF39

9F25
9F26

5F71

IF58

3F52

IF36

FF37

FD06

2D13

ID10

3S0Z

3S38

2F49

3F34

IF40

2D14

IS1D

3EB1

IF72

2F31

2D01

5D03

FD14

FS57

9E01

IF52

FD05
ID32

ID09

ID31

FS52

3EA1

IF35

ID28

2B00

3B03

2D27

7F52

IF50

IF79

2F52

3F32

IF45

3S36

FS53

2F95

2F73 2F80
2F72 2F82
2F77
2F76 AF73

FF55
FF29

IS11

5F74

ID29

IS0R
IS1P

3S3P

FF30

FF39

9F30
9F29

FF38

FF42

2F62
2F70

3F43

FF41

IS1H

ID19

IS12

FS03

3S5E

ID37

FD02

3S47

IS1J

IS02

5F76

2F65
3F82

ID15

ID30

ID18

2B01

2B41

IS07

IS1Q
IF16

FF46

3B28

FD09

IS03

7S05

3S16 3S17

IE54
IF47

IS0V
FF48

C001

2S3E

3S10

3S37

3S6L

3S05

IE67

IE05

3S34

IS06

IS44

3F40

7D15

ID27

3S72

IS20

2S3B

IS5C

2S8A

9S24
IS3E

FS50

FD08

2D29
FD03

IS1S

IS3F
IS2V

IS1N

IS4V

2S3D

IS5G

FD01

FS08

IS1M
2S16

2S3K

2S40

2S19

IS5J

3S08

IS5H
IS2Z

3S2S

2S29

2S3H

3S09

2S2L

IS19

IS3D

3S46

ID33

2D28

2B40

2S36

IS1B

3F45

FF49

FF45

3S6Q

2S60
5S93
2S68

2S4R

2S4Z

3S75

2S18

2S14

FS11

3S5V

IS1A

IS4W

2S75

2S86

FS49

FS44

2S4S

2S23
2S45
2S3G

2S76

2S22

3S18

2S3M

3S25

3F42

IS1K

2S64

2S5J
5S89
5S87
5S81
5S90

5S04

2S53

5S84

2S13

IS5E
3S5S

3S2L

3S5T

3S11

3S6M

IS1E

FF50

FF44

IS1G

3S19

2D02
ID14
2B09

2S46

3S76

3S1H

FD07

ID11
2B13

3S22

IS3L

IS3B

IS5D

3S1G

2S84

2S3Q

2B17
FS02

2S6G

2S50

2S15

DS52

2S10

FS10

ID12

2B37
2B15

IS5F

2S85

IS42

2S20

2S51

FS45

7S09

3D15
2B10
3S0V

2S65

2SHW

FS51

IS1L

2S6E
2S6D

2S6N

3S5B

IS2U

2S52

2S37

2S55

2S11

2S6A

2S5K

2S2K

3S2H

FS0Z

ID34

3B01

IS4Z

ID35

7D11

3S30
3S33

2S43

9S0D

2S4K

IF51
FF04

IT51

2B18

3B22

2S5G

2S4U
3S40

IS16

3S55

2S21

5S95

2S4V

3S0W

2S2E

3S64
3S45

9S09

3B06

2D03

2S4Y
5S83

FG31

2G9C

2B20

3D01

5S88

2S5H

5S92

2S5A
2S59

2S28

2S6M

2S58

2S6K

2S6H

2S5C

2S27

2S5B

3S2K

3S41
3S1P

7S20

IT54

IS05

FC95

IT67

3T53

3F44

5S80

2S6B

2S4W

2S4T

3S2V

IT53

6T50

3T62

IT69

2S6L

IS01

5S94

2S57

IS3Q

2S6C

2S3L

2T58

IT61

2T60

3T60
3T52

IT57

3T27

7T51

9S0E

IT68

2T53

IT60

IT62

3T58
2T54

3T55

2T37

FF43

5S85

IS10
FS64

3S1F

3T50

3T54

2T51

IS3S

IS04

9R04

IT50

FF47

5S82

3S82

2S5D

3S1T

3S1S

3S1U

3S1R

IT59

IT28

IT64

3T59
2T62

2S6F

2R22

9T52

2T61

2T52

3T61

2T38

3S69

3S1E

9R03

2T59

6T54

IT58

IT65

IT52

3S6V

3S1X

2R15

2R26

2R25

2R21

3T56
9T50
9T51
IT63

IT55

3S6W

3F06

IR04

2R09

2S62

IS3K

2S5M

2S6P

IS25
3S1W

IS58

3T57

2S63

IS26

3S56

2S56

2R23

3S2F

2S39

3S6D

3S57

3S6A

IR03
3R01

2R14

IT66

IF37

2B24

2S26

2S67

3S6F

3S5Z

3S5Y

2R52

2R17

2S61

3S15

3S6E

IS40

2R51

3S2G

3S07

2S66

5R00

FG32

FS01

2S4N

3S1V

2R08

IR00

3T51

IF43

FG33

9S08

2G93

FG30

3S61

3S60

FG1D

2G92

3B27
2B22

3S06

IS00
IF87

FG1F

3D06

3S6C

2S89

2B31

2B42

2G95

9S12

3D02

9C00

FG1L

FG1G

FG1E

2D16

9S97

3S67

9S96

3S65

3S6G

IF88

FF33

3B09

3B21

IS08
9S11

3R00

FF32

2UB3

FG0H
2B29
FS31

2R13

2R07

FG1M

FG1J

FG11

FG1H

2B38

3S6B

FG1N

FG1K

2B23

9C01

2B34

2B28

3S68

3S66
9S10

3F19

2R49

2R24

2R16

IT56

FB00

FG12

2G9F

2B25

2R12

2B27

2B33

9S94

9S95

FGA0

FG16

FG14

FG13

2GA1

2R50

FR01

3UB4

5GA1
2GE0

2B32

2S12

3F20

2R02
FR02

IF22

FG18

FG15

2B43

3GE4

7S01

3R13

2R06

2R04

2R05

2R03

2R11

FG1A

FG19

5GA0
2GA0

3GA3

3GE3

3GE2

9S13

3F22

3F12

FG1Q

FG1B

IS09

FR07

FR03

2UB1

2GA3

2GA5

7GE0

2GA6

3GA4

3F21
2R10

IF23

2F20
2F21

FR04

CUA0

FGA3

2F03

9GE1

3F24
IF21

3R11

2R00
2R19

FG2J

FG17

2B30

3F23

2R48

3R02

FUU0

FGA1

2R01
2R53

3UU0

3GE0

IGE0

FF31

2R18

7UU3

FUU1

FG1P

IS15

9R00

FR00

IUU3

FGA5

7GE1

IR01

7UU1

3UU3
IUU4

2G9E

3GE1

2GA2

IS17

IR07

IUU2

IUU5

FGA4

3F07

IR06

IUD5

FUA3

FGA6

7F02

IF07

3F05

9GE2

IR08

IC78

2U14

FU03

IUU0

IGE1

6R00

FC97

FGA2

9GA1

3R10

2U29

IUU1

9GE0

FR05

FUD2

2UE5

IF05

IR02

2UB6

IUB1

2U10

IU40

2UB0

IUB6

7UA5

2UB2

3U41

3F03

7UA3

5UA0

3U15

IU44

2UB5

3F02

3F01

2F02

7F01

3F10

IU19

IU01

FUA4

2UB7

7U42

FC98
3U21

IUB2

3U12

7UA6

7UD2

IU47
IU43

9U41

IUB3

7U43

3U59

FUD3

IF03

IR05

7U48

7UC0

IUB4
IUB5

3UB6

3U16

IU30

3U69

6UD1

3U70

IU45

IU21

CU05

2U71

FU00

3U20

2U13 2U12

7UA7

3U74

7F00

2F00

3F11

2F06

7F05

IF02

IF01

3R07

2UB4

3UB2
3UA0
9U42
3U75

3U53

IF08

FR06

3UB1

IU29

3U68

3F04

FC96

3U03

IU41

3U25

IF06

FU06

IU14
IU25

2U04

IU02

3U83

3UB5

2UA4

IF04

FU05

2U05

IU09

3U61
IU64

IUA6

IU07

IU12

FU02

IU50

3U82

3UB7

3F08

3F09

7U03

IU10
FU04

3UB0

IUA5
IUS7

IF55

2R47

3UB3

7UA0

IU06
2U02

2U00

FU07

FUA0

3U17

IU13

IU61

IU52
IUB0

3U18

3U14

3U63

FS2Y

3U19
2U08

3U09

IU20

IU04

IU08

FC63

7UA4

7F03

3FD4

2F04

IFD3

3U60

FU76

CU00
3U10
2U07

3U22

IU11

IUS8

7F04

3FD6

IFD1
9FD1

6FD1

3FD7

9FD5

3F53

3FD3

2F05
FF58

3F54
3F66

2FD1

9FD2

9CH0

IFD5

7F53
3F67

3FD1

7F54

IF57

3FD2

3F69

2F53

IF56

IFD2

7FD1

IFD4

3F68

FS2W

FU62

2U03

IU16

FU72

IUD7
FC62

FU55

3U01

IU24

2U21

2UU1

FC86

2U01

IU05

IU63
IU28

FU53

IU55

FU08

FU09

3U27

3U73

IUD6

IU48

3U62

IU27

FU52

IU56

3U00

2U55

FC85

FU51

FU67

2U06
FU01

3U05

IUD3

IT06

IT16

FU60

3U72

6U40

2U22

IU51

FU68

2U57

FU59

FU74
FU57

IUS0

7U00

FU56

FU58

3UU1

3T20

FU54

7U40

3T04
IT07

2T31
IT15

FU50

FC61
FC64

3U28

3T24

FU49

FU48
IT05

3U08

3T08

FC79

1U40

3T31

3T07

3T14
3T17

6T05

2T16

FC70
FC72

3U04

IT14

FUM0

FC71

FC78

3U11

2T28

2G17

2T26

2T15

2T27

IT13

3T12

2T29

2T23
2T24

IT25

FT05

3T29

IT17

3T05

IT32

FC73

2G19
FC76
FC82

IT21

IT04

2T13

IT26
IT27

2T40
2T21

3T23

IT29

FT00

7T04

3T06

IT08

2T20

IT10

2T35

2G18
FC77

IT23
IT22

FC74

FC75

FC84

FC83

IT12

2T25

2T41

2T07

IT30

FT04

3T10

IT09

2T43

IT03

6T02

6T00

IT24

IT11

3T13
2T34
3T09 3T15
3T19 3T16
3T18

5T02

FT08

2T10 2T36

FT06

6T04

3T03

FT07

3T11

7T01

2T09

2T39
2T08

3T02

3T00 3T21

6T01

2T05

IT18

2T04

3T01
IT02

IT20

2T06

2T30

IT19

2T03

3T25
3T28
3T26
2T42

2T02

FC81

IT00

IT01

FC93

9E54
FEE0

3ECK

FC94
IE12

IEE1
FE41

9EC2

FFC7
2EC8
FFC2

5EC0
IE65

IE66
FEC0

3ECU

FE36

FFC4

2EC6

FFB4

9FC2

FFC5

2ECV

FFC3

FFB3

9FC1

FFC1
FFC6

IEC7

FECA

FECW

FFC8

IEC6

IEC5

9EC0

7EC0 7E02

3ECE

FECJ
FE35

3E23
FEC2

3ECD

FFB2

2EC0

IEE2

IEC4

FECE

FEC4
FEC5
FEC1

FECM

3ECA
FECF

3EC1

FECD
FEC6

FECK
FECL

FECP

FECC

FECN

FECG

LAYOUT
SSB TV550 2K11 4DDR EU

2011-0?-??

2011-01-27

3139 123 6495


19104_056_110628.eps
110628

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 195

10-21 B01 313912365192


Common Interface

Common Interface

B01A

B01A
+3V3
2F00

TRANSPORT STREAM FROM CAM

19

CA-MOVAL
CA-MOSTRT

3F03-2 2

3F03-1

8
100R

7
100R

3
4
5
6
7
8
9

IF03

18

MOCLK

17
16
15
14
13
12
11

MOVAL
MOSTRT

CA-DATADIR

CA-ADDENn

MOCLK

MOVAL

10

MOSTRT

MDO0
+3V3
2F02

19
IF05
CA-MDO0

3F04-1 1

IF06
CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7

3F04-3 3
3F05-1 1
3F05-3 3

3F04-2
6 100R
3F04-4
8 100R
3F05-2
6 100R
3F05-4

7 100R

5 100R

7 100R

5 100R

3
4
5
6
7
8
9

RES
MDO2
MDO3

3EN1
3EN2
G3

8 100R

MDO1

100n

20

7F01
74LVC245A
1

1
2

18

MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7

1
2

MDO7

10

CA-WAITn
+3V3

CA-INPACKn
2F03

15-BIT ADDRESS
3EN1
3EN2
G3

XIO-A01
XIO-A02
XIO-A03
XIO-A04
XIO-A05
XIO-A06
XIO-A07

17
16
15
14
13
12
11

1
2

CA-VS1n

1
19

CA-ADDENn

CA-A00

3
4
5
6
7
8
9

CA-A01
CA-A02
CA-A03
CA-A04
CA-A05
CA-A06
CA-A07

10

XIO-A00

18

CA-WP

100n

20

7F02
74LVC245A

RES

3F08-2

3F09-1
3F09-2

3F10-1
3F10-2

3F12
10K
7
10K
3F11-3
3
6
10K
3F11-4
4
5
10K
3F11-1
8
1
10K
2

20

100n

3EN1
3EN2
G3

XIO-A09
XIO-A10
XIO-A11
XIO-A12
XIO-A13
XIO-A14

17
16
15
14
13
12
11

1
2

1
19

CA-ADDENn

CA-A08

3
4
5
6
7
8
9

CA-A09
CA-A10
CA-A11
CA-A12
CA-A13
CA-A14

10

18

+3V3
2F05

8-BIT DATA
3EN1
3EN2
G3
18

XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07

17
16
15
14
13
12
11

1
2

CA-DATADIR

19

CA-DATAENn

CA-D00

3
4
5
6
7
8
9

CA-D01
CA-D02
CA-D03
CA-D04
CA-D05
CA-D06
CA-D07

10

XIO-D00

RES

100n

20

7F04
74LVC245A

+3V3
2F06

CONTROL
7F05
74LVC245A

18

XIO-D09
XIO-D08
XIO-OEn
XIO-WEn
XIO-D14
XIO-D15
CA-WAITn

17
16
15
14
13
12
11

RES

100n

3EN1
3EN2
G3
XIO-D11

IF08

+5VCA

+3V3

1P00

CA-D03
CA-D04
CA-D05
CA-D06
CA-D07
CA-CE1n
CA-A10
CA-OEn
CA-A11
CA-A09
CA-A08
CA-A13
CA-A14
CA-WEn
CA-RDY
+5VCA

2F04 RES

XIO-A08

+3V3

3F11-2

+3V3

7F03
74LVC245A

IF04

8
10K
7
10K
3F10-3
3
6
10K
3F10-4
4
5
10K

CA-RDY

IF07

+3V3

3F08-1

8
10K
7
10K
3F09-3
3
6
10K
3F09-4
4
5
10K
2

MDO5
MDO6

3F07-2

8
10K
7
10K
3 3F08-3 6
10K
3F08-4
4
5
10K

MDO4
MDO0

17
16
15
14
13
12
11

20

22u 16V

RES 2F01

+5VCA

CA-CD2n

1
2

1
19

CA-ADDENn

CA-REGn

3
4
5
6
7
8
9

CA-MIVAL
CA-MICLK
CA-A12
CA-A07
CA-A06
CA-A05
CA-A04
CA-A03
CA-A02
CA-A01
CA-A00
CA-D00
CA-D01
CA-D02
CA-WP

CA-CD1n
MDO3
MDO4
MDO5
MDO6
MDO7
CA-CE2n
CA-VS1n
CA-IORDn
CA-IOWRn
CA-MISTRT
CA-MDI0
CA-MDI1
CA-MDI2
CA-MDI3
+5VCA
CA-MDI4
CA-MDI5
CA-MDI6
CA-MDI7
MOCLK
CA-RST
CA-WAITn
CA-INPACKn
CA-REGn
MOVAL
MOSTRT
MDO0
MDO1
MDO2
CA-CD2n
71
72

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70

1X07
REF EMC HOLE

1X04
EMC HOLE

1X08
REF EMC HOLE

1X01
REF EMC HOLE

1X10
HOOK1

1X11
HOOK1

92789-055LF

CA-CE1n
CA-CE2n
CA-OEn
CA-WEn
CA-IORDn
CA-IOWRn
XIO-D10

10

3F01
+T 0R3

IF02

100K

3F07-4

5
10K
7
10K
3F07-3
3
6
10K
3F07-1
1
8
10K

CA-DATAENn

100R
+5V

3EN1
3EN2
G3

CA-CD1n

IF01

3F02

CA-MOCLK

3F06

CA-RST
RES

100n

20

7F00
74LVC245A
1

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_010_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 196

Flash

Flash

B01B

12

7F20
NAND04GW3B2DN6F

37

100n

100n
2F21

2F20

+3V3

VCC

[FLASH]
4G 16
3F20-1 1

3F20-3 3

3F21-1 1

3F21-3 3

100R
3F20-2
100R
3F20-4
100R
3F21-2
100R
3F21-4

100R

100R

100R

100R

3F22-2
+3V3

XIO-OEn
XIO-WEn
NAND-WPn

3F23
3F22-4

7
100R
3F22-3 3
10K
3F22-1 1
5 100R

100R

100R

16
17
9
8
18
19
7

IF22
3F24

+3V3

NC

2K2

CLE
ALE
CE
RE
WE
WP
R
B

IF23
VSS
13

3F19

10K

NAND-RDY1n

0
1
2
3
IO
4
5
6
7

IF21

NAND-CE1n
NAND-CLE
NAND-ALE

29
30
31
32
41
42
43
44

36

XIO-D00
XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07

1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
25
26
27
28
33
34
35
38
39
40
45
46
47
48

+3V3

B01B

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_011_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 197

USB Hub

USB Hub

B01C

B01C

+3V3

USB-OVR1
3FL2

45

26
IFLA
IFL1
IFL2

9F26
9F25

46
17
18

5
9FLC
9FLD

100K

13
14

3 3FLE-3 6

9
10

100K
3FLF
9FLF
9FLG

10K

IFL3

9FLK
9FLL

USB2-DM
USB2-DP

53
51
5
6
42
41
54
1
2
44
43
52

3FLG

+3V3

10K
USB-OVR1
3FLH
+3V3
10K

XOUT
GREEN2
AMBER2

SELFPWR

PWR1
OVR1

VBUSPOWER
RESET

PWR2
OVR2

DD+

SPI_CS
SPI_SCK
SPI_SD

DD1DD1+
DD2DD2+

VIA

RES

NC

4
8
12
16
20
24
28
34
40
47
50
56
1P07
N
N
Y
Y

1P08
Y
Y
Y
Y

1F24
N
Y
N
Y

3FLG
N
Y
Y
N

3FL2
N
N
Y
Y

3FL4
N
N
Y
Y

3FL7
N
Y
N
Y

3F32
Y
Y
Y
Y

3F34
N
Y
Y
Y

7FL5
CY7C65621
CY7C65621
CY7C65631

9FLE 9FLC/D 9F25/6 9FL2


N
N
Y
N
N
N
N
Y
Y
Y
N
N
N
N
N
Y

FL32

2FLC 1n0

2FLB 1n0

10n
2FL3

2FLA 1n0

10n

10n

100n
2FL2

2FLD

100n
2FL1

2FL5

100n

1 3FL4-1 8
100K

37
38
IFLB

+5V
4

9FLE

3
3FLA
3FLB
3FLC

+T 0R3

3F34-4

FL43

+3V3
+3V3

1P07
+5V-USB2

3F34-3

FL40
FL41

USB2-DM
USB2-DP
FL42

2 3F34-2 7

3F34-1

1
2
3
4
5

USB-16-PBT-B-30-CU1-BRF

100K

58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82

IFLF

USB2 (BOT)

+5V-USB1

100K

10K
15K
10K

USB-16-PBT-B-30-CU1-BRF

100K

IFLC
IFLD
IFLE

1
2
3
4
5

3F32

31
32
25
48
49

USB1-DM
USB1-DP

100K

35
36

29
30

3FL4-2

FL36
FL37

100K
+3V3

+5V

RES
RES
RES
RES

1
2
3
4

9FL1-1
9FL1-2
9FL1-3
9FL1-4

8
7
6
5

1
2
3
4

9FL2-1
9FL2-2
9FL2-3
9FL2-4

8
7
6
5

(WIFI)

RES 3FLJ
+T 0R3

RES
1F24
+3V3-1

FL38
FL39
FL30

USB-WIFI-DDn
USB-WIFI-DDp

1
2
3
4
5
6

502386-0570

GND
HS

GND

SCENARIO
1x USB
1x USB + WIFI
2x USB
2x USB + WIFI

+3V3
GREEN1
AMBER1

XIN

9FLH
9FLJ

+3V3

1P08
+5V-USB1

9FL3

22

10K

100K

RESET-USBn
USB1-DM
USB1-DP
USB-DM
USB-DP
USB2-DM
USB2-DP
USB-WIFI-DDn
USB-WIFI-DDp

USB1 (TOP)

3 3FL4-3 6

10K

IFLG

VCC

3FL7

21

2 3FLE-2 7

2FL4

2FL8
IFL4

3
7
11
15
19
23
27
33
39
55

12p

7FL5
CY7C65621-56LTXCT

100K

3FLE-4

+5V-USB2

100K

100K

2FL7
3FLE-1

FL33

FL31

+5V

3FLD

3FL4-4

9FL3
N
N
N
Y

57

+3V3

+T 0R3
4

24M

12p

2FL6

4
2

1FL5

2FL9

1u0

100n

+5V

9FLF/G 9FLH/J 9FLK/L


N
N
N
N
Y
N
Y
N
N
N
Y
Y

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

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div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 198

SD Card

SD-Card

B01D

3F40

FF45

+3V3
22u 16V

+T
2F40

B01D

+3V3-SD

0R3

+3V3

3F41-1

IF47

47K

SDIO-DAT3
2

3F41-2

SDIO-DAT3

3F44-1

SDIO-CMD

FF47

100R

SDIO-CMD

3F43-2

1P09-1
7

FF48

100R

47K
3F45 RES

SDIO-CLK

3F44-4

+3V3-SD

SDIO-CLK

SDIO-DAT0

3 3F43-3 6

FF49

100R

10K
3 3F41-3 6

SDIO-DAT0

47K

4 3F41-4 5

3 3F42-3 6

47K

SDIO-DAT1
SDIO-DAT2

SDIO-DAT1
SDIO-DAT2

47K

FF41

100R

4 3F43-4 5

2 3F44-2 7

100R

FF42

3F42-1

FF46

SCDA7A0200

1P09-2
8

SDIO-CDn

SDIO-CDn

FF44

SDIO-WP

SDIO-WP

FF50

47K
2 3F42-2 7

14
16

FF43

100R

13
15

1
2
3
4
5
6
7
8
9

10
11
12
SCDA7A0200

47K

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 199

PNX85500 Control

PNX85500-Control

+3V3-STANDBY

B01E

+3V3-STANDBY

IF50

512 K
FLASH

BACKLIGHT-BOOST
7F53 RES
PDTA114EU

PNX-SPI-SDO
IF52

10K
RES

10K

10K

3F67

3F66

IF53
1

PNX-SPI-CSBn
IF54

HOLD

+5V

PNX-SPI-CLK

PNX-SPI-WPn
+3V3-STANDBY
FF29

VSS

IF55

BOOST-PWM

IF61

47K

+3V3

+3V3

3F68 RES

PNX-SPI-SDI

3F52

7F52
M25P05-AVMN6

VCC
IF51

+3V3

100n
RES

100p

2F52

2F49

+3V3-STANDBY

7F54-1 RES
BC847BPN(COL) 6

7F54-2 RES
BC847BPN(COL)

SPI-PROG

IF56
4

IF57

2
1

FF04

IF62
SDM

FF58

1K0
RES

RES

3F69

10K

1u0

2F53

MAIN NVM

+3V3

RES

9CH0

10K

3F54

3F53

DEBUG ONLY
IF58

2F58 RES

IF59

(8K 8)
EEPROM

1
2
3

0
1
2

100R
FF62
3F63

FF63

WC
SCL

ADR
SDA

100R

SCL

1
2
3

SDA
5

7
6
5

FF55

3F59
100R

3F60

SCL-UP-MIPS

FF56

SDA-UP-MIPS

100R

3F58

RES
1F52

3F62

SDA-SSB

7F58

FF61

SCL-SSB

100n

10K

B01E

FF57

LEVEL

DEBUG / RS232 INTERFACE

TXD-UP
RXD-UP
RESET-STBYn
SPI-PROG

FF65

3F64

FF66

100R

SHIFTED

RES
1F51
FF64

3F65
100R

1
2
3
4
5

UP

FOR
DEBUG
USE ONLY

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

3139 123 6519


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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 200

Tuner

Tuner

* 1T01

IF11

2F65 RES

15p

820R

1p0

AF73

330n
3F82 RES

2F73

220R

IF16

PNX-IF-N

10n

1K0
2F92

3F72

BA591

4K7

6F72

3F81
220R

2F91 RES

IF13
IF-

10n
IF14

2F64

IF15

22p

220R

2F63

680n
2F66

5F73

10n

IF12

5F66

TUN-IF-P

3F80
3K3

5F70

TUN-IF-N

IF-N-DVBT2

2F90

470n

IF86

3F78

9F06

3F71

9F05

47n

2F85

+5V-TUN-PIN

IF+

10n

ATB2012

* For BR NIM Tuner only

10n

FF81
FF82

IF89

47R
3F75

15p

47R

TUN-P6
IF88

IF90

SELECT-SAW
SCL-TUNER

SDA-TUNER

7F70
PDTC114EU

IF-P-DVBT2

10n

15p
2F86

IF87

RES

3F76

2F94

2F84

3F79-4

AGC CONTROL

10n

IF80

2F72

9F02

10n

IF72

RES 2F95

100n

+5V-TUN-PIN

2F93

2F79

FF01

IF-AGC

FF75

220R

IF79

4K7
IF-AGC
100p

* 9F04

100p

2F60
2F59

FF00

IF78

RES 5F76

VAGC

2F70 RES

OUTPUT2

2F62

INPUT2

5F74

3F77

RES 2F96

100n
4n7

RF-AGC

IF82

PNX-IF-AGC

10n

IF77

X7251M
36M17

TUN-IF-N
TUN-IF-P

*
AF72

3F79-1

2p2
2F77

OUTPUT1

9F03

1
VCC

INPUT1

IF76

2F82

IF81

GND

2F75

2F80

10n
2F78

IF74

RES
2F76

5
4

IF73

5F71

O1
O2

2F74

GND2

I
ISWI

2F9D

2F9B

2F9C

2F99

2F98

2F97

RES 2F81

2F9A

AF71
AF70

FF76

2F61

10n

GND1

6p8

6p8

6p8

6p8

6p8

6p8

1F75
1
2
3

TUN-P6
TUN-P7

+5V-TUN-PIN
7F75
UPC3221GV-E1

IF75

PNX-IF-P

2F71

9F01

9F00

IF_OUT2

NC

13

12

11

IF_OUT1

4MHZ_REF

10

B+_TUN

I2C_SCL

I2C_SDA
7

TUN
4

B+_LNA

RF_AGC
3

14

FF74
4n7

TUN-P1

RF_IO

16

I2C_ADR

TUNER

15

6p8

FF71

B01F

B01F

* For EU Hybrid Tuner only

TUN-P7

9F71
5F72 RES
+5V-TUN-PIN

+5V-TUN

* Remarks
Item No.
1T01
2F61
2F62
9F02
9F03
9F04
9F05
9F06
2F73
2F82
2F72
2F80
2F77
5F71
5F74

22u

2F88

30R

Component
Europe
Brazil
TH26X3
FA23X7
4u7
RES
10p
5p6
Used
RES
RES
Used
RES
Used
RES
Used
RES
Used
1p0
RES
1p0
RES
15p
12p
15p
12p
22p
18p
680n
560n
820n
680n

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 201

Toshiba Supply

Toshiba supply

B01G

+1V2-BRA-DR1

+3V3

IN

OUT

30R

5FA4

7FA3
LD1117DT12

30R

5FA3

+1V2-BRA-VDDC

FFAF
+1V2-FE
* FOR DVBT-2
10u

2FA4

100n

2FA3

100n

COM
2FA2

B01G

FFA2

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 202

HDMI

HDMI

B01H

HDMI CONNECTOR SIDE


1P05
DRX2+

DIN-5V

DRX2DRX1+
DRX1DRX0+
DRX0DRXC+
DRXCPCEC-HDMI
FFB1
FFB2
FFB3
FFB4
20
22

DRX-DDC-SCL
DRX-DDC-SDA

DRX-DDC-SCL
DRX-DDC-SDA

47K

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FFB5 21
23

1 3FBF-1 8

B01H

2 3FBF-2 7

DIN-5V

47K
DIN-5V
DRX-HOTPLUG

FFB6

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 203

VGA

VGA

B01I
3FC5
CDS4C12GTA
12V

RES 6FC1

1FC1

100p

2FC1

FFC1

FFC4

CDS4C12GTA
12V

RES 6FC3

1FC3

100p

2FC3

FFC3

9FC5

H-SYNC-VGA

9FC6

V-SYNC-VGA

4K7

3FC3

CDS4C12GTA
12V

RES 6FC4

1FC4

FFC6
1216-02D-15L-2EC

B-VGA

18R

FFC5

47p

CDS4C12GTA
12V

6FC6

47p

2FC6

10K

RES
3FC2

FFC9

6FC7

47p

2FC7

10K

4K7

3FC4

CDS4C12GTA
12V

RES 6FC5

1FC5

FFC8

CDS4C12GTA
12V

RES
3FC1

47p

2FC5

FFC7

9FC1

VGA-SDA-EDID-HDMI

9FC2

VGA-SDA-EDID

RES

9FC3

VGA-SCL-EDID-HDMI

9FC4
RES

VGA-SCL-EDID

6FC8

1FC6

47p

+5V-VGA
CDS4C12GTA
12V

17

G-VGA

18R

3FC7

2FC4

VGA
CONNECTOR

CDS4C12GTA
12V

RES 6FC2

1FC2

100p

2FC2

3FC6

1E05
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

R-VGA

18R

FFC2

2FC8

B01I

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 204

Temp sensor & headphone

Temperature sensor + headphone

B01J

SCL

A2

1K0

3FD2

9FD2 RES

9FD1 RES

100n

IFD3

IFD5

RES

+VS

A1

9FD5

SDA

1K0

2FD1

1K0
IFD4

IFD1

A0

100R

100R

OS

1K0
3FD7

SCL-SSB

3FD4

3FD6

SDA-SSB

IFD2

7FD1
LM75BDP

GND

3FD3

LTST-C190KGKT

RES

RES
3FD1

+3V3

6FD1

RES
1329

1
2
3

502382-0370

1328
MSJ-035-69A-B-RF-PBT-BRF

FFDA

AMP1

2
3
1

22n

FFDB
22n
2FDD

CDS4C12GTA
12V
2FDC

RES

6FD3

CDS4C12GTA
12V
1FD3

6FD2
RES

1FD2

1K0

1K0
3FDG-4

3FDG-1

AMP2

B01J

FFDC

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 205

Tuner Brazil

B01K

Tuner Brazil

B01K

5FE0

IF63

IF64

+2V5-BRA

+1V2-BRA-VDDC

+3V3-BRA-FLT

1u0

100n
2FF1

100n
2FF0

100n
2FE5

100n
2FE4

2FE3

1u0

2FE0

30R

AGND
5FE3

IF65

IF66

+3V3-BRA-FLT

5FE4
+3V3-BRA

30R
1u0

100n
2FF6

100n
2FF5

100n
2FF4

100n
2FF3

2FF2

1u0

2FE6

30R

AGND
5FE5

IF68

IF67

+1V2-BRA-DR1
IF48

5FE7

+3V3-BRA

+3V3

1u0

100n
2FF9

100n
2FF8

2FF7

1u0

2FE8

30R

30R

5FE8

IF69

+2V5-BRA
7FE3
LD3985M25

5FE9

+5V
30R

18p

2FG3

18p

2FG2

25M4
4 2

1u0

2FG0

1FE0

100n
2FG1

30R
1

IN

OUT

INH

BP

FF03

+2V5-BRA

10n
2FG6

2FG7
AGND

2FG9

100n
2FG8

10n

100n

IF17
IF18

30
29

BFE2

28
27

BFE3

100n
2FH6

100n

24
25

2FH7

100n

26

AGND

39

AGND

0
XSEL
1

FIL

PBVAL
RERR
RLOCK

P
ADI_AI
N

RSEORF

P
ADQ_AI
N

SBYTE
SLOCK

P
AD_VREF
N

SRCK

AD_VREF

SRDT

DTCLK

STSFLG1

DTMB

AGCCNTI

21
58
53
54
55

3FG6-4

33R

TS-BR-VALID

9F27-1

TS-FE-VALID

3FG6-3

33R

TS-BR-SOP

9F27-2

TS-FE-SOP

TS-FE-CLOCK

TS-FE-DATA

SCL-SSB
SDA-SSB

3FE8

100R
3FE9

IF49
100R

45
46

AGCI
SLADRS

CKI
SCL
SDA

AGND

PLLVSS

11

SYRSTN

DFE9
5FG0
3FG7
3FG6-2

60

TN
VSS

0
1

SCL
SDA

33R

9F28

TS-BR-CLOCK

33R TS-BR-DATA

9F27-4

30R
5FG2

DFF1
30R

3FE5
18K

10
51

1u0

DFE8

DFF2

IF28
IF-AGC

AGND

42
6
5
12
14

3FG2-1

RESET-SYSTEMn
10K

3FG2-2
10K

3FG4-2
4K7

3FG4-1
4K7

+3V3-BRA-FLT

4
15
33
37
44
47
50
57
62

STSFLG0

17

10K IF29

0
TSMD
1

AD_DVSS

3FE7

1
41

AD_AVSS

10K

31

3FE6

AGCCNTR

S_INFO

23

10n

DFE7

IF27
40

+3V3-BRA-FLT

DFE6

61

38

1u0

AGND

1n5

59
52

2FH4

* To be drawn near PNX85500

2FH3

2FH5

2FH2

43
DR2VDD

34
48

VDDS

DR1VDD

13
35
49
64

16
36
56
63

10n

2FG4

IF+
IF-

VDDC

2FH8

3
2

PLLVDD

18

AD_AVDD

19

32

AGND

22

AGND

AD_DVDD

AGND

20

COM
7FE0
TC90517FG

AGND

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 206

10-22 B02 313912365192


NANDflash - conditional access

PNX85500 NAND Flash - Conditional Acces

D22
ALE
C21
NAND
CLE

XIO-A00
XIO-A01
XIO-A02
XIO-A03
XIO-A04
XIO-A05
XIO-A06
XIO-A07
XIO-A08
XIO-A09
XIO-A10
XIO-A11
XIO-A12
XIO-A13
XIO-A14
XIO-A15

J25
J26
H21
H22
H23
H24
H25
H26
G21
G22
G23
G24
G25
G26
F22
F23

IS25

00
01
02
03
04
05
06
07
XIO_A
08
09
10
11
12
13
14
15

XIO-D00
XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07
XIO-D08
XIO-D09
XIO-D10
XIO-D11

XIO

B22
OE_
C22
WE_

XIO-OEn
XIO-WEn

CLK_BURST
CE1_
CE2_
NAND RDY2
RDY1
WP_

INPACK
XIO-D14
XIO-D15

B21
E21
D21
A20
F21
A21

IS26

INPACK

3S15
10K

+3V3
NAND-CE1n

NAND-RDY1n
NAND-WPn

9S08

10K
RES

NAND-ALE
NAND-CLE

D25
D26
C24
D23
C23
B23
A22
E22
F24
F25
F26
E23
E24
E25
E26
D24

00
01
02
03
04
05
06
07
XIO_D
08
09
10
11
12
13
14
15

3S1V

FLASH

B02A

10K

3S1W

+3V3

7S00-5
PNX85500

IS00

7S00-11
PNX85500
3S01-1 8
33R
3S01-3 6

CA-MDI0
CA-MDI1
CA-MDI2
CA-MDI3
CA-MDI4
CA-MDI5
CA-MDI6
CA-MDI7

7 3S01-2 2
3 33R
33R 5 3S02-4 4
33R
7 3S02-2 2
33R 8 3S02-1 1
6
3 33R
3S02-3
33R 5 3S01-4 4
33R

P21
P22
P23
P24
P25
P26
N21
N22

CA-ADDENn

J22

CA-DATADIR

K25
K26

CA-DATAENn

3S03

CA-MICLK

N23
10R
L25

CA-MOCLK

N24
3S31
CA-MIVAL
33R

N25

CA-MOSTRT

L22

CA-MOVAL

L23
J21
L24

CA-RDY

L26

CA-RST

J23

RES
9S01

CA-MISTRT

J24
+3V3

VIDEO_STREAM

0
1
2
3
MDI
4
5
6
7

0
1
2
3
MDO
4
5
6
7

10K

3S1X

+3V3

N26
M21
M22
M23
M24
M25
M26
L21

CA-MDO0
CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7

ADD_EN
DATA_DIR

VS

K23
1
K24
2

CD

K21
1
K22
2

DATA_EN
I
MCLK
O

9S00

CA-VS1n
CA-MOCLK
CA-CD1n
CA-CD2n

CA

+3V3

MISTRT
MIVAL

TS-FE-DATA

3S1R

MOSTRT

TS-FE-CLOCK

3S1S

MOVAL

TS-FE-VALID

3S1T

OOB_EN

TS-FE-SOP

3S1U RES

560R
560R

RES

560R
560R

RDY
RST
VCCEN
VPPEN

T21
DATA
T23
ERR
T22
TNR_SER1 MICLK
R23
MIVAL
R22
SOP

TS-FE-DATA

TS-FE-DATA

3S23

TS-FE-CLOCK
TS-FE-VALID
TS-FE-SOP

TS-FE-CLOCK

3S24

TS-FE-VALID

3S28

TS-FE-SOP

470R
3S29 RES

TS-FE-ERR

470R
470R

100n

7S02
5

33R

RES 470R

3S04
2S09

B02A

1
4
2
3

74LVC1G08GW

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 207

SDRAM

PNX85500: SDRAM

B02B

3S07

180R 1%

180R 1%

DDR2-VREF-CTRL2

2S12

N
P

DQS0

N
P

DQS1

N
P

DQS2

N
P

DQS3

N
P

CASB
CKE
CSB
ODT
PCAL
RASB
WEB
VREF

1
2

N5
N4

DDR2-CLK_N
DDR2-CLK_P

3S30
10R

3S33
10R

E2
E3

DDR2-DQS0_N
DDR2-DQS0_P

D3
D4

DDR2-DQS1_N
DDR2-DQS1_P

R1
R2

DDR2-DQS2_N
DDR2-DQS2_P

T3
T4

DDR2-DQS3_N
DDR2-DQS3_P

K3
K4
L5
M4
M1
M5
H3

DDR2-CAS
DDR2-CKE
DDR2-CS
DDR2-ODT
DDR2-RAS
DDR2-WE

A2
V1

DDR2-CKE

3S6Q
10K

DDR2-ODT

3S6P
10K
RES

DDR2-VREF-CTRL2
DDR2-VREF-CTRL3

3S0V

FS01

DDR2-VREF-CTRL3

CLK

2S24

FS02

100u 2.0V

3S06

180R 1%

180R 1%

3S20

+1V8

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DQ
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

1%

F3
C2
F2
C3
B4
F1
C1
E1
F4
B2
E5
C5
A4
G5
B3
F5
U3
P2
U2
P3
N1
U1
P1
T1
V4
R5
U5
P5
N3
V3
R4
V5

M0

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13
DDR2-A14

IS42
261R

DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D6
DDR2-D5
DDR2-D4
DDR2-D7
DDR2-D8
DDR2-D9
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D14
DDR2-D15
DDR2-D16
DDR2-D17
DDR2-D19
DDR2-D18
DDR2-D22
DDR2-D23
DDR2-D20
DDR2-D21
DDR2-D24
DDR2-D30
DDR2-D26
DDR2-D25
DDR2-D28
DDR2-D31
DDR2-D27
DDR2-D29

0
1
DM
2
3

J1
J3
K1
G4
L3
G3
L2
H5
L1
J5
J2
M3
J4
M2
K5

100p

D1
D5
R3
T5

0
1
2
3
4
5
6
7
A 8
9
10
11
12
13
14

100n
2S25

DDR2-DQM0
DDR2-DQM1
DDR2-DQM2
DDR2-DQM3

MEMORY

0
1 BA
2

100n
2S17

DDR2-BA2

H1
H2
G1

DDR2-BA0
DDR2-BA1

100p
2S20

7S00-8
PNX85500

3S22

B02B

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_022_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 208

Digital video in

PNX85500: Digital video in

B02C

7S00-6
PNX85500
T25
T26

HDMIA-RX1+
HDMIA-RX1-

U25
P
U26
RX1_A
N

P
RX0_A
N

HDMIA-RX0+
HDMIA-RX0-

Y26
SCL
Y25
DDC_A
SDA
V25
P
V26
T24
RX2_A
HOT_PLUG_A
N

HDMIA-RXC+
HDMIA-RXC-

W25
P
W26
RXC_A
N

DDCA-SCL
DDCA-SDA
IS10

IS01

3S0W

W24

RREF

12K
10u

+3V3

HDMI_DV

HDMIA-RX2+
HDMIA-RX2-

RES
2S2E

B02C

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_023_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 209

Audio

PNX85500: Audio

B02D

B02D
3S0Z
+2V5-AUDIO

3S53-1

+24V-AUDIO-POWER
4R7

100R

AD7
AE7
AF7
AD6
AE6
AF6

1
2
3
ADAC
4
5
6

AD9
L
AIN4
AC9
R

2S32

7
1u0
3S10
100R

2S2L
IS1B

1u0

IS19

AE9
L
AIN3
AF9
R

AF8
L
AIN5
AE8
R

1u0

2S41

4R7
2S42

4
IS1S

AB9
POS
VR_AADC
AB8
NEG

AF5

100n

56R

DBS8

AE5

3S3G-3

220n

2S3J

2S2S

10u RES

ADAC(2)

IS03

ADAC(2)

10

7S05-3
LM324 8

3S39

-AUDIO-R

100R
11

ADAC(3)

33R

ADAC(4)

3S36-3

10K

6
5

10K

3S3H

ADAC(5)

33R
3S3U

SPDIF_OUT
SPDIF_IN1

3S36-4
2S2H

47p

ADAC(6)

+24V-AUDIO-VDD

33R

2S3D

3S3F

33R

AE1
1
AF2
VREF_AADC
2
AE3
I2S_OUT_SD 3
AC8
AF3
VCOM_AADC
4

IS1A

3S36-1
2S2G

ADAC(1)
3

3S3G-2
2
7
3S3G-4

AD8

IS07
3

ADAC(5)

7S05-1
LM324

AUDIO-OUT-L

2
11

3S37

3S6L

10K

22K
2S2K

+3V3

47p

+3V3-ARC

+24V-AUDIO-VDD
3S11

IS1L

1R0
5

ADAC(6)

IS06

7S05-2
LM324 7

AUDIO-OUT-R

SPDIF-OUT-PNX

3S6N

14

7S09-1
74LVC00APW
1

IS1D

&

SPDIF-OPT

47R

3
2
+3V3

+3V3

&
6

14

+3V3-ARC
7S09-3
74LVC00APW
9

&
8

5
+3V3

10

2S3L

180R

100n

3S6M

IS1K

2S3M

IS44
eHDMI+

100n
3S25

IS1E

22K
2S2J

+3V3-ARC
7S09-4
74LVC00APW
12

14

SEL-HDMI-ARC

3S32

10K

47p

+3V3-ARC
7S09-2
74LVC00APW
4

3S34

&
11

+3V3

13
7

SPDIF-OUT-PNX

11

14

10u
2S3G

33R

AD4
OSCLK
AD1
SCK
AD2
WS

I2S_OUT

33R

1n0

7
10K

10K

68R

3S17-2

AC6
P
ADACR
AB6
N

IS1Q

AD10
L
AIN2
AC10
R

1 3S3G-1 8
IS1N

1u0

1n0
2S38

1u0
2

3S36-2

47p

1n0
2S39

2S33

3S13-2
22K

8
10K

100n
2S3H

3S17-1

10u
2S3E

AUDIO-IN4-R

22K

2S3F

+AUDIO-L

11

100n

3S13-1

AUDIO-IN4-L

AUDIO
AE10
AC7
L
P
AIN1
ADACL
AF10
AB7
R
N

2S30
1u0

3S38
100R

+24V-AUDIO-VDD
2S36

1n0
2S3A

6
10K

22K
IS1P

7S05-4
LM324 14

13

7S00-2
PNX85500

2S31
1u0

3
3S17-3

IS02

10K

1n0
2S3B

5
10K

4
12

ADAC(1)

100u 4V

3S17-4

2S3Q

22K

1u0

3S13-3

+2V5

2S2Y

10K

AUDIO-IN3-R

IS0R

4S14

IS1M

10K
3S13-4

1u0
IS0V

3S51

3S16-4 5

INH

IS13

COM

1u0

BP

FS03

1u0 RES

2S2Z

100R

10K

IN

2S34

3S16-3 3

OUT

2S2V

5
IS12

3S53-4

7
10K

22K

AUDIO-IN3-L

FS08

1n0
2S3C

100R

2S2T

2
3S16-2

1u0

3S19

AUDIO-IN1-R

IS1J

2 3S12-2

100R
3S53-3

100n

22K

2S2W

2S2R

10u

1 3S16-1 8
10K

IS1H

3S12-1

7S08
LD3985M25

9S06
RES

1
AUDIO-IN1-L

+24V-AUDIO-VDD

+3V3

3S53-2

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_024_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 210

MIPS

PNX85500: MIPS

B02E

B02E
+3V3

7S00-3
PNX85500

CONTROL

+3V3
+3V3

3S80
3S81

10K

RES 3S21
+3V3
10K
3S62

10K
10K

FS10 TXD2-MIPS
FS11 RXD2-MIPS
IS04

GPIO6

PNX-SPI-CS-BLn

+3V3

9S09

GPIO6
PNX-SPI-CS-BLn
BOOST-PWM
SELECT-SAW

5K6

SELECT-SAW

3S55

+3V3

FS64

B25
SDA
A24
SCL

TRSTN
TMS
TCK
TDO
TDI

RESET_SYS
BL_PWM

10K
CLK_54_OUT

3S83
+3V3

RXD1-MIPS

3S60

1
100R

B24
SDA
4
A23
SCL

R26
DN
R25
USB
IS4Z R24 DP
RREF

USB-DM
USB-DP

10K

3S64

1
100R

1 3S5Y 2
100R

1
100R

SDA-UP-MIPS
SCL-UP-MIPS

2 3S5W

SDA-SET
SCL-SET

SDA-SET
SCL-SET

3S6C

4K7

3S5Z

SDA-SSB
SCL-SSB

SDA-SSB
SCL-SSB

3S6E

2K2

3S61

SDA-TUNER
SCL-TUNER

2
1
100R

AA25
AA24
AA23
AB26
AB25

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TDI-PNX85500

3S00

AE4

RES
1F10

3S69

2 3S57

SDA-UP-MIPS
SCL-UP-MIPS

3S6A

SDA-TUNER
SCL-TUNER

4K7

3S6G

4K7
3S6B

4K7

3S6D

2K2

3S6F

2K2

FS44

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDI-PNX85500

FS49
FS50
FS51
FS52

EJTAG-DETECTn

FS53
10 9

1
2
3
4
5
6
7
8

FOR FACTORY
USE ONLY

2K2
3S6K

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TDI-PNX85500

1
10K

8 3S6H-1
10K
3
6 3S6H-3
2
10K
10K

+3V3

FS57

+3V3-STANDBY

BM08B-SRSS-TBT

7 3S6H-2
5 3S6H-4
4
10K

RESET-SYSTEMn

33R

AD5

BACKLIGHT-PWM

AC5
10K

BOOST-PWM

+3V3

IS17

1
100R

3S58
1
2
100R

B26
SDA
2
A25
SCL

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_10
GPIO_11

3S27

3D-LR

DS52

10K
3S82

Y21
IS16 Y22
Y23
Y24
W21
W22
W23
V22
V23
U23

3S56

10K

+3V3

BOOTMODE
3D-LR
RXD1-MIPS
TXD1-MIPS
RXD2-MIPS
TXD2-MIPS

3S6J

10K
3S40

1
100R

C25
SDA
C26
SCL

3S26

BOOTMODE

RES 10K

IS05

3S45
+3V3

10K
+3V3
TXD1-MIPS

3S72

10K

+3V3
IS40
PXCLK54

47R

RES

+3V3
2S89
100n

+3V3

+3V3

7S01
PCA9540B

VDD

SCL-SET

SCL

SDA-SET

SDA

INP
FIL

I2 C
-BUS
CTRL

SC0

SCL-DISP

SC1

SCL-BL

SD0

SDA-DISP

SD1

SDA-BL

SCL-DISP
SCL-BL
SDA-DISP
SDA-BL

3S65

1
4K7
1
4K7
3S67
2
1
4K7
3S68
2
1
4K7
2

3S66

VSS
6

3S84

FS31

9S10
IS08
SCL-SET

IS09

SDA-SET

SCL-BL

9S11

FS2W

SCL-DISP

9S12

FS2Y

SDA-DISP

9S13

SDA-BL

7S00-4
PNX85500

ETHERNET

ETH-RXCLK

AA3

ETH-RXD(0)
ETH-RXD(1)
ETH-RXD(2)
ETH-RXD(3)

Y5
0
Y6
1
RXD ETH
AB4
2
AC1
3

ETH-RXDV
ETH-RXER
SDIO-DAT3
SDIO-CLK
SDIO-CMD
SDIO-DAT0
SDIO-DAT1
SDIO-DAT2
SDIO-CDn
SDIO-WP

IS50

RXCLK

TXCLK

0
1
AC2
TXD
2
RXDV
Y4
RXER
3
ETH
TXEN
W2
CC_DAT3
TXER
W1
COL
CLK
W6
CMD
CRS
W5
0
MDC
W4
SDIO
1 DAT
MDIO
W3
2
U6
SDCD
V6
SDWP

AA2

ETH-TXCLK

AA1
AA4
AB1
AB2
AA5
AB3
AC3
Y2
Y3
Y1

ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)
ETH-TXD(3)
ETH-TXEN
ETH-TXER
ETH-COL
ETH-CRS
ETH-MDC
ETH-MDIO

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

3139 123 6519


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2011-Nov-04 back to

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 211

Video out - LVDS

B02F

PNX85500: Video out - LVDS

B02F

7S00-7
PNX85500
PX1APX1A+

A7
B7

PX1BPX1B+

C8
B8

PX1CLKPX1CLK+

9S90
9S91

N
A
P

LVDS

N
B
P

C10
N
CLK
B10
P

PX1CPX1C+

A9
B9

PX1DPX1D+

N
P

N
P

CLK
LOUT1 LOUT3

D7
E7

PX3APX3A+

E8
D8

PX3BPX3B+

E10
N
D10
P

9S94
9S95

PX3CLKPX3CLK+

N
P

D9
E9

PX3CPX3C+

A11
N
D
B11
P

D11
N
E11
P

PX3DPX3D+

PX1EPX1E+

C12
N
E
B12
P

E12
N
D12
P

PX3EPX3E+

PX2APX2A+

A14
N
A
B14
P

D14
N
E14
P

PX4APX4A+

PX2BPX2B+

C15
N
B15
B
P

E15
N
D15
P

PX4BPX4B+

CLK

E17
N
D17
P

D16
N
E16
P

PX4CPX4C+

D18
N
E18
P

PX4DPX4D+

E19
N
D19
P

PX4EPX4E+

PX2CLKPX2CLK+
PX2CPX2C+
PX2DPX2D+
PX2EPX2E+

9S92
9S93

N
C
P

C17
N
CLK
B17
P
A16
B16 N
C
P
A18
B18 N
D
P
C19
B19 N
E
P

LOUT2 LOUT4

9S96
9S97

PX4CLKPX4CLK+

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_026_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 212

Standby controller

PNX85500: Standby controller

B02G
POL

+1V1

B02G

2S13

100n

1u0
2S10

30R

RES
5S04

IS3B

3S3T
10K

+3V3-STANDBY
3S1H
10K

3S1G

RXD-UP
TXD-UP

10K
3S2A

RXD-UP
TXD-UP
DETECT2

AE21
0
AF21
1
AA22
2
AB22
P3
3
AC22
4
AD22
5

RESET-SYSTEMn
AV2-BLK
AV1-BLK
KEYBOARD
LIGHT-SENSOR
AV1-STATUS
AV2-STATUS

AD23
0
AE26
1
P5
AE25
2
AE24
3

DETECT2

10K
RES
3S1K
10K
RES

RESET-SYSTEMn
3S1J
100K
RES

KEYBOARD
2S4E
100n

3S1L
10K

SPI-PROG

SPI-PROG
PNX-SPI-WPn

AF22
4
P6
AE22
5

AC17

AF26

VDD_XTAL

PSEN
MC

AB23

AC23
SDA
AC24
SCL

AD26
0
PWM AC25
1

3S2F
100R

100R

3S2G

SDA-UP-MIPS
SCL-UP-MIPS

100R

3S2K

3S2H
100R

LED1
LED2

3S44
10K

3S43

IS3D

10K 3S42

10K

PSEN

PSEN

AE23
SDO
AF25
SDI
SPI
AF24
CLK
AF23
CSB
AB17
0
AA18
1
AD18
2
AE18
3
P0
AF18
4
AA19
5
AB19
6
AC19
7

ALE

ALE

AC26

IS3F
IS3E

EA

RES

SDA-UP-MIPS
SCL-UP-MIPS

3S6V
4K7
RES

LED1
LED2

IS2V

CTRL-DISP
RESET-DVBS
RESET-USBn
RESET-ETHERNETn
SEL-HDMI-ARC
RESET-AVPIP
RESET-AUDIO
AUDIO-MUTE-UP

RES

3S41

10K
10K

PNX-SPI-SDO
PNX-SPI-SDI
PNX-SPI-CLK
PNX-SPI-CSBn

IS2Z

3S6W
4K7

3S1P

3S2L

RES
10K
RES 3S3Y
10K

CTRL-DISP
RESET-DVBS
RESET-USBn
RESET-ETHERNETn
SEL-HDMI-ARC
RESET-AVPIP
RESET-AUDIO
AUDIO-MUTE-UP

10K

3S2S
RES
3S3W
4K7

RES
10K
RES
10K

3S46
+3V3-STANDBY

3S47
3S2M
RES
3S49

10K
4K7

+3V3-STANDBY

+3V3-STANDBY

7S20
NCP303LSN28
2

FS45
1

IS2U
5

INP
OUTP
CD

1K0

10K

ALE

EA

1 3S2V 2

RES 3S3S

EA

RESET-STBYn

FS0Z

RESET-STBYn

NC GND
3

10K

AC20
0
AD20
1
AE20
2
AF20
3
AA21
P2
4
AB21
5
AC21
6
AD21
7

AA26
AB24

3S3P

LCD-PWR-ONn
EJTAG-DETECTn
LAMP-ON
STANDBY
FAN-CTRL1
FAN-CTRL2
POWER-OK
ENABLE-3V3n

RESET_IN

STANDBY

+3V3-STANDBY

10p

AF17

100n

10K

LCD-PWR-ONn
EJTAG-DETECTn
LAMP-ON
STANDBY
FAN-CTRL1
FAN-CTRL2
POWER-OK
ENABLE-3V3n

XTAL_OUT

AE17

10p
2S4F

2S4K

3S3M

RES
10K
3S3N RES
10K
3S3Q RES
10K
3S3R
10K RES

2
4
1

9S0E

10K

7S00-9
PNX85500
XTAL_IN

2S4G

RES

3S3L

AD19
0
AE19
1
AF19
2 P1
AA20
3
AB20
7

DS50

9S0D

3S1E
10K
+3V3-STANDBY

10K
3S1D
27K

RC
TACHO
CEC-HDMI
BACKLIGHT-PWM-ANA-DISP
SDM

VDDA_ADC2V5

RES
10K
RES
3S1F

RC
TACHO
CEC-HDMI
BACKLIGHT-PWM-ANA-DISP
SDM

VSS_XTAL

2S4D
1n0

3S1B
3S1C

AD17

+3V3-STANDBY

VDDA_1V1_DCS

AA17

IS20

54M

100n

1S02

9S24

1u0
2S11

RES

2S37

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_027_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 213

Power

PNX85500: Power

B02H

5S80

IS3Q

100n

2S5A

RES 10u

+1V1

2S6A

B02H

30R

5S81

2S5B

RES 10u

100n

2S6B

+2V5
30R

5S82

IS3S

100n

100n
2S68

+3V3

VDD_3V3_SBY

2S5D

2S4M

100n

1
10u

2S4P

100n

2S4N

VSSA_USB

VDDA_2V5_VADC
VDDA_2V5_VDAC
VDDA_3V3_USB

10u

100n
100n

2S4Y

10u

2S50

100n

2S4Z

6.3V
10u

100n

+1V2
30R
c000

SENSE+1V2

Y17
D13
POL

T20
Y13

+2V5-AUDIO

Y10

100n

VDDA_2V5_USB

30R

R21

R20

100n

2S45

+2V5-AUDIO

5S87
+2V5

1u0

2S56

100n

2S55

30R

5S88
30R

10u

100n
2S57

2S5M

+2V5-LVDS

10u

100n
2S58

100n
2S6K

+2V5
30R

2S6H

5S89

5S90
+2V5

10u

100n
100n

2S53

2S4T

30R

2SHW

5S92

1u0

100n
2S59

100n
2S6L

+3V3
30R
2

2S6M

IS58

VDD_1V1_DDR

VSSA_1V1_LVDS_PLL

VDDA_2V5_LVDS_BG

AA7

+2V5

30R

5S84

AA9

2S46

VDDA_2V5_DCS

5S95

Y12

RES 1u0
2S4W

+1V1
IS3L

2S52

VDDA_2V5_ADAC

5S83

B13

2S51

VDDA_2V5_AADC

2S6P

100n

100n
2S6C

Y19
Y18

AA15
Y15
VDDA_1V2
AA13
VDDA_2V5

30R

+3V3-STANDBY

IS3K
VDDA_1V1_LVDS_PLL

+3V3

2
100n
2S6N
1

W20
P20
M20
K20
V7
Y8

100n
1 2S6G 2

5S85

10u
2S4U

VDD_1V1

C7
C9
C11
C14
C16
C18

2S4V

VDD_3V3

+2V5-LVDS

N6
N7

2S6F

VDD_2V5_LVDS

U22

VDD_2V5

220u 6.3V

100n
2S6E 2

U20
U21

2S6D

HDMI_VDDA_2V5

+2V5

30R

HDMI_VDDA_1V1

V20
V21

HDMI_VDDA_3V3_TERM

VSSA_2V5_LVDS_BG

1u0

2S21

100n

2
2S5P
1

VDD

C13

2S29

220u 2.5V

100n

J7

30R

VDD_1V8

A13

100u

2S23

5
100n

100n
2S5H-4
5
100n
2S5J-4
4

7
100n
2S5J-2
2

3
5S94

+1V1

10u
RES

VSS

2S4S

VSS

VSS

M7
N2
N20
P10
P12
P14
P16
P18
P4
P6
P7
T10
T12
T14
T16
T18
T2
T6
T7
U4
V10
V12
V14
V16
V18
V2
Y20

AF1
AE2
AD3
AC4
AB5
H20
F11
G11
F13
G13
F15
G15
F17
G17
F19
G19
J9
J11
J13
J15
J17
L9
L11
L13
L15
L17
N9
N11
N13
N15
N17
R9
R11
R13
R15
R17
U9
U11
U13
U15
U17
J6
AA6
Y7
W7
F9
G9

U24
V24 HDMI_AGND

3
2

8
100n
2S5J-1

100n
2S5J-3

4
3

100n
2S5H-3

8
100n
2S5H-2

6
6

AA16
AA8
Y11
Y14
Y16
Y9

VSS

G14
G16
G18
G2
G20
G8
H4
H6
H7
J20
K10
K12
K14
K16
K18
K2
K6
K7
L20
L4
M10
M12
M14
M16
M18
M6

A1
A10
A12
A15
A17
A19
A26
A3
A8
B1
B20
C20
C4
D2
D20
E13
E20
E4
F10
F12
F14
F16
F18
F20
F8
G10
G12

100n
2S5K-4

100n
2S5K-3

100n
2S5K-2
2

2S5K-1

100n
2S5H-1

100n
2S5G-4

100n
2S5G-3

7
2

100n
2S5G-2

2S5G-1
1

22u

22u
2S4R

100n

2S4Q

100n

2S27

2S28

100n

2S43

+1V1

30R

5S93

L6
L7
R6
R7
U7
A5
A6
B5
B6
C6
D6
E6
F6
G6
F7
G7

7S00-10
PNX85500

VSSA

RES 10u

c001

SENSE+1V1

7S00-12
PNX85500

100n

2S5C

100n
2S67

100n
2S66

100n
2S65

100n
2S64

100n
2S63

100n

2S62

100n
2S61

100u
2S60

2S26

+1V8

SPB SSB
TV550 2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_028_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 214

Analog video

PNX85500: Analog video

B02I
2S87

AV1-CVBS

Y-SVHS

2S8A

3S59

47R

3S5B

22n

56R

47R

22n

Connectivity

3S05

B02I

2S7J

AV1-R

C-SVHS

2S22

3S4J

56R

22n

22n

EU: SCART1

CVBS-MON-OUT1
22n

560R

3S5E

2S7K

AV1-B

56R

3S4L

AP:

3S08

560R

47p

2S7H

2S40

IS4V

22n

8K2

IS4W
3S09

56R

3S4K

AV1-G

2S7M

YPBPR1-SYNCIN1

10n
2S7L
56R

3S4P

AV3-Y

22n

2S7N

AP:

56R

YPBPR1
YPBPR1

3S4R

AV3-PR

EU:

22n
7S00-1
PNX85500

ANALOG_VIDEO

2S7P

AF15
AE15
AC15
AD15

2S8G

AV2-CVBS

9S18

22n

AB14
AF14
AE14
AC14
AD14

2S7R

AV4-Y

SCART2
YPBPR2

22n
9S19

EU:
AP:

AF16
AD16
AE16
AB18
AC18
AF4
AD24
AD25

AF11
AE11
AB10
AA11
AC16
AB16
AB13
AB12
AA12
AA10
AD12
AB11
AE12
AF12

IS5E

3S5S
10K

IS5D
IS5F
IS5G
IS5H
IS5J

3S75
BS15

PNX-IF-AGC

10K

BS10

IS11

3S76

PNX-RF-AGC

47K

9S20

10n

2S76

AA14

2S7U

2S14

BS13

AGND

22n

2S15
22n

AD11
AC11

+CVBS
AV4-PR

2S16
22n

22n

22n

IS5C

2S18
22n

AC12
AF13

2S19

CVBS_Y1 ATV_CVBS_Y3
R
C3
B AV1
CVBS_Y7
G
C7
SYNCIN1
CVBS1_OUT
Y_G1
CVBS2_OUT
PR_R_C1
PB_B1
RESREF
CURREF
CVBS_Y2
SYNCIN2
1
Y_G2
2
PR_R_C2
3
PB_B2
REF
4
5
R
6
G VGA
B
HSYNC_IN
IF_AGC
RF_AGC
IN
VSYNC
OUT
SCL VGA_EDID
P
TUNER N
SDA

10n

AB15
AC13
AD13
AE13

22n

2S75

56R

3S4T

AV3-PB

2S77

PNX-IF-P

10n

2S7E

AV4-PB
9S21

22n

2S78

PNX-IF-N

10n

2S84
56R

3S50

R-VGA
22n

2S85
56R

3S52

G-VGA
22n

2S86

V-SYNC-VGA

3 3S5T-3 6

VGA-SCL-EDID

7
100R

3S5V-2
2

100R

3S5V-4
4

100R

100R

3S5T-1

100R

3S5T-2

H-SYNC-VGA

AP: VGA

22n

3S5T-4

56R

EU: VGA

3S54

B-VGA

100R

VGA-SDA-EDID

3S5V-3
100R
3S5V-1

* 319803104790 - RST SM0402 47R PMS Col R at 9S18 for BRZ

SPB SSB
TV550 2K11 4DDR EU SD

100R

2011-02-01

3139 123 6519


19101_029_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 215

10-23 B03 313912365192


Audio
+AVCC

7D03-1
BC847BS(COL)
6

3D09

+24V-AUDIO-POWER

B03A

+24V-AUDIO-POWER
FD14

Audio

220R

GND-AUDIO

1u0

3
6

3D02-3

7D15-2
BC847BS(COL)
4

4K7

ID19
ID18

2D16
2D17

ID29

ID30

AUDIO-MUTE-UP

2D26
RES

2D22
220n

3D14-1
220n

7
3D14-2
22K
2

3D14-3
22K

5
3D14-4
22K

22K

2D08

R
BSR
R
OUT
L

0
GAIN
1

BSL

16

ID32

2D10

15

5D05
ID06

22u

22
21

5D02

ID10
220n

5D01

ID09
ID31

2D09

22u

ID05

2D12

220R

ID08

35V 220u

5D04

ID07

2D11

220R

RIGHT-SPEAKER

LEFT-SPEAKER

35V 220u

220n

11
7
4
2

1u0

1u0

7D10-1
TPA3123D2PWP

PVCC

CLASS-D
AUDIO AMP

IN

18
17
GND-AUDIO

1
3

AVCC

47n

GND-AUDIO

10
12

2D23

ID15

19
20

2D29

4K7

FD03

3D02-1
1
8

+AUDIO-L

220n

2D19

7D15-1
BC847BS(COL)
1

4K7

ID28

2D07

7 3D02-2 2

47n

ID27

220u 35V

A-PLOP

4K7

1u0
FD08

220u 35V

2D24

ID14

2D20

2D28

3D02-4

FD01

-AUDIO-R

GND-AUDIO

220n

2D05

10u 35V

22K

220R
5D08

5D07

ID12

220n

3D16
ID11

2D06

4R7

VCLAMP
BYPASS
MUTE
SD

ID37

PGND

2D21
220n

3D10-1
220n
1

2D27
RES

7
3D10-2
22K

GND-AUDIO

DETECT2

GND-AUDIO

26
27
28
29

LEFT-SPEAKER

VIA
VIA

VIA

GND-AUDIO

VIA

37
36
35
34

GND-AUDIO

10n

GND-AUDIO

GND-AUDIO

40
39
38

2D03

7D10-2
TPA3123D2PWP

V_NOM
2D14

GND-AUDIO

3D01-4
47K

100p

GND-AUDIO

3D10-3
22K

GND-AUDIO

+3V3-STANDBY
ID35

7D11-2
BC847BS(COL)
4

4n7

ID34

1D50

EMC 4n7
RES 2D31

FD15

3D10-4
22K

CD10

22K

23
24

EMC

RES 2D30

4K7

47K

MAINS SWITCH DETECT

GND_HS

7D11-1
BC847BS(COL)
1

3D15

+3V3-STANDBY

6
6

25

8
9

AGND

13
14

FD09

A-STBY

3D01-3

VIA
1735
30
31
32
33
LEFT-SPEAKER
3

100K

3D06-2

100K

100K

10n

4
RIGHT-SPEAKER
ID33
GND-AUDIO

3D06-4

2041145-3

2041145-4

100K

1
2
3

8 3D06-1 1

RIGHT-SPEAKER

FD02

1D38
1
2
3
4

2D02

V_NOM

3D06-3 FD07

GND-AUDIO

10n
2D13

GND-AUDIO

2D01

220R
3 7D03-2
BC847BS(COL)

FD05
FD06

5D03

1D52

B03A

5
2

10u

SPB SSB TV550


2K11 4DDR EU SD

GND-AUDIO

2011-02-01

3139 123 6519


19101_030_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 216

DC/DC

DC/DC

B03B

B03B

5U03 RES
30R
5U02

FU05

IU22
+12V
1u0

2U20

10u

10u

7 8

IU10

12V/1V8 CONVERSION

3R3

3U11

2U19

2U25

7U02-1
SI4952DY

10u

10u

2U23

2U24

30R

FU02

2U21

5U00

FU03

22u

47u

2U16

47R

2U15

7
47R
3U23-1

3U23-2

3u6

5 6
IU23

1n0

2U17

IU09

47R

7U02-2
SI4952DY

47R
3U23-3

3U23-4

220p

+1V8
IU11

IU15

IU08

5 6 7 8

IU12

3U14
IU07

GND-SIG

20

3U28
GND-SIG

18
19

FU04

1u0

2U05

10u

10K

100n

2U14

RES 100u 2.0V

22u

2U13

IU17

IU25

GND

+1V1

IU18
1u0

2U10

GND-SIG

1n0

2U09

GND-SIG

3U21

FU00

SENSE+1V1

IU19

GND-SIG

2U07

RES 100p

22K

3U10

GND-SIG

FU08

100n

1% 330R
1% 1K0

CU00

5K6

FU09

IU04

3U19

3U22
1K0 1%
3U09

330R 1%

1K0 1%

3U08
+1V8

100p RES

IU20

RES
2U29

3U17
3U18

100R 1%

2U08

10K

V5FILT
VREG5

VIN

7
17

47u

1
2

2U12

TEST

10R
RES

1
TRIP
2

3U20

1
2

+1V1

47R

PGND

22
15

FU01

2u0
47R
3U24-1

1
VFB
2

5U01

FU06

24
13

3U24-2

1
2

47R

SW

12V/1V1 CONVERSION

1
12

47R
3U24-3

1
VO
2

1 2 3

3U24-4

1
2

4
IU14

1n0

IU02

12K

DRVH

5 6 78

IU16

23
14

2U11

3U03

22K
GND-SIG

21
16

1
EN
2

2U06

3U00

3U01

IU01

1
2

2U04

1
2

+3V3-STANDBY

5
8

DRVL

7U04
SI4778DY

6U00

1n0 RES

2U03
IU03

4
9

+1V1
+1V8

1
VBST
2

220p

STPS2L30A

3
10

ENABLE-1V8

3R3

2U01

100n

2
11

IU24

GND-SIG
3U02

3U05

7U03
TPS53126PW

IU13

10R

2U02
100n

7U00
BC847BW

3R3

2U22
IU06

IU05

RES

1 2 3

3R3

10u

2U00

10R

3U04

1n0

3U27

2U18

7U01
SI4778DY

IU21

CU01
CU02
CU03
CU04
CU05

GND-SIG

GND-SIG

GND-SIG

GND-SIG
GND-SIG

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_031_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 217

DC/DC

DC/DC

B03C

B03C

+3V3-STANDBY

+3V3

RES 10K

+5V +3V3-STANDBY

3U75

3U74

RES 10K

LED-2

IU43

RES 10K

3U69

optionally 1M99 is a 9 pin connector

IU44

3U41

IU45
9U42
RES

LED-1

LED2

3U59

LED2

10K RES

10K RES

7U42 RES
BC847BW
IU47

**

7U43
BC847BW

1M99

LED1

3U53

LED1

10K

10K

+12V_AL
3D-LR

100R

100p

BL-SPI-CSn
BL-SPI-CLK

+3V3-STANDBY

3U71

STANDBY

7U48-2
BC857BS(COL)

100R

3U62-4

3U83-2

100K

IU40

100R

FU53

BACKLIGHT-PWM_BL-VS

3U43

BACKLIGHT-BOOST

100R

4U01
FU55

**

4U00

POWER-OK

Items

100p

1n0

10n

2U44

2U45

2U46

100K

3U65

1n0

2U53

1K0
4U00
4U01
1M99
1M95
2U56

+12VD

RES 10K

3U61

10K

10K

DETECT2

22K

FU72

3
5

7U41-2
BC847BS(COL)
8

22K

3U60-4
4

IU50

4K7

IU62

6
10K 1
7U41-1
BC847BS(COL)
1

**

IU55

3U64

3U60-2

IU63

3U62-1

LAMP-ON
3U42

3U62-2

ENABLE-1V8

3U60-1

IU57

ENABLE-3V3n

22K

IU52
3U63

RES 10K

100R

FU73

22K

3K3

3U45

FU51

IU49
6
7U40-1
BC847BPN(COL)

3U73
+3V3-STANDBY

3 3U60-3 6

3U80

2U55

1K0

3U72

10n

IU56

3U62-3

3
+3V3

GND-AUDIO

3U81

10K

GND_AL

100K

IU61

100p
RES

2U49

+24V-AUDIO-POWER

2U50

FU66

1n0
RES

2U58

IU51
T 3.0A 32V

FU76

**

+12V

+12VIN

FU52

+12VIN

1U40

2U54

BZX384-C6V2

10n

1u0 RES

+3V3-STANDBY

6U40

STANDBY-1

FU67
LAMP-ON-1
BACKLIGHT-PWM_BL-VS-1
BACKLIGHT-BOOST-1
POWER-OK-1
FU62
+24V

1-2041145-4

IU48

3U83-3

10n
FU58
FU59
FU60
FU61
FU63
FU75

3
4

1u0
2U47

1
2
3
4
5
6
7
8
9
10
11
12
13
14

7U40-2
BC847BPN(COL)

10K

2U68

1M95

BL-SPI-SDO

RES 100p

100R

RES
3U67
100R
RES
3U84
100R
RES
3U76
MAINS-OK
RES 100R

2U43

RES 100p
2U52

2U51

RES 100p

1n0
2U48

**

2U56

1n0

1-2041145-3

3U66

FU56
FU57
FU74
FU68

BL-SPI-SDO-1
BL-SPI-CSn-1
BL-SPI-CLK-1
MAINS-OK-1
100p RES
2U72

+12VIN

ENABLE-3V3-5V

100K
IU41

100K

FU07

7U48-1
BC857BS(COL)

3U44

FU54

3U83-4

3U83-1

3D-LR-1

10K

+3V3

FU50

FU77
FU78

1K0 RES

3U56

FU49

GND_AL

IU64

3U82

FU48

GND_AL

RES 2U57

3U70

100n

GND_AL

1
2
3
4
5
6
7
8
9
10
11
12
13

+3V3

2U71

10K

3U68

9U41

Optional table for Ambilight


Emmy
( +24V AL)
yes
yes
no
yes
no

Sundance / Infinity
( +12V AL)
no
no
yes
yes
yes

BlockBuster
(For non-Amblight sets)
no
no
no
yes
no

Dream Catcher
Core Range

2U44

3U43

1M95

0R

open

13 POLE

100p

100R

14 POLE

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

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110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 218

DC/DC

B03D

DC/DC
+3V3

B03D

7UC0
LF25ABDT

+12V

IN

OUT

1u0

2UA4

2K2

3UA0

COM

FUA0
+2V5-REF

7UA0
TS2431

FUA4
+2V5

CUA0

IUB6

+2V5-LVDS

+5V-TUN

+3V3

+5V

3U16-1

3UB0

1u0

2UB0

IUA5

22R
4

FUA3

3U15-2
100R
3U15-3
100R
3U15-4

3U16-2
100R
3U16-3
100R
3U16-4

100R

100R

1u0

2UB1

470R

+1V2

+3V3

100R

100R
7UA3
PHD38N02LT

IUB4

2
470R
3UB7-3
3
3UB7-4470R
5
4

3U15-1

IU26

7UA7-1
BC847BS(COL)
3U13

3UB7-2

2UB8

7UA7-2
4
BC847BS(COL)

+5V

2UB2

+1V8

470R

22u

+2V5-REF

7
1K0 IUB2
3UB6-3
3
6
6
1K0
3UB6-4
4
5
1K0
IUB5
3 1

RES 1u0

3UB6-1
1
8
1K0
3UB7-1
8
1

3UB6-2

330R
1%

+12V

7UA6
BC817-25W
3U12
IUB3

330R
1%

+5V5-TUN

NOT FOR 5000 SERIES

ENABLE-1V8
5

+12V

RES
7UA4
TS431AILT

RES

NC

REF

470R

NC

470R
3U26-2

3U26-3
470R
3U26-4

INH

BP

+5V-TUN

IUB1

1
3UB3

RES

470R
+3V3

OUT

COM

1 3U26-1 8 RES

IN

1u0

470R
3U29-4

100n
2UB6

3UB2

2UB5

3 3U29-3 6 RES

IU30

+5V5-TUN

470R

7UA5
LDS3985M50

RES
7U06-1
BC847BS(COL)
1

RES

1u0

+3V3

470R
3U29-2

2UB7

3
RES
7U06-2
BC847BS(COL)
4

3U29-1

4K7

1
3U25-1

RESERVED
5UA0

1K0

30R
1

IU29

SENSE+1V2

4K7

7
3U25-2

IUA6

3U25-3

100K RES

100K RES

3UB1

100K RES

100K RES

3U25-4

3UB5

3UB4

100K

1K0

IUB0

2UB3

+5V
6

RES

22n
2UB4

RES

330p
RES

470R
2

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_033_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 219

DC/DC

DC/DC

B03E
5UD0

IUD0

+12V

33K
1%

68K
3UD1

1%
3UD0

12

22u

IU27

3U06

120K

RES

SW

VIA

10

4n7
3UD2

15

7UD0-2
ST1S10PH

13

IUD6

7U05-1
BC847BS(COL)
RES 1

10K

2UD7

RES 2UE9

100n

+1V1

RES 2U27

SS36

220u 16V

FUD3
+5V

3u6

VFB
GND
P HS

6UD0

IUD7

2UD6

SYNC

5UD1

22u

VIN

IUD3

SW

22u
2UD5

INH

RES 1n0

2UD3

ENABLE-3V3-5V

2UD4

1
A

10u

2UD2

10u

2UD1

10u

2UD0

7UD0-1
ST1S10PH

+5V5-TUN

30R

B03E

14

11

5UD3

IUD1

7U05-2
RES
4

3U07

100n
IU28

RES

33K
1%

12

1M0
3UD5

3UD4

VIA

10

15

IUD2
7UD1-2
ST1S10PH

BC847BS(COL)

10K

RES 2U28

2UE4

22u

22u
2UE3

+1V1

220u 16V

+3V3
3u6

VFB
GND
P HS

FUD2

5UD2

2UE2

SYNC

IUD4

SW

VIN

1% 100K

INH

2UE1

ENABLE-3V3-5V

4n7
3UD3

SW

7UD1-1
ST1S10PH

10u

14

11

7UD2
LD1117DT25
3

IN

S1D

OUT

+2V5

2UE6

100n

2UE5

COM

22u 16V

IUD5

(*) FOR 5000 SERIES ONLY


(**) NOT FOR 5000 SERIES

7UD3
LD1117DT33
IN

OUT

+3V3

100n

COM

22u 16V

2UE8

6UD1
+5V

2UE7

10u

2UD9

10u

2UD8

30R

13

+12V

2UE0

**

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


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110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 220

Temperature sensor & AmbiLight

B03F

Tempsensor + Ambilight

B03F

5UM1

IUM0

1UM0

+3V3
30R

FUM0

V-AMBI

T 1.0A 63V

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


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110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 221

Fan control

Fan Control

B03G
+12V

+12V

1K0

FAN-CTRL1

IUS3 3US5-3
6
3

IUS6

10K

IUT1

100n

2US3

7US1-1
LM339P
14

10K 7

10K

3US7

+12V

3US5-2

10K

3US2

1 3US4-1 8

+3V3

7US2
BC807-25W

12
+12V

IUS7

11
IUT2
FAN-CTRL2

7US1-2
LM339P
13

IUS4 3US5-4
5
4

10

10K

22R

BC807-25W
7US3

IUS8

12

3US6

IUS9
47R

3US3

+12V

10K

3US5-1

3US9

+3V3

10K

FAN-DRV
+3V3

10K

7US1-3
LM339P
2

10K

3US4-3
3

+12V

IUS5

3US4-4

+12V

4
12

TACH01

RES

+12V

10K

+12V
3US4-2

9US0
TACH02

7US1-4
LM339P
1

FUS0

12

B03G

TACHO

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


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110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 222

Vdisp switch

Vdisp-Switch

B03H

1 9UU0-1
RES
2 9UU0-2
RES
3 9UU0-3
RES
4 9UU0-4
RES
1 9UU1-1
RES
2 9UU1-2
RES
3 9UU1-3
RES
4 9UU1-4
RES

7UU0
SI4835DDY

47R
IUU1
3UU0-2
7
2

8
7
6
FUU0

47K RES
2UU1

2
IUU2

1u0

3UU3-2

IUU3
7

47K RES
7UU3 RES
BC847BW

3UU0-1

3UU0-3
+3V3-STANDBY

47K

47K

2
3

7UU2-1
PUMD12
1

47K

22n

2UU2

+VDISP-INT

IUU0

3UU1

IUU4 3UU3-3 IUU5 3UU3-4


6
3
4
5
47K RES

VDISP-SWITCH

2UU0

3UU3-1

FUU1
3UU2

+3V3

47K RES
RES 100n

RES
7UU1
SI3441BDV

+12VD

4
PUMD12
7UU2-2

B03H

+3V3

4K7 RES

LCD-PWR-ONn

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


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110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 223

10-24 B04 313912365192


Analogue externals A

Analogue externals A

B04A
FE70

3E37-4

AP-SCART-OUT-R

IE67

2EA4

AUDIO-OUT-L

8 470R 1
FEA0

7E01-1 6

1n0

2E87

1E00

CDS4C12GTA
12V

RES 6E01

100p

2E01

IEC0

3EA7-1

5 100R 4

1u0 16V
AP-SCART-OUT-L

IEC1
2
1
PUMH7

FEA2

IEC2

3EA7-4

IE68

2EA5

AUDIO-OUT-R

5 470R 4
FEA1

7E01-2 3

1n0

1E31

2E88

RES 6E03

1K0

100p

2E06

RES

FE71

3E07-4

CDS4C12GTA
12V

AUDIO-IN1-R

1u0 16V
AP-SCART-OUT-R

5
4
PUMH7
RES
FE72

3E37-1

AP-SCART-OUT-L

FEA3

1n0

2E90

1E53

3E17
1R0

3EA2
4E02
RES

17
IE17

IE96

18

3E06

5K6

3EB6-1

18p

2E98

39p

18K

2E97

1
2

IE91
8
IE92

7E05
BC847BW

3EB6-4

CVBS-OUT-SC1

470R

4E01
RES

3E45
68R

20

FE85

RES
3E48

1750-821-591-56
GND_A

3E37-2

68R

2 100R 7
3

100p

RES 2E75

3E37-3

1E22

CDS4C12GTA
12V

RES

75R

3E43

6E29

7E09-1
PUMH7

4K7

3E73
39K

1u0

3E18 2

2EB3

3E19

CVBS-MON-OUT1

470R

19

FE84

100n

2E24

4K7

10u

100n

2E74

100p

2E12

16

9E09

21

3E44

5E80

15

9E06

+3V3

FEA7

IE59

+5V

14

FE83

AV1-BLK

1K0

3EA1
2

4E03
RES

13

FE82

1E19

CDS4C12GTA
12V

RES 6E28

RES

2u2

12

9E05

18R

18R

* EU

2EB1

10

FE81

150p

2E86

150p

1u8

2E81

11

5E76 3E79BEC5

FEA6

3EB3

IE08
9E08

IE16

AV1-R

IE70

BC847BPN(COL)

820R
4E04
RES

IE51
AV2-BLK

4p7

9E10
3E78

7E06-1

IE60
1 3EB1 2
1

2E99

IE14

9E55

9E54

9E07

AP

7E06-2

100p

150p

RES
YPBPR1-PR

IE61

3 BC847BPN(COL)

2E14

18R

4E05

FE80

1E18

1u8

4E06

5
6

FE74

CDS4C12GTA
12V

3E77

RES 6E26

5E74

2E84

150p

2E83

FEA5

FE73

FE75
AV1-G

IE89

330R

100p

2E18

1E55

CDS4C12GTA
12V

4K7

3E32
3E76 18R

RES 6E22

YPBPR1-SYNCIN1

9E53

+3V3

IE13

3E31
12K

9E52

9E01

* EU
IE18

AP

IE90

1E01

AV1-STATUS

4K7

2E91

1E54

1n0
100p

150p

RES

(AV1)
2E15

18R

2E80

150p

2E79

IE05

SCART1

1u8

RES 6E23

AV1-B

AV2-STATUS
+5V

100n

3E74 18R

* EU

1E12

5E73 3E75
BEC3

CDS4C12GTA
12V

FEA4

CDS4C12GTA
12V

9E51

RES

9E50

A-PLOP

2K2
RES

1K0 8

100p

2E04

YPBPR1-PB

AP

3E24

3E07-1
1

6E09

AUDIO-IN1-L

CDS4C12GTA
12V

RES 6E07

100p

2E10

8 100R 1

2E85

1X06
EMC HOLE

1X02
REF EMC HOLE

100R
3E07-2
1K0

3E07-3
3E62

1K0 6
3EA7-2

2 470R 7
3EA7-3

100p

RES 6E32

2E44

27R

1E25

FEA8

CDS4C12GTA
12V

AV1-CVBS

3 470R 6

3EB6-2
470R
3EB6-3

470R

GND_A

100p

RES 2E76

1E23

CDS4C12GTA
12V

CVBS-OUT-SC1

RES 6E30

B04A

* 3139803190010 - RSI SM 0402 JUMP 0R05 Col at 2E44 & 2E75 for BRZ

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


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110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 224

Analogue externals B

Analogue externals B

B04B
YPBPR
1E08-3
* GREEN
EU

FE54

MSP-8033SH-02-NI-FE-RF-PBT-BRF

IE71

9E29

4E20

FE5A

3E87

AV3-Y

18R

CDS4C12GTA
12V

RES 6E40

1E43

100p

2E27

AP

3E88

9E04

YPBPR1-SYNCIN1
IE73

AV2-CVBS

27R

GND_A
1E08-2
BLUE
MSP-8033SH-02-NI-FE-RF-PBT-BRF

FE51

EU

GND_A
1E08-1
RED
MSP-8033SH-02-NI-FE-RF-PBT-BRF

IE76

9E58

AV3-PB

3E90

FE5C

AV3-PR

18R

CDS4C12GTA
12V

FE42

FE5B

YPBPR1-PB

EU
RES 6E52

1E39

100p

2E68

3E89
18R

FE48

4E22
RES

IE74

9E57

CDS4C12GTA
12V

RES 6E51

1E28

100p

4E21

2E67

YPBPR1-PR

GND_A

YPBPR AUDIO

+3V3

1E03-1
RED
MSP-8032SH-01-NI-FE-RF-PBT-BRF
2

CDS4C12GTA
12V

FE43

RES
1E32

AUDIO-IN3-R

100p

1K0
2E72

RES 6E06

1E29

1n0

FE50
2E39

1
4E23
RES

FE5D

3E97

AV3-Y
AV1-CVBS

9E15
9E16

RES
RES

AV3-PR
RXD1-MIPS

9E19
9E12

RES
RES

AV3-PB
TXD1-MIPS

9E17
9E14

RES
RES

AUDIO-IN3-R
AV1-B

9E11
9E18

RES
RES

AUDIO-IN3-L
AV1-G

9E13
9E20

RES
RES

CVBS-OUT-SC1
AV1-R

9E21
9E22

RES
RES

AP-SCART-OUT-R
AV1-STATUS
AUDIO-IN1-R
AV1-BLK
AP-SCART-OUT-L
AUDIO-IN1-L

9E23
9E24
9E25
9E26
9E27
9E28

RES
RES
RES
RES
RES
RES

GND_A

GND_A

FE5E

AUDIO-IN3-L

1K0
100p

CDS4C12GTA
12V

3E96

RES 6E38

1E42

1n0

2E40

RES
4E24

FE49

2E71

1E03-2
* WHITE
MSP-8032SH-01-NI-FE-RF-PBT-BRF
4

VGA ( OR DVI ) AUDIO

IE09
AUDIO-IN4-L

1K0
100p

CDS4C12GTA
12V

3E21

RES 6E19

V_NOM

1n0
1E37

2E36

FE02

2E35

1E09
MSJ-035-12D-B-AG-PBT-BRF
2
3
1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32

31

DF50-30DP

FE01

AUDIO-IN4-R

100p

1K0
2E38

CDS4C12GTA
12V

RES 6E20

V_NOM

1n0
1E38

2E37

IE10

3E20

FE03

1E10
3150-831-030-H1
2
VCC

1R0

SPDIF-OPT

CDS4C12GTA
12V

RES 6E53

V_NOM

100p
1E80

RES 2E77

GND
MT
7 6 5 4

FE55

100n

VIN

3E9C

+3V3

2E73

B04B

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

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110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 225

Ethernet & Service

Ethernet & Service

B04C

IE07

5E08
+3V3

+3V3-ET-ANA
IE49

3E53-2

RXD1-MIPS
+3V3-ET-ANA

IE50

3E53-3
47R

+3V3

6E43
IE38

3E30

FE57

1E06

2
3
1

UART
SERVICE
CONNECTOR

47R

MSJ-035-69A-B-RF-PBT-BRF
FE58

ETH-TXD(3)
ETH-TXER

10u

2E48

100n

2E49

12

RES
6E48
100n

10K

3E68
RES
3E35
RES

3E34

2
10K

3E72

ETH-REGOFF

10K

+3V3
ETH-INTSEL

10K

+3V3
ETH-CRS

RXD1-MIPS

VSS
14

33
7E10-2
LAN8710A-EZK
TXD-UP
VIA

10K

RES
7E11-3
74HC4066PW
8

40
41
42

VIA

AV2-BLK

X1
7

34
35
36

RES
7E13
PDTC144EU

RES
7E12
PDTC144EU

X1
IE39

+3V3

RES
7E11-2
74HC4066PW
4

32

MDC
MDIO

13

X1

9E42

14

+3V3

RES

RXD-UP

ETH-RXCLK

10K

RES
3E9E

RES

RES
7E11-1
74HC4066PW
1

10K

+3V3

RES
3E9D

IE64

14

ETH-RXER

10K

3E65

CRS

ETH-RXDV

IE63

REGOFF
1
LED
2
INTSEL

RES
2E69

ETH-TXCLK

3E64

RBIAS

17
16

ETH-MDC
ETH-MDIO

20

13

RXER
RXD4
0
PHYAD
1
RXCLK

0
1
2 TXD
3
4
INT
TXER

ETH-TXP
ETH-TXN

26

RXDV

TXEN

29
28

502382-0370

22
23
24
25
18

P
N

ETH-RXP
ETH-RXN

14

ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)

TX

31
30

1
2
3

TXD
RXD

21

P
N

TXCLK

COL
CRS_DV
MODE2

+3V3

ETH-TXEN

RX

12K1
1%

15
10K
10K

27

0
MODE
1
RMIISEL
PHYAD2
RXD<0:3>

RES
1E71

IO

RST

10K

RES 3E71
RES 3E80

1A 2A
VDD

3E40

10p
19

1K5

4n7

100n
2E53

CLKIN
1
XTAL
2

11
10
9
8

3E51

10p

2E54
2E55

10p

RES
RES
RES
RES

7E10-1
LAN8710A-EZK

CR

ETH-RXD(0)
ETH-RXD(1)
ETH-RXD(2)
ETH-RXD(3)

3E70
RES

FE56

PROVISION FOR iTV

5
4

ETH-COL

+3V3

25M

RES 2E70

47R
3E53-4

BAS316

3E33

3E66
3E67
3E81
3E82

1M0
1E70
NX3225GA

3E69
RES
10K

IE06

3E53-1

IE33
2E52

10K
10K
10K
10K

10K

IE32

IE26

+3V3

RESET-ETHERNETn

47R

1E86

1E85

TXD1-MIPS

BZX384-C5V1

100n

100n
2E66

2E62

10u
2E63

30R

BZX384-C5V1
6E44

B04C

37
38
39

14

VIA

TXD1-MIPS

10

RES
7E11-4
74HC4066PW
11

12

X1

CONFIGURATION RESISTOR SETTINGS

+3V3-ET-ANA

+3V3-ET-ANA

ETHERNET CONNECTOR
ETH-TXP

FE27

1E87
3 ACM2012 2

ETH-TXN

FE28

ETH-RXP

FE29

1E88
3 ACM2012 2

ETH-RXN

FE31

1N00
FE60

1
FE30
FE61

22n

9 11
10 12
2E60

5
4

CDA5C16GTH
16V

6E47-4

CDA5C16GTH
16V
RES

6
6E47-3
3

7
2

CDA5C16GTH
16V
RES

6E47-2

8
1

6E47-1

RES
RES

FE34

5450-323-183-H3

15p

2E59

5E04

RES 27n

CDA5C16GTH
16V
RES

1
2
3
4
5
6
7
8

RES 15p

2E09
15p
3E39

0 ohm

RES

RES 27n

5E03
2E08

RES 15p
2E58
RES

0 ohm

15p

3E29

2E57
RES

RES

RES 27n

5E02
2E07

RES 15p
0 ohm

15p

3E28

2E56
RES

RES

RES 27n

5E01
2E05

RES 15p
0 ohm

3E27

RES

POP

EMPTY

22R

22R
3E98

3E26

3E99

49R9
1%

3E95

49R9
1%

3E25

49R9
1%

3E22

49R9
1%

Resistor

FE32

3E64 (RES)

PHYADD(0) = 1

PHYADD(0) = 0

3E65 (RES)

PHYADD(1) = 1

PHYADD(1) = 0

3E66 (RES)

PHYADD(2) = 1

PHYADD(2) = 0

3E67 (RES)

RMII mode selected

MII mode selected

3E68 (RES)

Internal 1.2V reg. disabled

Internal 1.2V reg. enabled

3E69 (RES)

MODE(0) = 0

MODE(0) = 1

3E70 (RES)

MODE(1) = 0

MODE(1) = 1

3E71 (RES)

MODE(2) = 0

MODE(2) = 1

3E72

INTERRUPT FUNCTION

INTERRUPT FUNCTION

DISABLED ON

ENABLED ON

nINT/TXER/TXD4 SIGNAL

nINT/TXER/TXD4 SIGNAL

ETH-INTSEL
ETH-REGOFF

FE33

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_040_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 226

HDMI

I2C Address

ARX2+

MICOM-VCC33

1u0

10u

2ECV

100n

FEC3

3ECH

ARX1ARX0+

BRX2+
BRX2BRX1+
BRX1BRX0+

BIN-5V

ARXCARXC+

65
66

ARX0ARX0+

67
68

ARX1ARX1+

69
70

ARX2ARX2+

71
72

BRX-HOTPLUG

47K

3ECM-3

2
3ECN-2

10R

7
100K
1u0

BRX-DDC-SDA
BRX-DDC-SCL

IE43

35
36
33
34

2ECN

N
R0XC
P

FECC
FECD

BRX-DDC-SCL
BRX-DDC-SDA

FECE
FECF

BIN-5V
47K

BRX-HOTPLUG

20
22

3ECA-1

BRX-DDC-SCL
BRX-DDC-SDA

BIN-5V

HDMI CONNECTOR 1

CIN-5V

3ECM-2

3
3ECN-3

10R

CRX-DDC-SDA
CRX-DDC-SCL

CRX2+

1u0

CRX2CRX1+
CRX1CRX0+

CIN-5V

PCEC-HDMI

47K

3E23
RES
7E02
BC847BW

100R

IEC4

3ECM-1

10R

1u0

DRX-DDC-SDA
DRX-DDC-SCL
5EC2

eHDMI+

30R
ARC-eHDMI+
2ECC

CIN-5V

7EC0
BC847BW

3ECD

+3V3-STANDBY

22K
RES

DIN-5V

4
3ECN-4

10p

20
22

47K

CRX-HOTPLUG

3ECA-3

CIN-5V

FECM
FECN

BRX0BRX0+

3
4

BRX1BRX1+

5
6

BRX2BRX2+

7
8

6
100K

IE44

41
42
39
40

2ECP

CRXCCRXC+

11
12

CRX0CRX0+

13
14

CRX1CRX1+

15
16

CRX2CRX2+

17
18

DRX-HOTPLUG

CRX-DDC-SCL
CRX-DDC-SDA
6

FECK
FECL

3ECA-4

FECA

CRXCPCEC-HDMI
ARC-eHDMI+
CRX-DDC-SCL
CRX-DDC-SDA

FECJ

CRX0CRXC+

1
2

CRX-HOTPLUG

1P02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
23

BRXCBRXC+

5
100K

IE45

2ECQ

45
46
43
44

DRXCDRXC+

19
20

DRX0DRX0+

21
22

DRX1DRX1+

23
24

DRX2DRX2+

25
26

IEC6
9EC0

CEC-HDMI

IEC5

100n

CEC_D

49

DSCL4
DSDA4

N
R0X0
P

2EC3

38

10K

37

9
27
64

R4PWR5V

48
47

VGA-SCL-EDID-HDMI
VGA-SDA-EDID-HDMI

51

9EC2
RES

CEC-HDMI

N
R0X1
P
N
R0X2
P
TX2

(CBUS) HPD1
R1PWR5V
DSDA1
DSCL1
N
R1XC
P
N
R1X0
P

N
P

TX1

N
P

TX0

N
P

TXC

N
P

3ECA-2

BRXCPCEC-HDMI

BIN-5V

BRX0BRXC+

DSDA0
DSCL0

+5V-EDID

29
30

(CBUS) HPD0
R0PWR5V

57
56

HDMIA-RX2HDMIA-RX2+

59
58

HDMIA-RX1HDMIA-RX1+

61
60

HDMIA-RX0HDMIA-RX0+

63
62

HDMIA-RXCHDMIA-RXC+
3ECJ RES

N
R1X1
P

TPWR_CI2CA

N
R1X2
P

CEC_A

(CBUS) HPD2
R2PWR5V

INT

55

50

52

4K7
IE12
FECR

RES
3ECK

MICOM-VCC33

4K7
9EC3
RES

FECY

PCEC-HDMI
3ECL RES

+3V3

4K7

DSDA2
DSCL2
N
R2XC
P

CSCL
CSDA

N
R2X0
P
RSVDL

N
R2X1
P

54
53

10
28

N
R2X2
P
(CBUS) HPD3
R3PWR5V
DSDA3
DSCL3
N
R3XC
P
VIA

N
R3X0
P
N
R3X1
P
N
R3X2
P

3EC3
3EC5

100R
100R

SCL-SSB
SDA-SSB

10p

AIN-5V

HDMI CONNECTOR 2

2ECM

31
32

10K
3ECP-3

1u0

IE42

3ECP-1

10R
ARX-DDC-SDA
ARX-DDC-SCL

8
100K

1
3ECN-1

30R

10p
RES 2ECY

RES 2ECX

AIN-5V

3ECM-4

SBVCC33

MICOM_VCC33

1
47K

3EC1-1

ARX-HOTPLUG

ARX-HOTPLUG

10u

RES 2ECW

100n

100n
2EC8

VCC33

AIN-5V

20
22

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FECG 21
23

100n
2EC7

2EC6
6
47K

3EC1-3
3

7EC1
SII9187B

ARX-DDC-SCL
ARX-DDC-SDA

FEC4
FEC5

+3V3

+3V3-HDMI

ARXCPCEC-HDMI
ARX-DDC-SCL
ARX-DDC-SDA

RES
5EC3

FEC7

AIN-5V

ARX0ARXC+

FEC1
FEC2

B04D

SII9187B = 0xB2

FECB

ARX2ARX1+

1P03

74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89

73

EPAD

3ECE

22K

IEC7
FECW
+3V3-STANDBY

6EC1
+5V

+5V-VGA

7EC1

3ECN

3ECF

NON-INSTAPORT

9187B

4X 100K

100K

BLOCKBUSTER

INSTAPORT

9287B

4X 100K

100K

SUNDANCE

BAT54
IE11

3ECG
3ECF

4R7

FECP

2EC0

HDMI CONNECTOR 3
1P04
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FEC6 21
23

30R
220u 16V

+3V3

FEC0

10K

5EC0

2EC2

HDMI
RES 2EC1

B04D

FECZ

100K

DDCA-SDA

IE65

3ECU-2

+3V3

10K
2ECU

DDCA-SCL

IE66

4 3ECU-4 5
10K

1u0
2

SPB SSB TV550


2K11 4DDR EU SD

+5V-EDID

2011-02-01

3139 123 6519


19101_041_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 227

Headphone

Headphone

B04E

+3V3-STANDBY

4
PUMD12
7EE0-2
A-PLOP
3

A-STBY

FEE0
2

RESET-AUDIO

7EE0-1
PUMD12
1

2EE0

22K

3EE1-3

3EE1-4

22K

3EE1-2

22K

47p
3EE1-1

22K
2EE5

7EE1
TPA6111A2DGN

100n

2EE1

47p +3V3

IEE2
ADAC(4)

2EE3
1u0

IEE1
2EE4
1u0

3EE0-1
10K

IEE3
1

2
5

3EE0-4

10K

6
IEE4

5
2EE2

AMPLIFIER

3 3EE0-3 6

2EE6

IEE7

33R
3EE2-4

6
FE36
5

VO

SHUTDOWN
BYPASS

VIA
GND GND_HS

7
10
11

2EE7

AMP1

33R

4V 100u

3EE2-3

IEE8

4V 100u
1

3EE2-2
33R
3EE2-1

FE35
7

AMP2

33R

IEE5

10K
22K

A-PLOP

IN-

1u0

IEE6

VDD

IEE0
ADAC(3)

RES 3EE3

B04E

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_042_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 228

10-25 B05 313912365192


DDR

C8
C2
3
D7
D3
1
D1
D9 3B00-4 4
B1
B9 3B00-1 1

NU|RDQS

2
6 3B02-3
33R 3
8 3B02-1
33R 2
3B02-2
5
3B02-4
4
33R
8
33R

B7
A8

3B00-2

7
33R
6 3B00-3
33R
7
33R
5
33R

3B12
33R

3B13
2B44
RES

0
1 BA
2

2p2

DDR2-D16
DDR2-D17
DDR2-D18
DDR2-D19
DDR2-D20
DDR2-D21
DDR2-D22
DDR2-D23

DDR2-DQS2_P
DDR2-DQS2_N

33R

A2

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

G2
G3
G1

DDR2-BA0
DDR2-BA1
DDR2-BA2

DDR2-ODT

ODT

3B03

CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

NC

L3
L7

DDR2-A14

VSSQ

VSSDL

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM3

F9
E8
F8
F2
G8
F7
G7
F3
B3

RES
240R

3B24
33R

2B17
100n
2B37
100p
VDD

VDDL

VDDQ

E2

A9
C1
C3
C7
C9

E1

A1
E9
L1
H9

100n

100n
2B16

100n
2B15

100n
2B14

100n
2B13

100n
2B12

100n
2B11

100n
2B10

47u
2B09

E2

A9
C1
C3
C7
C9

E1

DQS

A3
E3
J1
K9

33R

DQ

0
1
2
3
4
5
6
7

B05A

VREF

0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

SDRAM
DQ

0
1
2
3
4
5
6
7

DQS

C8
C2
3B05-3
3B04-3
D7
D3
D1
D93B04-4
B1
B93B04-1

3
3

4
1

B7
A8
2B45

0
1 BA
2

NU|RDQS

3B04-2
2
7
33R
6
6 33R
33R 2
7 3B05-2
33R
1
8 3B05-1
33R
5
5 3B05-4
4
33R
33R
8
33R

3B15
RES
2p2

3B14
33R

DDR2-D24
DDR2-D25
DDR2-D26
DDR2-D27
DDR2-D28
DDR2-D29
DDR2-D30
DDR2-D31

DDR2-DQS3_P
DDR2-DQS3_N

33R

A2

ODT
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

+1V8

NC

L3
L7

DDR2-A14

VSSQ

VSSDL

A7
B2
B8
D2
D8

3B23

SDRAM

DDR2-VREF-DDR

E7

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM2

F9
E8
F8
F2
G8
F7
G7
F3
B3

7B03
EDE1108AGBG-1J-F

VREF

VDDQ

A3
E3
J1
K9

RES
240R

3B01

2B41

2B36
100p
2B08
100n

DDR2-ODT

VDDL

A7
B2
B8
D2
D8

DDR2-BA2

VDD
0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

E7

G2
G3
G1

DDR2-BA0
DDR2-BA1

+1V8
DDR2-VREF-DDR

2B35
100n
2B39
100p

100n

100n
2B34

100n
2B33

100n
2B32

100n
2B31

100n
2B30

100n
2B29

100n
2B28

47u
2B27

2B43

100n

2B26
100n
2B38
100p

DDR2-VREF-DDR

100n
2B25

3B25
33R

DQS

B7
A8
2B46

0
1 BA
2

NU|RDQS

3B17
RES
2p2

3
1
3

3B16
33R

DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D4
DDR2-D5
DDR2-D6
DDR2-D7

DDR2-DQS0_P
DDR2-DQS0_N

33R

A2

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

G2
G3
G1

DDR2-BA0
DDR2-BA1
DDR2-BA2

DDR2-ODT

ODT

3B09

CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

NC

VSSDL

VSSQ

L3
L7

DDR2-A14

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM1

RES
240R

3B26
33R

F9
E8
F8
F2
G8
F7
G7
F3
B3

VDD

VDDQ

E2

A9
C1
C3
C7
C9

E1
VDDL

VREF

0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

SDRAM
DQ

0
1
2
3
4
5
6
7

DQS

C8
3B11-3 3
C2
D7
3B10-3 33R 3
D3
D1
D93B10-4 4
B1
B9 3B10-1 1

B7
A8
2B47

0
1 BA
2

NU|RDQS

6
6 33R

2 3B10-2 7
33R

2
1
5 3B11-1
4
33R
8
33R

3B19
RES
2p2

7 3B11-2
8 33R
33R
5 3B11-4
33R

3B18
33R

DDR2-D8
DDR2-D14
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D9
DDR2-D15

180R 1%

7
33R
6 3B07-3
33R
8 3B08-1
33R
6 3B08-3
33R

FB00
DDR2-VREF-DDR

180R 1%

5
33R
7
33R
5
33R
8
33R

3B07-2

3B20

3B21

DQ

0
1
2
3
4
5
6
7

C8
C23B08-4 4
D7
D3 3B08-2 2
D1
D9 3B07-4 4
B1
B9 3B07-1 1

A1
E9
L1
H9

E2

E1

SDRAM

DDR2-DQS1_P
DDR2-DQS1_N

33R

A2

ODT
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

NC

VSSDL

L3
L7

DDR2-A14

VSSQ

1X20
HOOK1

A7
B2
B8
D2
D8

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM0

F9
E8
F8
F2
G8
F7
G7
F3
B3

7B01
EDE1108AGBG-1J-F

VREF

E7

RES
240R

3B06

VDDQ

A3
E3
J1
K9

DDR2-BA2

DDR2-ODT

VDDL

A7
B2
B8
D2
D8

G2
G3
G1

DDR2-BA0
DDR2-BA1

VDD
0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

E7

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

A1
E9
L1
H9

7B00
EDE1108AGBG-1J-F
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

A9
C1
C3
C7
C9

+1V8

A3
E3
J1
K9

DDR2-CLK_P
DDR2-CLK_N

100n
2B24

240R

100n
2B23

3B28

100n
2B22

DDR2-CLK_N

100n
2B21

DDR2-CLK_P

100n
2B20

3B27
240R

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

100n
2B19

DDR2-CLK_P
DDR2-CLK_N

47u
2B18

3B22
240R

2B42

AT T-POINT

A1
E9
L1
H9

7B02
EDE1108AGBG-1J-F
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

+1V8

DDR2-VREF-DDR

100n

100n
2B07

100n
2B06

100n
2B05

100n
2B04

100n
2B03

100n
2B02

+1V8

100n
2B01

47u
2B00

2B40

B05A

DDR

1X21
HOOK1

1X22
HOOK1

1X24
HOOK1

1X23
HOOK1

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_043_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 229

10-26 B06 313912365192


Display interfacing-Vdisp

Display interfacing-Vdisp

B06A

1G03
T 3.0A 32V

5G01

FG0H

1G00

+VDISP-INT
100n

T 3.0A 32V
RES

2G43

+VDISP
30R
RES
5G02

22u
RES

30R
RES
2G44

B06A

3G28
2K2

IG11

6G00
LTST-C190KGKT

For Development use only

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_044_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 230

Video out - LVDS

B06B

Video out - LVDS

B06B

2G94

100n

FG2J

2G95

100n

FG30
FG31
FG32
FG33

FG11
FG1J

PX3DPX3D+
PX3EPX3E+

FG1K
FG1L
FG1M
FG1N

PX4APX4A+
PX4BPX4B+
PX4CPX4C+

FG12
FG13
FG14

PX4CLKPX4CLK+
PX4DPX4D+
PX4EPX4E+

FG15
FG16
FG17
FG18
FG19
FG1A
FG1B
FG1Q
FG1P

47p

47p

47p

2G25

2G27

2G24

2G26

47p

47p

2G7A

47p

47p
2G79

47p

2G75

2G76

2G78

47p

47p

1n0
2G9B

2G77

1n0

10K
3G35

FG34
FG2H
FG2G

CTRL-DISP
BACKLIGHT-BOOST
3D-LR
3D-VS-DISP
CTRL-DISP
CTRL-DISP
3D-LR-DISP

3G38
3G37
3G2Z
3G36
RES 3G30
RES 3G31
3G39

100R
100R
100R
100R
100R
100R
100R

FG35
FG2R
FG2K

FG04

FG2L
FG2M

PX1APX1A+
PX1BPX1B+
PX1CPX1C+

FG2E
FG2F
FG1Y
FG1Z
FG20
FG21

PX1CLKPX1CLK+

FG22
FG23

PX1DPX1D+
PX1EPX1E+

FG24
FG25
FG26
FG27

PX2APX2A+
PX2BPX2B+
PX2CPX2C+

FG28
FG29
FG2A
FG2B
FG2C
FG2D

PX2CLKPX2CLK+

FG1R
FG1S

PX2DPX2D+
PX2EPX2E+

FG1T
FG1U
FG1W
FG1V

2G28
2G29

47p
47p

FG2P

RES 9G0G

FG2N

+VDISP

1G50

TO DISPLAY

EMC 100n
RES 2G9C

PX3CLKPX3CLK+

FG1C
FG1D
FG1E
FG1F
FG1G
FG1H

100R
100R
100R

EMC 100n
RES 2G9E

PX3APX3A+
PX3BPX3B+
PX3CPX3C+

47p
47p
47p
47p

RES 3G32
3G2W
3G2Y

EMC
RES 2G9F

2G96
2G99
2G97
2G98

41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

CTRL-DISP

100n

100n

SDA-DISP
SCL-DISP

100n

2G93

FI-RE41S-HF
50
51
48
49
46
47
44
45
42
43

2G91

100n

EMC 100n
RES 2G9D

2G92

FI-RE51S-HF
60 61
58 59
56 57
54 55
52 53

4
3
2
1

9G0K-4
9G0K-3
9G0K-2
9G0K-1

5
6
7
8

3G33

RES

2G9A

10K

10K

+VDISP

3G34

+3V3

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

1G51

TO DISPLAY

1X05
REF EMC HOLE

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_045_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 231

AmbiLight CPLD

AmbiLight CPLD

B06C

B06C

5GA0

FGA0

+3V3

VINT

5GA1

100n

100n
2GA2

2GA1

1u0

2GA0

30R

DEBUG ONLY

FGA1

+3V3

VIO

+3V3

100n

10K
RES

IGA2

IXO4_19
IXO4_20
IXO4_21
IXO4_22
IXO4_23
IXO4_27
IXO4_28

IXO2_29
IXO2_30
IXO2_31
IXO2_32
IXO2_37
IXO2_38

IGA1

19
20
21
22
23
27
28

TCK
TDI
TDO
TMS

PNX-SPI-CSBn
BACKLIGHT-PWM
3D-LR
3D-VS-DISP
BL-SPI-SDO
BL-SPI-SDI
BL-SPI-CSn
BACKLIGHT-PWM_BL-VS
BL-SPI-CLK

9GA1 RES

3GA1

4
3G10-4
2
3G10-2
3G12
3
3G11-3

RES
47R
5
3
33R
7 3G10-3
33R
3G13
10R
1
6 3G10-1
33R

IGA3
GCK2
+3V3
3

+3V3

AMBI-PROG_B1
AMBI-BLANK_R1

6
33R

AMBI-SPI-CS-EXTLAMPSn
AMBI-SPI-CLK-OUT
AMBI-SPI-SDI-OUT_G1
AMBI-SPI-SDO-OUT
AMBI-LATCH2_DIS

33R
8
33R

3
RES
7GA2-2
BC847BS(COL)
4

GTS2

4
17
25

+3V3

RES
3GA6-3

6 330R 3

5 330R 4

RES
3GA6-4

RES
3GA6-1

8 330R 1

RES
3GA6-2

LTST-C190KGKT

100n

2GA4

SD51022

RES
6GA3

LTST-C190KGKT

FGA3
+3V3

RES
6GA2

FGA5
FGA2

LTST-C190KGKT

FGA4

RES
6GA1

FGA6

1
2
3
4
5
6

LTST-C190KGKT

100R
100R
100R
100R

RES
6GA0

8
7
6
5

6
RES
7GA2-1
BC847BS(COL)
1

7 330R 2

RES
1G36
1
2
3
4

6
RES
7GA1-1
BC847BS(COL)
1

GTS1

+3V3

DEBUG ONLY
3GA2-1
3GA2-2
3GA2-3
3GA2-4

RES
7GA1-2
BC847BS(COL)
4

GCK3

GND

RES
1G35

5
6 100R
7 100R
8 100R
100R

CPLED2

GSR

RES
RES
RES
RES

4
3
2
1

26

IXO2_36|GTS1
IXO2_34|GTS2
IXO2_33|GSR

+3V3

1
2
3
4
5
6

3GA5-4
3GA5-3
3GA5-2
3GA5-1

CPLED3
5
6
7
8
12
13
14
16
18

10p

11
9
24
10

RES
RES
RES
RES

SD51022

10p
2G19

29
30
31
32
37
38

IXO3_5
IXO3_6
IXO3_7
IXO3_8
IXO3_12
IXO3_13
IXO3_14
IXO3_16
IXO3_18

10p
2G18

33R
2
33R

10p

10p
2G12

10p
2G11

10K

2G10

3G14
1
33R
7
3G11-2

8
3G11-1

IXO1_2
IXO1_3
IXO1_39
IXO1_40
IXO1_41
IXO1_42

10p
2G16

36
34
33

GTS1
GTS2
GSR
AMBI-SPI-CS-OUTn_R2-R
AMBI-PWM-CLK_B2
AMBI-SPI-CS-OUTn_R2
AMBI-LATCH1_G2
AMBI-TEMP
CPLED3
CPLED2

3G15

33R

GCK3
GTS1
GTS2
GSR

AMBI-SPI-CLK-OUT-R
AMBI-SPI-SDI-OUT_G1-R
AMBI-SPI-SDO-OUT-R

10p
2G15

3GA3

VCCIO

10p
2G14

PNX-SPI-CS-BLn
PNX-SPI-SDO
PNX-SPI-SDI
PNX-SPI-CLK

2
3
39
40
41
42

VCCINT
IXO1_43|GCK1
IXO1_44|GCK2
IXO1_1|GCK3

2G13

43
44
1

15
35

7GA0
XC9572XL-10VQG44C0100
PXCLK54
GCK2
GCK3

VIO

1
2
3
4
5
6

+3V3

10p
RES

VINT

2GA6

3GA4

RES
1G37

10p
2G17

2GA5

1u0

2GA3

30R

BACKLIGHT-PWM

9GA0

BACKLIGHT-PWM_BL-VS

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_046_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 232

SPI buffer

SPI-Buffer

B06D

RESERVED

+3V3

20
3EN1
3EN2
G3
PNX-SPI-CLK

PNX-SPI-SDO

RES
7GE0
74LVC245A
1

1
2

17
16
15
14
13
12
11

RES
7GE1
PDTC114EU

PNX-SPI-CSBn

IGE0

19
2

RES 3GE0-3 3

6 47R

3
4
5
6
7
8
9

RES
RES
RES
RES
RES

8 47R
1 47R
4 47R
47R
47R

3GE0-1 1
3GE1-1 8
3GE1-4 5
3GE3
3GE4

BL-SPI-CLK
BL-SPI-SDO
AMBI-SPI-CLK-OUT-R
AMBI-SPI-SDO-OUT-R
PNX-SPI-SDI

10

AMBI-SPI-SDI-OUT_G1-R
BL-SPI-SDI

18

10K

100n

RES
3GE2

+3V3

RES
2GE0

B06D

PNX-SPI-CLK

RES 8

9GE0-1

BL-SPI-CLK

PNX-SPI-SDO

RES 6

9GE0-3

BL-SPI-SDO

BL-SPI-SDI

RES

9GE1

RES

9GE2

PNX-SPI-CS-BLn

IGE1

RES 5 9GE0-4

PNX-SPI-SDI

*
** 4

BL-SPI-CSn

Buffer

*
**

Direct

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_047_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 233

10-27 B07 313912365192


DVBS-FE

B07A

DVBS-FE

B07A
7R01-1

STV0903BAC

100n

10n

2R15

100n

2R14

10n

2R09

+3V3-DVBS

+3V3-DEMOD

+3V3-DEMOD

10n

10n

2R52

10n

2R51

100n

2R50

100n

2R49

100n

2R48

2R47

100n

2R46

22u

2R16

30R

VIA

VDD3V3

2
3
100n

2R17

+1V-DVBS

VDDA2V5

60
56
RES 2R21

DISECQ-DET
F22-DISECQ-TX

128
20
126
NC
107
NC
IR04
47p
97
98
3R00 IR03
19
18

1n0

RES 2R22
SCL-SSB
SDA-SSB

100R
RES 2R23

3R01
47p
100R

SCLT
SDAT

RESET-DVBS
9R00
RES

3R11
+3V3-DVBS
10K

IR02

62
58
26
23
24
29
27

FR02
FR03
FR04
FR05
FR06

FR07

XTALO

VS
AGCRF1

I2C-ADDRESS : D0
DIRCLK
CLKI
CLKI2
CLKOUT27
N
I1
P

N
Q1
P

0
1
2
3
D
4
5
6
7
CLKOUT
STROUT
DPN
ERROR

0
CS
1
DISEQCIN1
DISEQCOUT1
FSKRX_IN
FSKRX_OUT
NC
SCL
SDA
SCLT
1
SDAT

RESETB
STDBY
TCK
TDI
TDO
TMS
TRST

COMP

0
1

1
2
3
4
5
6
GPIO 7
8
9
10
11
12
13

52

SENSE+1V0-DVBS

63
64
65
67
68
70
71
73
74
75
78
79
82
83
84
86
87
89
90
91
94
95
108
109
111
115
116
119
120

AGC

2R53

1K0

47n

* To be drawn near PNX85500


3R03
3R04
3R05
3R06

47R
47R
47R
47R

NC

NC
NC
NC

TS-DVBS-DATA 4
TS-DVBS-CLOCK
TS-DVBS-SOP 2
TS-DVBS-VALID 1

9R03-4 * 5
9R04 *
9R03-2 * 7
9R03-1 * 8

TS-FE-DATA
TS-FE-CLOCK
TS-FE-SOP
TS-FE-VALID

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

40
41
101
50
49
47
46
44
43
37
35
34
32
30
55

FR00

3R02

16

6p8

8
7

IM
IP

MAIN

XTALI

IR05

3R07
120K
DISECQ-RX

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

100n

2R26

100n

2R25

100n

2R24

100n

100n

2R19

+2V5-DVBS
2R18

VDDA1V0

5
9
13
114
118
123
127

11
12

QM
QP

130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165

VDD1V0

21
38
54
76
80
92
96
106

59
104
103
100

129

GND_HS

IR00

5R00

NC
NC

124

2R20 RES

GNDA

NC

1K0

10n

100n

2R13

10n

2R12

100n

2R11

10n

2R06

2R05
2R08

100n

2R07

+1V-DVBS

1
4
6
10
14
113
117
121
125

3R10

100n

10n

2R10

100n

2R03

10n

2R02

100n

2R01

2R00

100n

2R04

+1V-DVBS

POWER_VIA

10K

15
17
22
25
28
31
33
36
39
42
45
48
51
53
57
61
66
69
72
77
81
85
88
93
99
102
105
110
112

+1V-DVBS

122

XTAL

3R13

7R01-2
STV0903BAC

+3V3RF
3R12

IR06

+3V3RF

IR01

NC

2R43

9
8
7
6
5
4
3
2

SCL
SDA

XTAL_OUT
IP
IN

SATELLITE
TUNER
I2C-ADDRESS : C6

QP
QN
RF_OUT

AGC
AS
NC

10u

2R61

SYN

VIA

RF_IN

32
18
19

3R09

2R40

1K0

100p
3
3R08-3

21
20
7
34
35
36
37
38
39
40
41
42

XTAL

2
3R08-2
NC

4
6 3R08-4
100R
1
7 3R08-1
100R

5
100R

QP
QM

8
100R

IP
IM

0p56

SYN HS
29 33

100p

2R62

1n0

1n0
2R35

1n0
2R33

1n0
2R34
28

10p

23
24

XTAL_CMD

GND
RF LNA LT MIX DIG BB VCO
5
3
9 10 15 17 25 26

27n

5R02
2R45

1n0

2R29

SM15T

FR01

6R00

LNB-RF1

16

VCO

27p

10n

2R28

2R27

220u 6.3V

10u

10p

2R39
5R01
+3V3-DVBS

9R02
RES

27

2R56

AGC

22

10p

12
13

IR08

14

MIX DIG BB
VSS

XTAL_IN

1 2
1

11

2R55

31

10p

1R01
73356-5070
1

10p

NC

16M

2R38

IR07

SCLT
SDAT

LNA LT

10p

7R02
STV6110AT

3 4
30

10K

10K

3R15 RES

3R14 RES

10p

2R41

+3V3RF

2R54

1R10
NX3225GA

2R37
+3V3RF

1n0
2R32

2R31

4R7

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_048_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 234

10-28 B08 313912365192


DVBS supply

DVBS supply
5T00

B08A

IT00

A
4

VFB

+1V-DVBS

GND
P HS
8
9

3T00 RES

15

14

IT24

SENSE+1V0-DVBS

4n7
3T21

100n

2T06

11

+3V3-DVBS

4n7
2T36

1%

12

3K3

VIA

IT20

47K

1K0 1%
2T10 RES

IT02
13

10
3T03

FT06

IT18

2u0

22K
3T02

7T00-2
ST1S10PH

5T01

22u

SYNC

IT01

SW

VIN

RES 3T01

RES 1n0

2T03

INH

22u
2T05

1
A

+2V5-DVBS

2T04

7T00-1
ST1S10PH

22u

22u

2T02

22u

2T01

2T00

30R

SW

+5V-DVBS

1K0 1%
LD3985M25
7T01
IN

BP

+2V5-DVBS
IT19

COM
2

5T02

FT07

OUT

INH

30R

100n

2T07

1u0

1u0

IT03

2T39

BAS316

2T08

6T02 RES

BAS316

10n

6T00 RES

BAS316

2T09

6T01 RES
+5V-DVBS

7T02
LD1117DT33
IN

FT08

OUT

+3V3-DVBS
16V

22u

2T12

100n

2T11

COM

+24V

100u 35V

IT05

5T03

FT00

220n
2T17

2T14

47n

2T16

3R3

2T13

220n

IT04

100u 35V
2T15

3T04

10K

13
12
6
8

3R3

10K

5T04

4u7

RES 2T22

4u7

RES 2T38

10u

1n0

IT11

RES 2T37

10u

2T24

2T23

6T04

SS24

16
17
18
19
20
21
22
23
24
25
26

22R

3T11

33u

100u 25V

+V-LNB
IT32

GND_HS

IT17

1n0

IT12

3T29
3T08

3T10

IT09

15

GND

7T04-1
BC847BS(COL)
1

10u

2T35

IT21

IT10

47n

2T26

1n0

2T25
3T06

100K

IT27

6
3T07

ILIM2
SEQ
BP

VIA2

IT08

+3V3

BOOT2
SW2
EN2
FB2

IT26

2T27

9
10
11

BOOT1
SW1
EN1
FB1

PVDD2

1K0

1n0

2T21

2
3
5
7

IT07

+24V

10K

PVDD1

2T20

14

7T03
TPS54283PWP
IT25

IT06

22R

3T05

22u

6T03

SS24

33u

220u 16V
2T19

2T18

+5V-DVBS

RES
3T31

IT29

3T23

IT13

33K

2T41
RES
2T28

1n0
FT04

RES

+V-LNB

4u7

RES
3T24

SENSE+1V0-DVBS

15K

220p

2T40
2T31 RES

RES
2T29

47K
5%
RES

47K

3T16

3K3
5%

3T15

IT14
2T30 RES

3T17

7T04-2
BC847BS(COL)
4

22n
3T12

3K3

5
IT23

22n

3T14
2K2

BZX384-C
13V

1K0

IT22

6T05
+24V

3T13

IT15

3T25

3K3

V0-CTRL

330K
3T28
100K

RES 10n

RES
IT16

RES 10K

100n
RES

3T26
2T43

RES 2T34

IT30

2T42

22n

RES
3T19

33K

3K3
5%

3T18

18K
5%
22u

22u

2T33 RES

22n
3T20

RES 3T09

+5V-DVBS

2T32 RES

B08A

SPB SSB TV550


2K11 4DDR EU SD

FT05

2011-02-01

3139 123 6519


19101_049_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 235

DVBS supply

DVBS supply

B08B

B08B
+12V

+12V

+3V3-DVBS

3T22

220R

22u

RES

5T50

3T50

100R

100n

2T51

2T50

RES

100u 35V

IT50

IT28

220n

2T52

V0-CTRL

IT60
5T52

6T50

220n

2T53

BAT54 COL

18

A_GND
7T50-2
LNBH23Q
34
35
36

DISECQ-DET

6T54 RES

RES
7T51
BC817-25W

IT68

BAS316

IT69

IT59
9T52 RES

VIA
VIA

10n

2K2

IT55
2T62 RES

10u

3T58 RES

2K2

STPS2L30A

6T51

2T60

IT64

2T61

20

+3V3-DVBS
10K

1R0

IT67

150R

BYP

1
2
3
7
8
16
17
23
24
25
26
31
32

3T57 RES

3T62

22R

NC

VUP

11

IT66

3T54 RES

VCTRL

15R

3T59 RES

VCC_L

TTX

470n

VIA

DISECQ-RX

39
40

VIA
37
38

2T59

470n

15
2T58

100u 35V

2T57

470n

2T56

100u 35V

2T55

IT58

EXTM

22

RES

27

DSQOUT

DSQIN

LNB-RF1

3T53

21

3T27

14

+V-LNB

RES

VOTX

22K

1n0

13

9T51

IT57

30R

DETIN

3T52

RES

12

IT63

30
5T51

VORX

GND_HS

RES

29

IT65

RS1D

6T53

STPS2L30A

6T52

RS1D

6T55

IT56

F22-DISECQ-TX

9T50
RES

ADDR

28

IT52

220u

IT54

10K 3T55 RES


2T54 RES
IT61
IT62
10K
3T56 10n
10K

ISEL
LX

P_GND

DISECQ-DET

10

IT53

33

LNB-RF1

100R

SCL
SDA

3T60 RES
+12V

9
6

3T61

SDA-SSB

VCC

100R

IT51

41
42

SCL-SSB

19

7T50-1
LNBH23Q

3T51

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_050_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 236

10-29 B09 313912365192


Connectors comp

Connectors comp

B09A
+3V3

5C55-1

30R

1M59

AMBI-BLANK_R1
AMBI-PROG_B1
AMBI-LATCH2_DIS
AMBI-TEMP

FC77

FC76
FC78
3C70

100R

FC79

AMBI-TEMP-1

100n

2C70

FC81

GND_AL
NC

FC83
+24V

1C86

FC82
AMBI-POWER

100n
RES

1C87

100n

2C95

FC84
+12V_AL

2C94

T 2.0A 63V

T 2.0A 63V
RES

Option table for Ambilight

27

2C96

ITEMS

BLOCKBUSTER

EMMY

SUNDANCE
/ INFINITY

1C86

1C87

100p

100R

2C77

3C76

100p

IC73

100R

2C78

IC74

3C77

100p

2C93
47n RES

RC

LED-2

TO
LED PANEL

100R

FC90
FC91
FC92
FC93

2C79
IC75

3C78

100p

100R

2C80

FC94
+5V

100p
FC95

KEYBOARD

1
2
3
4
5
6
7
8

FC89

+3V3-STANDBY

LED-1

**

1M19

FC88

100n

V-AMBI

3C75

2C81

FC75

FC87
LIGHT-SENSOR

6C02

FC74

3C79

28

10R

100p

FH34SRJ-26S-0.5SH(50)

2C82

100n
RES

RES

AMBI-SPI-CS-OUTn_R2
AMBI-LATCH1_G2

2C76

**

6C05

FC73

AMBI-PWM-CLK_B2

RES
BZX384-C5V6

FC72
V-AMBI

BZX384-C5V6

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

FC71

AMBI-SPI-SDO-OUT
AMBI-SPI-SDI-OUT_G1

6C03 RES

FC70

AMBI-SPI-CLK-OUT

BZX384-C5V6

FC9C

100K
RES

5C55

3C74

B09A

1
2
3
4
5
6
7
8
9
10
11

GND_AL GND_AL
RES 3C96
+3V3-STANDBY
+T
1
2
3
4

0R3
9C02-1
9C02-2
9C02-3
9C02-4

8
7
6
5
12

3C97

SDA-BL

FC86

100R
3C83

1
2
3
4

1u0

1u0
2C91

2041145-4

TEMPERATURE
SENSOR

100R

RES 3C93

**

2C90
FC98

FC9D

3D-LED

10K
FC99

30R

RES 5C53
+12V

2C85

5C54
+3V3

**

T 1.0A 63V

FAN-DRV

FC97

RES 3C92

RES
1C85

+3V3

FC9B

47R

1M71

FC96

FC64

20

10p

FC63

100R
RES 3C82

SDA-SET

47R

19
FH52-18S-0.5SH

FC9A

10p
RES 2C87

FC85

100R
3C81

9C00
RES
9C01
RES

SCL-SET

RES
3C94
RES
3C95

RES 2C86

FC62

100R
RES 3C80

100R
FAN-CTRL2

**

RES 3C91

1u0

TACH02

100p

SCL-BL

10K

13

0R3

RES 3C90

100p
2C84

TACH01

2C83

FAN-CTRL1

+3V3
FC61

+T

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

FH52-11S-0.5SH

+5V

* HOTEL TV

RES
1M21

1M20

IC78

RESERVED

30R

Option table for Leading Edge

Items

BlockBuster / Emmy

Sundance / Infinity

1M19

Yes

No

1M20

No

Yes

1M21

No

No
2

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_051_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 237

10-30 B10 313912365192


DVBT2

DVBT2

2FJ4
100n
2FJ3
100n
2FJ2
100n

2FJC
100n
2FJB
100n
2FJA
100n
2FJ9
100n
2FJ8
100n
2FJ7
100n
2FJ6
100n

B10A

+1V2-DVBT2-M

+1V2-DVBT2-C

B10A

+1V2-DVBT2-P
2FJJ

+2V5-DVBT2-A

+3V3-DVBT2-D

100n
+3V3-DVBT2-R

2FJE
100n
2FJF
100n

2FJP
100n

2FJD
100n

2FJL
100n
+2V5-DVBT2-X
2FJK

2FKB

IF-N-DVBT2

3FJM

RES 9FJ4

IFJ5

2FJY
DVBT2-IFN

DVBT2-IFN

47
IFJ1

3FJ0

46
1K0
50
49

5FJ9
9FK5

3FJB
2FJ1

150K
100p

3FJA
3FJ9

100R
330K

53

1M0

3FJN

3FJ2
2FJN

RF-AGC
5
7FJ1-2
BC847BPN(COL)

64
63

1K0

MVDD

3FJ7
1
7FJ1-1
BC847BPN(COL)

IFJ4

10K
3FJ8

+3V3-DVBT2-D

R
VDD

45

54

44

8
19
40
41

52

11
27
59
DVDD

XTALI
XTALO

0
1
2
3
TSDATA
4
5
6
7

AINP
AINM

RFAIN

58
57

IFAGC
RFAGC_GPIO1

SCL
SDA

TUNERCLK
TUNERDAT

I2C ADDRESS
0xD8, 0xDC

DFJ1
1

GPIO0

10K

3
+3V3-DVBT2-D

IF-AGC

IFJ8

RES 3FJ4
4K7

RES 3FJ3

32

33

TESTMODE

A0

4K7
DFJ2
REMOVE IN
NEXT LAYOUT

VIA
34

9FJ0
37

RESET-SYSTEMn

OSCENBN

RESETN

DFJ4
38

OSCMODE

DFJ3
PLLBPN

IFJA

PVSS

5
4
3
2
12
13
16
17
22
23
24
25
28
29

RES 9FJ1

3FJG
3FJF-2 2
3FJF-3 3
3FJF-4 4

7
6
5

47R
47R
47R
47R

9FK1
9FK2
9FK3

3FJF-1

47R

9FK4

IFJ9

TS-FE-CLOCK
TS-FE-VALID
TS-FE-SOP
TS-DVBT2-ERR
TS-FE-DATA

REMOVE IN
NEXT LAYOUT
9FJ2
3FJH
3FJJ

47R
47R

SCL-SSB
SDA-SSB

66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90

XVSS
48

MVSS

43

6
10
15
21
26
31
35
55
60

51
5FJ1

FFJ0

+3V3-DVBT2-D

+3V3

GND_HS

9
18
39
42

VSS

AVSS

65

62

6p8

TSCLK
TSVALID
TSSYNC
TSERR_GPIO2

DFJ0

IFJ3

4n7

2
4

CVDD

47p

+5V-TUN-PIN

820n

7
14
20
30
36
56
61

12p

AVDD
IFJ0

2FJV

100n

RES 2FJM

7FJ0
CXD2820R

2
4

1FJ0
41M
680n

10p

100n

100R

10n

47p

DVBT2-IFP

100R

10n

IFJ2

2FJW
DVBT2-IFP

5FJ0

3FJK

RES 9FJ3

RES 2FJ5

2FKA

IF-P-DVBT2

12p

2FJH

2FJT
820n

2FJG

100n
5FJ8

5
6
7
8

+1V2-FE
IFJB

5FJ5
+3V3-DVBT2-R

IFJE
+1V2-DVBT2-C

+1V2-FE

30R

2FK4

1u0

2FK1

30R
1u0

220u 16V

5FJ2
10u
2FKG

9FK6-4
9FK6-3
9FK6-2
9FK6-1

RES 2FKF

4
3
2
1

+1V2

1u0

2FK0

30R

RES 5FK2
+5V

7FK1
LD3985M25
IFJC

+2V5-DVB

5FJ6

+1V2-DVBT2-M

1u0

30R
2FK5

IFJF

+2V5-DVBT2-A
30R
1u0

BP

COM

5FJ3
+2V5-DVB

2FK2

INH

FFJ1

1u0

OUT

2FKE

5FJ4

IFJD

5FJ7

IFJG
+1V2-DVBT2-P

+2V5-DVBT2-X
2FK6

1u0

1u0

30R

30R
2FK3

1u0

2FKC

IN

10n

30R

2FKD

+3V3

30R
5FK1

SPB SSB TV550


2K11 4DDR EU SD

2011-02-01

3139 123 6519


19101_052_110504.eps
110504

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 238

10-31 313912365192 SSB Layout

1C87
1C86

3C70

2C70

2C96

2G13
3G13

3G12

3G11

3G14

3U81

3U42

7T03

5UD3

2UE4

6GA1 3GA6

1X10

2G44

1G03

3GA5

1X07

7GA1

1G36
3GA2

3G15

6G00

3G28

1P00

1G37
7GA2

2UU2

5G01

2T19

3US3

3US2

2T33

6GA0

IUS9

2UD9
3U26

2UD6 6UD0

7US3

3UD3

2UD4 2UD5

1G35

IG11

9GA0

2GA4

2G43

2UE1

3UD4

9UU1 9UU0

5G02

1G00

1X08

3US9 3US6

2U15

3UD5

2UE2

5U01

5C53

3U29

IU15

2UE3

5C54

2U16

2UD8

2UE6

6U00

2C85

3C82

7US2

2U09
3C93

3C92

1C85

IUD2

IUS6
2US3

2C83
2C84

3U24

2U17

IU18

IU17

3C90

2U11

3C91

IUT1

IUS5

2U18

3C81
3C83

5U00

IU23

2T18

5UD0

IUD4

7UD1

2T00

5T03
2T32

2UD2

IUD1

IUT2

2T01

6GA2

2U27

3UD2

3U06

2UD7
3UD1

3UD0

3U07

2UD1

3US7

3C80

5UD1

2UE0

3US5

7US1

7UD0

5UD2

9US0

3US4

3U23

7U01 7U04 7U02

7UU0

1M71

IUS4

2UD3

7U05

2UE9

IUS3

2U28

7UD3

2UD0

6GA3

2UE8

5U03

5U02

2U19

2U23

2U25

2U24

2UE7

IU57

2T22 2T12

2C95

IUD0

2U20

7T00
5T00

1UM0

2U56

3U56

3U44

2U50

2U52

3U66

3U67

2U51

3U84

5UM1

3U76

2U68

2U54

1F24 2T14 2T17 5T04

2C94

5C55

3G10

3U65

2U48

2U72
4U00

3U45
3U64

2U49

3U71

2D30

2U47

2U45

2U58

2U53

3U43

2U44

4U01

2U46

1M59

1M99

CXXX

2U43

1M95

5T01

Overview top side

3GA1

7GA0

3B11
3B26

IGA3

3B18

IGA2

7S02

3S31

3S02 3S01

3S24

3S23

3S29

3S62
3S21
3S3S
3S1K

2S4E

3B13

3S3N

3S2A

3S1B
3S1L

3S3T

2S4D

3S1J

3B12

3S3R

2B44

3S28

3S03

9S01

3S3Q

3B02

7S00

3B23

3S1C
3S3L

3R14

2R29

2R28

3R15

2R33

9R02

2R45

2R31

5R02

2R43

3R09

2R38

1R10

2R40

2R34

2R39

2R62

2R54

2R41

7R02
2R37

6T55

2T55
6T52

7T50

2T56

1X04

3S42

2F40

2FKG

2F91
3F72
IF89

2FL7

1P08

7FL5

5F70

2F9D

1E85

9FLF

3F34

9FLG

9FL3

IF86

5F73

9F04

3FL4
9FLE

1E08
3ECG

2FDD

2EC1

7EC1

3FL2

2F60

6FC7

2F97

3ECM

6FC5

3FC3

1E37

1P03

1P02

1FC3 1FC4 1FC2

1FC5

1P04

1FC6

6FC2
6FC1

3FC5

3FC6

9FC6

9FC4

2FC1

1E09

1E10

2FC7
3FC2

2FC6

1E38

2ECC

9FC5

5EC2

9FC3

1N00

1P05

6FC3
6FC4

IEE3

9EC3

1E80

3F65

3F64

2F9B

2F88

2F86
3F75

1329

2FDC

3FDG

2ECN
2ECM

6FC6
3FC1

7EE1
2EE1

3ECN IE42

2E67

2FC2

3EE2

6E51
9E57

2FC4

3E9C

3E89

3FC4

3ECF
4E21

4E20
2E73

9E17

IEE6
2EE2

6FC8
2FC8

1FC1

6E53

2EE7

4E24

9E50

IEE4
IEE5

3FC7

2E77

2EE3

6FD2

2F81

2C81

1FD2

1P07

3ECP
6FD3

2EE5

3C95

3EE3

3C94

2C87

3EE0

2C90

2C86

1T01

1FD3

6EC1

2ECU

3EE1

6C05
2C91

1E39

1E28

2FC3

2E05
3E27

1E88

2E62

2E60

6E47

IC74

2F9A

2F99

2FC5

5E01

2EE6

3C79

3E98

6C03
2C82

5E02

1E03

2E63

2E56

3E28

3E26

3C77
5E08

3C96
3C97

9C02

2C78

IC75

2EE4

2E57

3C78

2EE0

3E25 3E22

2C93

2C80

7EE0

2E66

2E07
3C76

1E87

3C74

6C02
2C77

3E40

3C75

1E43

1E42

1E29

1F52

3E68

IE11

3E34
3E35
3E72

2ECP

IE07

2C76

1F51

2F98

2G75
2G77

IE09

2E54

3F63 3F62

4E22

2E27

9F71

9E15

4E23

2E71

9E13

6E38

3E96

2E40

6E06

9E11

9E29

6E40

IE10

2G76

1X06

3E88
9E52

1328

7E10

2G27

2E55
3E30

3E33

1E70

2G9B

2E39

2E72

2E52
3E51
3G38

2G78

3E97

2E53
3G39

2G26

5F72

1E32

2G9A

2G25

3E87

9E04

3E66

2F93

3E65

3E67

3E70

3E69

2E49

3E64

9E42

2E48

3E80

3E71

2F9C

2G24

1X02

2FL6

9FLL

1E25

9FLD

9FLK

1E22

1E54

3FLE

7F70

3FLC

1E55

1E31

1E18

1E01

5D05
2G28

9FLC

3F78

3FL7

1E23

1E19

6F72

9F05 9F06

1E12

1F75

9FLH

9FLJ

1FL5

9F00 9F01

9E22

1E06

2E14

1E86

1E53

9E05
4E02

4E04

4E01

6E26

2E18

9E21

6E22
4E05

IF61

2F92 2F94
2F90 3F71

1E71

9E18

3E76

4E03

1X11
1E00

3E77

2E84

7F58

3F58

2F58

1F10

2S41
2E83
3E31

3F59
3F60

7F52

3S84
3S83

2S4M

5E74

3E32

5T51

1P09

2S77
2S78

BS13

9E20
9E24

2G29

2G79

1M20

9F28

3S44
3S2M
BS10
2S87

2S7L

2S7N

2S7U

2S8G
9S18

9S20

3S59

3S4P

3S4R

3S4T

3S4J 2S7J

2S7P

2S7R
9S19

2S7E

2S7H

2S7K
3S4L

9S21

2S7M

3S6H

3S13
3S12

5D02 5D01

3S4K

2S2S

3S53

9F27

3S3W

3E17

2S2Y

2S31

2S2Z

2S2W

2S33
2S32

4S14

3S6J

7S08

3S26

2D09

IS13
2S34

2S30

2S2R
2S2T

1X24

3S3M

3S43

3S3G

2S2V

9S06

3S3H

3B04

3S3U

DBS8

1S02

5T50

3S50

2D06

2D12 2D11

3S54

2S4G

3B14

3S27

2D10

3S52
DS50

3S3F

3B15

6T51
6T53

2S4F
BS15
2B45

1X20

2D07

7B03

7D10

2G7A

1M21 1M19

5T52

2D23

2D24

2D17

3B05

3S80

3B24

5D04

1G51

IF62
3S81

3S00

1D52

2D08

1735 1D38

1D50

3S6K

5D07

1R01

3R08

2R56
9S00

1X23

3S3Y

3S04

7R01

3T22

3R06

2T57
2T50

3R05

2S09

7B02

3R04

3B17

3B07

2R20

2R27

2R32

2R46

9S93

9S92

3B08

9S90

5R01

3R03
3B16

3B00

1X05

7F20

3B25

2B46

7B00

2D20

2D05

5D08

2D19

2G96

9S91

2S4P

3B10

2G99

2R55

2G98
2G97

2R35

IGA1

3R12

3B19

2R61

2B47

7B01

2F01

1X21

1G50

1X22

1X01

1E05

SSB Layout Top

2011-02-09

3139 123 6519


19100_804_110209.eps
110209

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 239

Overview bottom side

2G17

FC71

2G16

2G14

2G12

2G10

IUB5

3U69

3UB6
IUB3

7F02

FGA4

2GA5

2UB3
2UB4

3UB4

3S39

2S2H

2F79

2FE6

5FE7

7FE0

DFE8

7FJ1

IU56

IU55
FU09
CU01

CU02

3U05

FU00

IU14
3U02

2U00
3D16

7D03

FUU0

7UU2

FG1J

FG32

2G94
2G95

3D06

FG1Y

FG1Z

FG2E

FG2F

3G30
IE38

FE49

3G34

IE26

IE64

FE50

2E06
9E25

FE5E
FE5D

IE63

3G36

FG2L

3G2Z
FG2R

3G37

FG2K
FG2G

IE06
2FE4

3G2Y

FG35

IE32

3G2W

2E70
DFE7

FG04

3G32

FG34

3G35

IE39

DFE6
FE31
DFE9

IF17

2FG4

FC9D

FE29

IF18

FE34

DFF2
IF49

2FH3

2FF4

2FF8

3E29
FE27

FF63
5FA3

2FA3

FE28

5E03

3E99
FC88

2E59

5E04

3E39

FC93
IC73

IEE7

5FA4

IF69

2FF9

2FF1

2FA4

FF61

2E58
2E08

3FE9

3FE8

2FF2

2FF7

2FE3

3E95

FE32

DFF1

IF68

2FH4

7FE3

FF62

2FG0

IF67

5FE8

5FE5

2E09

2FE8
FF03

FC89

FE33

IEE8

FC90

FFAF
FE30
IEE0

FC91

FC92
FC94

FE60
FECB

IE44

FFA2

FE48
9E54

6E52
IE76

FE5C

9E19

FE51

FEE0

FE5B

IE74

FC9B

2ECX
3EC5

2E68

3EC3

IE12

6E20

9E58

3ECJ

FECR

2EC7

2EC3
FECY

5EC3

3ECK

FEC7

3ECL

FEC3

FC9A

2ECW

IE43

IE45

2EC2

2E37

3E20

2E36

6E19

2E38

FE02

FE01

2E35

3ECH

7FA3

2ECQ

FE03

2FA2

FF76

3E21

FFC9

FE61

FECZ

2F59

2F61

3FJN

9FK5

3FBF

FG20

2C79

FF74

FFB1

2UU1

9G0K
2E04

3E82

3E07

FEA3

IE73

FE55

FFB6

2D22

2E88

6E03

FE73

9E28
IE71
FE54
IE51

FEA2

4E06

FE5A

9E26

2FG6

FF81

5FE9

FG21

3G33

3E81

FE71

2E91

6E09

9E07

IE14

BFE2

FFDB

FFB5

IUU2

2UU0
3UU2

3D01

2D27

IEC1
3E24

2D26
FE82
FEA7

9E10

2E75

7E09

FE84

BFE3

6E29

3E43

2E44

6E32

FEA8

FE42
2FF0

2FG1

2F84 3F76

9E16

2FF5

IE16

3FG7

2FH7

2FH2

FFDA

FG24

FG22

FG2M
3G31

2FH6

2FG7

FFDC

FG29

FG25

IF29

2FG8

FL33

FG28

FG23

FG2H

2FG9

3FG2

FC87

IF65

FL40

FG2B
ID08

IE33

FF82

FL41

FG1R

FG2A

FG26

3E73

2FH5

FG1S

FG2D

FG27

2E24

2FE0

5FE3

FG1T

FG1U

FG2C

3D14

ID06

3E44

5FE0

FG2P

3FG6

2FG3

IF63

IF48

FG2N

3FE6

2FF3

2FE5
2FG2

5FE4
FF00

FF64

FL32

FE72

5FG0

3FG4

1FE0

IF66

2E01

2G91
2E90

FE70

IE50

IF82

IF27

IF64

2FF6

ID07

6E07

2E15

2E87

2F71
2F75

3F77
3FE5

3D02
CD10

6E23
FE74

2D21

2G9D
9E08

3D10

9G0G

IE08

3E37

3E74

3E53

3FE7

IF28

ID30

FD09
ID09

2E86

3E79

9E55

FE81

9E53

9E09

BEC3

9E51

2E85

6E28

2E80
3E75

2E12

2E76

6E30

9E06
FE43

FE80

6E01

3E19

3E48

5E76

ID05

9E27
FE75

FEA6

IE17
IE92
3E45

2E98

3EB6

2E10

FEA0

2EA4

IEC0

7E01

9E23

3EA7

IE49

IF74

3F80
3F81

2D16

2B36

2B02

2B08

2B03
2B07

2B05

IEC2

FEA1

5E73

BEC5
FE83

7E06

3EB3
2E99

IE60

IE91

IE96

3E62

IF14

5FG2

AF70
IFLB

FF65

2U57

2D31
3D09

2B11

2B12

2S29

2B06

2S39

2S38

2S3A

3S72

2S3B

2S3C

2S3D
3S34

3S32

2S2J

3S51

2S3J

2S42

2EA5

2E79

6E43

5F66

2F66

IF78

2F63
2F64

2FH8

FL43

3U11

2B26
3B20

2B21
2B14

2B16
2S24

C001

2S3E

2S3F
IS1M

2B04

2S4R

2S4Q

2S45
2S3G

IS1A

2S3H
IS1B

3S09
3S10

2S2L
3S08
3S37

3S6L

2S2G

3S38

7E05

2E74

9E01

3EA1

3E18

3E06

2E97

IF15

AF71

3U80

2UB1

2UB2

FUA3

2B39

2B27

2B35

2B28

2B19

3S6P

IS42
3S20

2S68

2S53

2S52
2S18

2S40

2S19

2S8A

3S5B

IS5C
2S22

2S2K

IS1P

FD02

3S0Z

FE85

IF76

IF12
IF13
IFLA

IFLE

FD06

2D13

ID10

6E44

9F03
9F02

2D14

5D03

FD14

IE70

2F78
2F74

FF71
3FLF

3FLD

IF10

IF11

FG1W

3S6Q

2S60
5S93

2S23

5S81
5S90

2S50

2S4Z

2S15

3S75
2S16
3S05

C000
3S49

3S3P

2D01

ID31

IF73

7F75

FF01

FG1V

3B21

3S06
3S07

2S17

2S26

2S67
2S64

2S5P

2S4S

2S5H

2S5J
5S89
5S87

2S5A

2S28

2S59

2S58

2S6K

2S55

2S56

2S4V

2S6A

5S04

5S92
2S6H

2S5C

IE59

IE13

3EB1

2FL9

3FLA

2FLD
3FLB
3FLH

3S36

FD05
ID32

IS12

IF81

3FLG

3F32

IE61

2E81
5E80

IF75

2FL8
2FL1

ID28

2B00

3B03

3S1D
IE89

2EB3

FE56

FF75

IF77

ID29

2B41

IS07

IE68

2FLA

FF66

ID19

ID27

FEA4

3EA2

IFLD

ID37

IE18

FE57

FE58

2F85

ID15

ID18

2B01

IE90

IF90

2FL2

3B28

FS57

2EB1

IFLG

2FL4

7D15

FS52

2F96

IF59

IFLC

IFL3

2S6M

2S5D
2S2E

3S47
IF80

FF57

IS0R

FD08

2D29

9E12

3F79
IF79

IF72

IS1H

FD01

IS1D

9E14

5F71

IF58
FF29

2FKD
IFL1

7E13

2F95

3S5E

FS53

3E9E

5F74

2F73 2F80
2F72 2F82
2F77
2F76 AF73

IF50

FF55

9FK6

FL36

2FLC

2S14

3S5V
3S6N

3S5T

3S11

3S6M

7E12
IS11

2D28

FD03

IS03

7S05

IS1J

IS02

7E11

9FJ3

9FJ4

2FKA

IF52

FF56

2F62
2F70

3F52

2F49

AF72

3FJK

2FKB

5FJ9

1FJ0

2FJH

2FK3

5FJ4

5FJ7

5FJ6

2FJG

3FJ0

2FJK

2FJ2

2FJ8

3FJ4
3FJ3
9FJ0
5FJ5

2FK4

7FK1

3FJM
IFJ0

IFJD

2F65
3F82

3E9D

IFJ1

2FK6

IE67

3S16 3S17

3E78

2FK1

IFJ2

2FJW

6E48

ID33

2B09

FD15

IS1S

FS03

2FJ5

2FJY

IS1N

IS06

FS50

5F76

2D02
ID14

2B40
IS50

IS1Q

5FJ8

IFJG

2FJJ

9S24
IS20

2FK2

2F52

3F43

3F41

3F42

IFJE
FF41

IFJF

IS5G

IS3E

IS0V

IF16

2B13

FS08

IS4V

IS3F
IS2V

FS44

FEA5

IF54

DFJ4

IS2Z

IE05

5FJ0 2FJT

2FJV

FFJ1

3S2L

IS19

FD07

ID11

2S36

IS5H

IS1E

2E69

2FJP

IS4W

IS44

2FJ1

3FJ9

IFJC

IFJ5

2FL3

2S76

IS5J

IF53

DFJ2

2FLB

IS5E
3S5S

IFJB

2FJ9

2FK5

IS3B

IS3D

3S46

2B17

2S46

2S86

FS49

IFJ4

2FJ7 2FJF
2FJL
3FJ7
3FJ8

7FJ0

2S85

ID12

2B37
2B15

FS02

2S6G

2S75

3S1H

3FJB

3FJA

5FJ3

3F40

IFJ3

9FK3

5FJ1

3D15
2B10
3S0V

2S65

2S20

2S51

3S2S

IS1K

IFJA

2S6E
2S6D

3S22

IS3L

ID35

7D11
ID34

2S6N

3S76

IS5D

3S1G

2S84

3S19

3S25

2FK0

2FJN

DFJ3

2FJ6

IFJ8

3S40

2S10

FS10

2B18

3S30

2SHW

FS45

7S09

IS1L

5FJ2

3F45

3FJ2

2FJ4

2FKF

2S5K
5S95

IS5F

FS11

3B06

3B01

DS52

FG31

2G9C

2B20

3B22

2S4U

IS4Z

9FK4

DFJ0

FF44

9S09

FG1D

3S33

5S84

3S55

2S3L
IFJ9

9FK1

DFJ1

FFJ0

2FKE

2S6B

2S21

5S83

2S5G

2S13

IS2U

2S3M

3FJF

9FJ1

2FJC

2FJD

3FJG

2FJ3

2FJB

3F44

9FJ2

2FJA

2FL5

FG30

2B24

2D03

2S4Y

FS51

FF48

FF42

3S0W

3S64
3S45
3S2H

FS0Z

FF43

3FJJ

IS01

2S4W

2S43

9S0D

2S4K

IF51
FF04

IT51

2S3Q

3FJH

2S5B

IS16

9FK2

2FJE

2S6L

3S2K

3S41
3S1P

2FJM

FF47

IS05

FC95

7S20

IT54

IS3S

2S27

2S4T

9S0E

IT69

IT67

3T62

5S80

2S62

5S94

2S57

IS3Q

2S6C

3S2V

6T50

3T27

7T51

3T53

2T58

3T55

IT61

IT57

2T37

IFL2

5S82

3S1U

3S1R

3S1T

3S1S

IT68

3S1F

3T50

2T60 2T53

IT53

3T60
3T52

3T58
2T54

IT62

FF45

5S85

IS10
FS64

IT64

2T51

3T59
2T62

2S6F

2R22

3S82

IS04

9R04

IT50

IT52

IT59

9R03

2T59

9T52

IT28

3T54

FR01

3S69

3F06

2T61

IT60

2T38

3S6V

3S1X

2R15

2R26

2R25

2R21

3T56
9T50
9T51

6T54
2T52

3T61

IT55

3S6W

3S1E

IR04

2R09

2S11

3S1W

IS3K

2S5M

2S6P

IS25

3S56

2S37

3S57
3S2F

3S6A

IR03
3R01

IT58

3T51

2S63

5S88

3S5Y

2R52

2R23

IR00

2R17

3S6D

3S2G

IS58

IT65

IFLF

3B27
2B22

3S6F

3S5Z

2R51

FG1F

FG1C

2G93

FS01

3S15

3S60
3S6E

IS40

5R00

2S61

2R08

2R14

IT63

5FK1

2B42

2S25

3S1V

FG1E

2G92

2S66

2R07

2R24

3T57

IFL4

2B33
2B29

3S58
3S5W

FG1G

FG33

9S08

3S6G

IT66

FF49

2B31

2B23

9S12

2B38

3S67

9S96

3S65

3R00

9F25
9F26

9S94

9S95

IS08
9S11

2S4N

IF88

FF46

FG1H

3B09

3S61

2R19

FG1L

FG11

2S89

IS00

FG1M

FG1K

2B25

3S6B
3S6C

IF87

FG1N

2G9F

2S12

9C01
9C00

FG12

2B34

2GA1

9S97

9S10
9S13

3F19

FG14

FG13
FB00

3GE4

2R13

2R16

IT56

2UB0

2GA3
5GA1

2GE0

5GA0
2GA0

3GE3

2B32

FS31

7S01

3F22
IF22

3F20

2R12

2R49

FG16

FG15

2B43

FGA0

IS09

2R11

FR07

FG1A

FG18

FG17

IS26

2R18

CUA0

9GA1
IGE1

3GE1

2GA2

2GA6

3GA4

7GE0
3GA3

3S68

IS17

2F20

FG1Q

FG19

2B30

3F23

2R00
IR01

FG2J

FG1B

2R50

IR07

3UU0

FGA1

3GE2

3S66

9GE1

3F24
IF23

3F12

3R13

2R06

2R04

3R10
FR02

FR03

IUU3

7UU3

FG0H

9GE2

2F03
3F21

2R10

FR06

7UU1

3UU3
IUU4

FUU1

3GE0

2R01
FR04

IUD5

IUU5

FGA6

IGE0

IF21

2F21
2R05

2R03

FR05

IC78

2U14

FU03

FG1P

3R11

3R02

FC99

FGA5

2R48

2R02

2R53

FC97

2G9E

9GE0

9R00

FR00

FC98

2U29

IUU0
FGA3

7GE1

6R00

IU40

3U21
IU19

2U10

IUU1

3F05

IR02

FUD2

2UE5

FGA2

IF07

IR05

2UB6

IUB1

7UA3

7UA5

IUB6

3U15

5UA0
3U41

3F07

3R07

7U48

3U20
IU01

FUA4

IU44

3F03

IU21

IUB2

3U12

2UB7

7U42

9U41

IU26

3U13

7UA6

7UD2

IU47
IU43

2UB5

3F02

3F01

2F02

7F01

3F10

IF05

2R47

2U04
3U03
CU05

7UC0
3U16

7U43

3U59

FUD3

IF03
IF01

3F04

FC96

IU64

3U83

3UB1

2U71

6UD1

3U74

7U06

7UA7

IF04

7F00

2F00

3F11

2F06

7F05

IF02

IF08

IF06

FU06

IU25
IU02

2U13 2U12

2UB8
IUB4

3U53

FU05

2U05

IU09

3UB7

IU30

IU07

IU12

FU02

IU50

3U61

IU41

3U68

3F09

7U03

FU04

IU29

3U75

IU06
2U02

3UB0
IUA6

FU76

3U17

IU13

3U82

3UB5
IUA5
IUS7

3U25
3U70

3U18

3U14

IU10
IU61

IU52
IUB0

2UA4

IU45

3U19
2U08

3U09

IU20

IU04

CU04
CU03

7UA0

3UA0

FUA0

3UB3

3UB2

FS2Y

FU62

IU08

3U63

9U42

3U10
2U07

3U22

2U21

FC63

7UA4

7F03

9FD2

IFD3

2FD1

3U60

FU55

2U03

IU24

2U01

IU05

IUS8

7F04

9FD1

3FD6

IFD1

FU53

FU08

FU72
IU11

7U41

FC62

2F04

2F05
3FD3

3FD4

6FD1
3FD1

3FD7

9FD5

3F53

IFD2

FU52

CU00

IU16

FU07

3F08

FL37

IU48

IU63

FS2W

3U01

3U27

3U73

IUD6

IF55

2FKC

IU03
IU49

3U62

IU27

FU51

3U00

2U55

FC85

FU67

2U06

FC86

7FD1

7F54

FF58

3F54
3F66

3FD2

2F53

3F69

9CH0

IFD5

7F53
3F67

5FK2

FU66

FU75

FU01
IU22

2U22

IUD3
IT06

FU61

FU63

IUD7

IF57

FL42

FU60

3U72

6U40

FU57

7U00

3FLJ

FU68

FU73

IFD4

FF50

IU51

1U40

3T31

3T07

FU74
FU56

IU62

IF56

IF47

FU59

FU78

FU58

IU28

3F68

IR06

FU54

FUS0

IT16

2T11

IR08

FU50

FC61
FC64

3UU1

3T20

FU49

FU48

IT05

3U08

2T31

FC9C

2G15

3U28

IT15

9FL1 9FL2

FC70
FC72
FC79

3U04

IT14

3T24

IT17

IUM0

FC78

FU77

IT07

2T30

2T28

2T25

IT13

3T12

2T29

2T23
2T24

3T29

2T21

2T40

IT32

IT08

FUM0

FC76
FC82

7U40

FT05

3T18

3T23

IT29

3T14
3T17

6T03

IT25

2T13

3T04

IT27

FL38

IT21

3T05

2T35

FC73

2G19

7T04

3T06

2G11

2T26

IT26

2T20

2T43

2G18

FT00

3T08

6T05

IT23

FC74

FC75

FC84

FL31

FC77
IT22

IT04

3T13
2T34
3T09 3T15
3T19 3T16

IT30

FT04

FL30

FL39

FC83

2T15 2T16

IT12

2T27

6T04

7T01

3T11

IT09

IT10

3T10

IT03

2T41

7T02

IT24

FC81
IT11

3T25
3T28
3T26
2T42

2T10 2T36

FT08

FT07

6T02

3T00 3T21

FT06

3T03

6T00

3T02

IT02

2T39
6T01 2T08

2T04

IT18

2T05

3T01

IT20

2T06

5T02

2T09

IT19

2T03

2T07

2T02

IT00

IT01

3E90
IEE1

2ECY
9EC2

2EC6

FFC7
2EC8
FFC2

5EC0
IE65

IE66
FEC0

3ECU
FE36

FECA
IEC6

IEC5

7EC0 7E02
IEC4

FECE

FECJ
FE35

FEC1

FECM

3ECE

3E23
FEC2

3ECD

9EC0

3ECA
FECF

FEC5

FECW

FFC8

IEC7

FFC1
FFC6

FEC4

9FC1

9FC2

FFC5
FFB4

FFC4

2ECV

FFC3

FFB3

2EC0

IEE2
FFB2

3EC1

FECD
FEC6

FECK
FECL

FECP
FECN

FECC

FECG

SSB Layout Bottom

2011-02-09

3139 123 6519


19100_805_110209.eps
110209

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 240

10-32 B01 313912365351, 313912365371


Common Interface

Common Interface

B01A
+3V3

3F01

19

3F03-2 2

3F03-1

IF02
3
4
5
6
7
8
9

8
100R

7
100R

CA-CD2n

3EN1
3EN2
G3

CA-DATAENn

100R
CA-MOVAL
CA-MOSTRT

CA-CD1n

IF01

3F02

CA-MOCLK

IF03

1
2

18

MOCLK

17
16
15
14
13
12
11

MOVAL
MOSTRT

CA-DATADIR

CA-ADDENn
MOCLK
MOVAL

10

MOSTRT

MDO0
+3V3
2F02

19

MDO1
RES
MDO2

100n

20

7F01
74LVC245A
1

MDO3

3EN1
3EN2
G3

MDO4

IF05
CA-MDO0

3F04-1 1

8 100R
IF06

CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7

3F04-3 3
3F05-1 1
3F05-3 3

3F04-2
6 100R
3F04-4
8 100R
3F05-2
6 100R
3F05-4

7 100R

5 100R

7 100R

5 100R

3
4
5
6
7
8
9

1
2

18

MDO0
MDO5

17
16
15
14
13
12
11

MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7

MDO6
MDO7

10

CA-WAITn
+3V3

CA-INPACKn
2F03

15-BIT ADDRESS
3EN1
3EN2
G3

XIO-A01
XIO-A02
XIO-A03
XIO-A04
XIO-A05
XIO-A06
XIO-A07

17
16
15
14
13
12
11

CA-WP

1
2

CA-VS1n

1
19

CA-ADDENn

CA-A00

3
4
5
6
7
8
9

CA-A01
CA-A02
CA-A03
CA-A04
CA-A05
CA-A06
CA-A07

10

XIO-A00

18

RES

100n

20

7F02
74LVC245A

5
10K
7
10K
3F07-3
3
6
10K
3F07-1
1
8
10K
2

17
16
15
14
13
12
11

20
1
2

1
19

CA-ADDENn

CA-A08

3
4
5
6
7
8
9

CA-A09
CA-A10
CA-A11
CA-A12
CA-A13
CA-A14

10

XIO-A09
XIO-A10
XIO-A11
XIO-A12
XIO-A13
XIO-A14

RES

100n

3EN1
3EN2
G3
18

+3V3
2F05

8-BIT DATA
3EN1
3EN2
G3
18

XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07

17
16
15
14
13
12
11

1
2

CA-DATADIR

19

CA-DATAENn

CA-D00

3
4
5
6
7
8
9

CA-D01
CA-D02
CA-D03
CA-D04
CA-D05
CA-D06
CA-D07

10

XIO-D00

RES

100n

20

7F04
74LVC245A

+3V3
2F06

CONTROL
7F05
74LVC245A

1
2

17
16
15
14
13
12
11

RES

100n

3EN1
3EN2
G3
18

3F07-2

+3V3

3F08-1

8
10K
7
10K
3 3F08-3 6
10K
3F08-4
4
5
10K
2

3F08-2

3F09-1

8
10K
7
10K
3F09-3
3
6
10K
3F09-4
4
5
10K
2

3F09-2

IF04

3F10-1

8
10K
7
10K
3F10-3
3
6
10K
3F10-4
4
5
10K

3F10-2

3F12
10K
3F11-2
7
10K
3F11-3
3
6
10K
3F11-4
4
5
10K
3F11-1
8
1
10K

+3V3

IF08

+5VCA

+3V3

1P00

+5VCA
2F04

XIO-A08

100K

3F07-4

CA-D03
CA-D04
CA-D05
CA-D06
CA-D07
CA-CE1n
CA-A10
CA-OEn
CA-A11
CA-A09
CA-A08
CA-A13
CA-A14
CA-WEn
CA-RDY

+3V3

7F03
74LVC245A

XIO-D09
XIO-D08
XIO-OEn
XIO-WEn
XIO-D14
XIO-D15
CA-WAITn

CA-RDY

IF07

XIO-D11

3F06

CA-RST
RES

100n

20

7F00
74LVC245A
1

0R3

20

22u 16V

+T

2F00

TRANSPORT STREAM FROM CAM

+5VCA

1
19

CA-ADDENn

CA-REGn

3
4
5
6
7
8
9

CA-CE1n
CA-CE2n
CA-OEn
CA-WEn
CA-IORDn
CA-IOWRn
XIO-D10

CA-MIVAL
CA-MICLK
CA-A12
CA-A07
CA-A06
CA-A05
CA-A04
CA-A03
CA-A02
CA-A01
CA-A00
CA-D00
CA-D01
CA-D02
CA-WP

CA-CD1n
MDO3
MDO4
MDO5
MDO6
MDO7
CA-CE2n
CA-VS1n
CA-IORDn
CA-IOWRn
CA-MISTRT
CA-MDI0
CA-MDI1
CA-MDI2
CA-MDI3
+5VCA
CA-MDI4
CA-MDI5
CA-MDI6
CA-MDI7
MOCLK
CA-RST
CA-WAITn
CA-INPACKn
CA-REGn
MOVAL
MOSTRT
MDO0
MDO1
MDO2
CA-CD2n
71
72

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70

1X07
REF EMC HOLE

1X04
EMC HOLE

1X08
REF EMC HOLE

1X01
REF EMC HOLE

92789-055LF

10

+5V
RES 2F01

B01A

SPB SSB TV550


2K11 4DDR EU HF

2011-06-17

3139 123 6535


19106_001_110920.eps
110920

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 241

Flash

Flash

B01B

12

7F20
H27U4G8F2DTR-BC

37

100n

100n
2F21

2F20

+3V3

VCC

[FLASH]
4G 16
3F20-1 1

3F20-3 3

3F21-1 1

3F21-3 3

100R
3F20-2
100R
3F20-4
100R
3F21-2
100R
3F21-4

100R

100R

100R

100R

3F22-2
+3V3

XIO-OEn
XIO-WEn
NAND-WPn

3F23
3F22-4

100R
3F22-3 3
10K
3F22-1 1
5 100R

16
17
9
8
18
19
7

100R

100R
IF22

3F24

+3V3

NC

2K2

CLE
ALE
CE
RE
WE
WP
R
B

IF23
VSS
13

3F19

10K

NAND-RDY1n

0
1
2
3
IO
4
5
6
7

IF21

NAND-CE1n
NAND-CLE
NAND-ALE

29
30
31
32
41
42
43
44

36

XIO-D00
XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07

1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
25
26
27
28
33
34
35
38
39
40
45
46
47
48

+3V3

B01B

SPB SSB TV550


2K11 4DDR EU HF

2011-06-17

3139 123 6535


19106_002_110920.eps
110920

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 242

USB Hub

B01C

USB Hub

B01C

IF44

100n

2F25

+3V3

32
26
11

IF42

2 3F31-2 7
10K
IF32

+3V3
3F30

IF39
4 3F31-4 5

31
30
27
35
22
24
25

100n

100n
2F33

100n
2F32

100n
2F31

100n
2F30

1u0
2F29

2F28
XTALIN|CLKIN
XTALOUT

IF35

OSC1
USBDP_DN1|PRT_DIS_P1
USBDM_DN1|PRT_DIS_M1
BC_EN1|PWRTPWR1

RESET
OSC2
USBDP_DN2|PRT_DIS_P2
USBDM_DN2|PRT_DIS_M2
SUSP_IND|LOCAL_PWR|NON_REM0BC_EN2|PWRTPWR2
TEST

DP
USBUP
DM
VBUS_DET

OSC3
USBDP_DN3|PRT_DIS_P3
USBDM_DN3|PRT_DIS_M3
BC_EN3|PWRTPWR3

RBIAS
SDA|SMBDATA|NON_REM1
SCL|SMBCLK|CFG_SEL0
HS_IND|CFG_SEL1

NC

13
2
1
12

3F37

USB-DP

9F25

USB-DP2

USB-DM

9F26

USB-DM2

RES 9F29

USB-DP3

RES 9F30

USB-DM3

10K

IF36
17
4
3
16

USB-OC2n
USB-DP2
USB-DM2

+5V

IF37
19
7
6
18

USB-OC3n
USB-DP3
USB-DM3
4 3F34-4

8
9
20
21

FF33

+5V-USB2

100K
3 3F34-3 6

USB-OC2n

100K

10K

2 3F34-2 7

VIA
38
39
40
41

GND_HS
37

10K

IF41

12K IF40

3 3F31-3 6

28

+3V3

3F32

IF30

33

VDD_3V3

USB HUB

+T 0R3

10p

IF33

RESET-USBn

IF31

34

CR PLL
FILT

24M

IF34

USB-DP
USB-DM

36
23
15
5
10
29

1u0

100n
2F27

7F25
USB2513B-AEZG

2F35

10p

3F35

10K
2F34

4
2

1F25

14

3F28

+3V3

1M0

2F26

IF43

3F36

+3V3

USB-OC3n

100K
1 3F34-1 8

10K

SIDE USB

100K

1P08
+5V-USB2
USB-DM2
USB-DP2

FF36
FF37
5

FF32

1
2
3
4 IF45
6

5401

FF38
USB-DM3
USB-DP3

RES
1F24

+5V

FF39

1
2
3
4
5

FF30
FF31

6
7
502382-0570

SPB SSB TV550


2K11 4DDR EU HF

2011-06-17

3139 123 6535


19106_003_110920.eps
110920

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 243

SD Card

SD-Card

B01D

3F40
+3V3
22u 16V

+T
2F40

B01D

FF45

+3V3-SD

0R3

+3V3

3F41-4

IF47

47K

3 3F41-3 6

SDIO-DAT3

SDIO-DAT3

SDIO-CMD

SDIO-CMD

3F44-2

FF47

100R

3 3F43-3 6

47K

100R

3F45 RES

SDIO-CLK

SDIO-CLK

10K
2

3F41-2

47K

3F41-1

47K

1 3F42-1 8

1P09-1
FF48

SDIO-DAT0

SDIO-DAT0

SDIO-DAT1

SDIO-DAT1

SDIO-DAT2

SDIO-DAT2

47K

3F44-1
100R
3F43-2

+3V3-SD
8
FF49
FF41

100R

3 3F44-3 6

3F43-1
100R

FF42
FF43

3F42-2

3F42-3

FF46

1P09-2
7

SDIO-CDn

SDIO-CDn

FF44

SDIO-WP

SDIO-WP

FF50

47K
3

14
16

SCDA7A0200

100R

13
15

1
2
3
4
5
6
7
8
9

10
11
12
SCDA7A0200

47K

SPB SSB TV550


2K11 4DDR EU HF

2011-06-17

3139 123 6535


19106_004_110920.eps
110920

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 244

PNX85500 Control

PNX85500-Control

B01E

+3V3-STANDBY

3F67

IF50

512K
FLASH

BACKLIGHT-BOOST
7F53 RES
PDTA114EU

PNX-SPI-SDO
IF52

10K
RES

10K

3F66

IF53
1

PNX-SPI-CSBn
IF54

HOLD

+5V

PNX-SPI-CLK

PNX-SPI-WPn
+3V3-STANDBY
FF29

VSS

IF55

BOOST-PWM

IF61

7F54-1 RES
BC847BPN(COL) 6

7F54-2 RES
BC847BPN(COL)

SPI-PROG

IF56
4

IF57
FF04

47K

+3V3

+3V3

3F68 RES

3F52

7F52
M25P05-AVMN6

VCC
IF51

PNX-SPI-SDI

+3V3

100n
RES

100p

2F52

2F49

+3V3-STANDBY

10K

+3V3-STANDBY

2
1

IF62
SDM

FF58

1K0
RES

RES

3F69

10K

1u0

2F53

MAIN NVM

+3V3

RES

9CH0

10K

3F54

3F53

DEBUG ONLY
IF58

2F58 RES

IF59

1
2
3

0
1
2

SCL
ADR
SDA

100R
FF62

FF63

WC

RES
1F52

3F62

SDA-SSB

(8K 8)
EEPROM

3F63

100R

SCL

1
2
3

SDA
5

7
6
5

FF55

3F59
100R

3F60

SCL-UP-MIPS

FF56

SDA-UP-MIPS

100R

3F58

FF61

SCL-SSB

100n
7F58
10K

B01E

FF57

LEVEL

DEBUG / RS232 INTERFACE

TXD-UP
RXD-UP
RESET-STBYn
SPI-PROG

FF65

3F64

FF66

100R

SHIFTED

RES
1F51
FF64

3F65
100R

1
2
3
4
5

UP

FOR
DEBUG
USE ONLY

SPB SSB TV550


2K11 4DDR EU HF

2011-06-17

3139 123 6535


19106_005_110920.eps
110920

2011-Nov-04 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 245

Tuner

B01F

Tuner

B01F
IF10
IF11

15p

820R

2F65 RES

AF73

IF16
330n
3F82 RES

1p0

2F70 RES

2F62

220R

5F74

4 3F79-4

PNX-IF-N
IF79

3F81
220R

IF14

2F64

IF15

15p

IF-

10n

IF+

10n

2F91

* For BR NIM Tuner Only

3K3

3F78

470n

TUN-IF-P

5F70

TUN-IF-N

5F73

IF13

2F90

IF86

2F63

680n
2F66

10n

1K0
2F92

3F72

BA591

4K7

6F72

9F06

IF12

220R

5F66

3F80
+5V-TUN-PIN
3F71

9F05

47n

2F85

100p

2F73

2F72

9F02

10n

IF80

RES 5F76

AGC CONTROL

10n
+5V-TUN-PIN

9F03

10n

IF72

RES 2F95

100n

FF82

2F79

AF72

1 3F79-1
220R

10n
IF78

FF01

IF-AGC

IF76

2F82

VAGC

2F75

2p2
2F77

OUTPUT2

IF74

2F80

INPUT2

RES
2F76

OUTPUT1

5F71

IF77

INPUT1

GND2

IF81

10n
2F78

5
4

IF73

PNX-IF-P

3F77
4K7

IF-AGC

FF75

FF81

IF82

PNX-IF-AGC

100p

2F61

TUN-IF-N
TUN-IF-P

RES 2F96

100n
2F60

* 9F04

O1
O2

GND

RES 2F9D

RES 2F9C

RES 2F9B

RES 2F9A

RES 2F99

RES 2F98

RES 2F97
4n7

FF00

I
ISWI

2F74

VCC

IF75

X7251M
36M17

AF71
AF70

2F93

TUN-P6
TUN-P7

RES 2F59

RES 2F81

4n7

FF76

10n

GND1

9F00

6p8

6p8

6p8

6p8

6p8

6p8

6p8

1
2
3

FF74

+5V-TUN-PIN
7F75
UPC3221GV-E1

1F75

TUN-P1

2F71

9F01

NC

IF_OUT2

IF_OUT1

13

12

11

4MHZ_REF

14

10

I2C_SDA

B+_TUN
8

I2C_ADR
5

TUN

RF_AGC

B+_LNA

RF_IO

16

I2C_SCL

TUNER

15

FF71

1T01

RES

ATB2012
10n
IF89

15p

47R

2F86

3F75

15p

47R

IF87

TUN-P6
SDA-TUNER

2F94

IF88

IF90

SELECT-SAW

SCL-TUNER

TUN-P7

7F70
PDTC114EU

10n

3F76

RES

2F84

* For EU Hybrid Tuner Only


9F71
5F72 RES

1T01
2F61
2F62
9F02
9F03
9F04
9F05
9F06
2F73
2F82
2F72
2F80
2F77
5F71
5F74

Component
Europe
Brazil
TH26X3
FA23X7
4u7
RES
10p
5p6
Used
RE