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ODD SEMESTER

LAB MANUAL

(10B17EC271)

Engineering

ODD SEMESTER

Department of ECE

BasicElectronicsDevicesandCircuitLab:LabExperiments

1.

simple pn junction diode. Also determine the forward resistance of the diode.

2.

calculate its ripple factor and efficiency.

3.

(Use sinusoidal/square wave as an input signal.).

4.

zener diode. Also determine the breakdown voltage, static and dynamic

resistances.

5.

line regulation and load regulation.

6.

7.

To observe inverting and non inverting amplifier Configuration using Opamp IC 741.

8.

9.

10. To realize wein bridge oscillator circuit and calculate its frequency of

oscillation

ODD SEMESTER

PREFACE

The Basic Electronics Devices and Circuit Lab is one of the most important labs for electronics

engineering students. This is the first level laboratory in which students are introduced with

electronics for the first time and are trained with the preliminary of electronics. In this lab students

are given introduction and identification of different active and passive electronics

devices/components. They are familiarized with different signal sources and instruments used in

electronics engineering, students learn the usage/handling of different measuring instruments like

Digital mulitmeter, CRO, Function Generators, Regulated power supply etc. In this lab, students

become familiar with device characteristics and their applications. Students learn to work with

hand by making the circuit on bread board and analyzing it using laboratory instruments such as

digital multimeters (DMMs), power supplies, function generators and oscilloscopes. By the end of

their lab coursework, students become familiar with basic components such as resistors, diodes,

transistors, and operational amplifiers function and have the necessary skills of circuit designs.

A practical approach is probably the best approach to mastering a subject and gaining a clear

insight. List of experiments of Electronic Devices and Circuits lab covers those practical oriented

electronic circuits that are very essential for the students to solidify their theoretical concepts. This

provides a communication bridge between the theory and practical of the electronic circuits. This

is a one of most challenging laboratories in terms of utilization because students of all departments

use this lab.

Utilization

This lab is utilized for conducting the following course(s):

Electrical Circuit Analysis Lab (10B17EC171)

Basic Electronics Devices and Circuits lab (10B17EC271)

Digital Multimeter,

Regulated Power Supply,

Cathode Ray Oscilloscope (20 MHz),

Function Generator (1 MHz to 3MHz),

Project Bread Board

ODD SEMESTER

1. General Guidelines:

Be punctual in coming to the lab and be sincere in doing your lab work.

Before starting the lab experiment you must go through the lab manual of that experiment. Get

your doubts clear and then start.

Be careful to keep watch bands, rings, necklaces and the other metallic object out of contact with

live parts when working around electrical apparatus.

If you are not sure how to operate a piece of equipment then read the manual or take help from lab

staff/ teacher.

At the end of each lab period, return all the components and instruments that are issued to you or

your group.

Keep the work area neat and clean; arrange the stools before leaving the laboratory.

Make the circuit on the bread board and check for all the connections before switching ON the

supply.

Use the proper source (A.C or D.C) and the range of meters. Always try to vary the voltage

gradually.

Never exceed the permissible values of current, voltage of any machine, apparatus, wires, load etc.

Switch off the circuit while making any modification in the circuit.

When working with inductive and capacitive circuits, reduce voltages or current to near zero before

switching open the circuits.

While connecting the CRO and Function Generator with the circuits, always connect with proper

polarity of the BNC cable.

ODD SEMESTER

EXPERIMENT -1

AIM:

To study the forward and reverse bias (volt-ampere) characteristics of a simple p-n junction

diode. Also determine the forward resistance of the diode and develop a linearized model.

Sl No

Quantity

1.

Multimeter

01

2.

DC Regulated Supply

01

3.

PN Diode IN4007

01

4.

Resistor 1K

01

THEORY:

The diode is a semiconductor device formed from a junction of n-type and p-type semiconductor

materials. The lead connected to p-type material is called as anode and the lead connected to ntype material is called cathode.

When diode is in forward bias (higher potential is connected to the anode lead), current flows

through it. As the voltage across diode increases, current also increases. It is observed that the rate

of change in current increases with increase in the voltage across diode. After some potential drop

across the diode, the rate of change in current increases rapidly. The potential drop after which

current increases rapidly is called as Cut in Voltage. It is measured by drawing a tangent on the

slope of the V-I Characteristics from where current increases drastically. For Germanium diode is

it around 0.2-0.3V, while for Silicon diode it is 0.4-0.7V. When diode is in reverse bias (higher

potential is connected to the cathode lead), ideally no current flows through it, practically a very

small leakage current (in micro ampere) flows due to some impurity charge carriers. In the p-n

junction diode the value of reverse breakdown voltage is very high (-600V for 1N4001). If this

voltage is applied in the reverse bias, then very high value of current will flow and diode will get

ODD SEMESTER

damaged. The characteristic curve for an ideal diode and practical diode is shown in Fig 2.

Figure 2:

V-I characteristics of Ideal and Practical Diode

While analyzing circuits, the practical diode is usually replaced with a simpler model. In the

simplest form, the ideal diode is modeled by a switch as shown in Fig (3). The switch is closed

when the diode is forward biased and open when reverse biased. The real diode is modeled as

shown in Fig (4). Rf and Rr are the resistances offered by the diode in the forward bias and reverse

bias respectively. Vy is the cut-in voltage of the diode.

ODD SEMESTER

CIRCUIT DIAGRAM:

Figure5

PROCEDURE:

1.

2.

3.

4.

5.

6.

7.

8.

Study the characteristics of the diode in the data sheet. Copy all the specification for the diode

in your final lab report.

Connect the circuit as shown in Circuit Diagram

Connect voltmeter across diode and resistor respectively.

Vary the input voltage (as shown as 15Vdc in figure) from -5 to 5 volt in the step of 0.1 volt

and note down the reading across diode and resistor.

Calculate the current flowing through the resistance.

Now plot the graph between the current flowing through the diode and potential across the

diode.

From this graph, obtain the cut-in voltage for the diode. From the point where current

Increases sharply, draw a line to x-axis. The point where it intersects on the x-axis is called

cut-in voltage.

Measure the slope of the curve to calculate the resistance offered by the diode in the forward

bias as well as reverse bias. Forward bias resistance is named as Rf and reverse bias resistance

is named as Rr as shown in Fig4.

OBSERVATION:

Sr.

No.

Resistor

Voltage(Vr)

RESULTS:

Vy =

Rr =

Rf =

LEARNING OUTCOME

Current

(I)=Vr/R

Diode

Voltage(Vd)

Slope

( Vd/ I)

ODD SEMESTER

EXPERIMENT -2

AIM:

To observe the output waveform of half/full wave rectifier and calculate its ripple factor

and efficiency.

Sl No

Quantity

1.

Transformer (12-0-12)

01

2.

PN Diode

04

3.

Resistor 1K

01

4.

CRO

01

5.

Bread Board

01

6.

Connecting wires

THEORY:

Half wave and full wave bridge rectifier:

In half wave rectification, single diode act as a half wave rectifier. The A.C. supply to be rectified

is applied in series with diode and load resistance RL. A.C. supply is given through a transformer.

During positive half cycles of input A.C. voltage, this make diode forward biased and hence it

conducts current. During negative half cycles, diode is reverse biased and it conducts no current.

Therefore, current flow through the diode during positive half cycles of A.C. input voltage only. it

is blocked during negative half cycles.

Full wave bridge rectifier, current flow through the load in the same direction for both half cycles

of input A.C. its contain four diode D1, D2, D3, D4 connected to form bridge. The A.C supply to

be rectified is applied to the diagonally opposite end of the bridge trough the transformer. Between

two other ends of the bridge, the load resistance RL is connected. During the positive half cycle of

A.C. input voltage D1 & D3 forward biased while diode D2 &D4 are reversed biased. Therefore

only diode D1& D3 conduct. These two diode will be in series through the load. Current flow

through load. During negative half cycles diodes D2&D4 becomes forward biased whereas D1

and D3 become reverse biased. Therefore only D2&D3 conduct .these diodes will be in series

through the load RL. Current flow through lo

ODD SEMESTER

CIRCUIT DIAGRAM:

PROCEDURE:

1. Connect the circuit as shown in figure.

2. Apply A.C. supply through transformer;

3. Find the current through load resistance.

4. Observed voltage wave across the load on CRO.

4 find the value of ripple factor and efficiency Plot the graph between VBE and IB for VCE.

Ripple Factor

Efficiency, is the ratio of the dc output power to ac input power

Ripple Factor

The ripple factor for a Full Wave Rectifier is given by

Efficiency

Efficiency, is the ratio of the dc output power to ac input power.

RESULT:

Voltage wave form across the load:

Ripple factor:

Efficiency:

LEARNING OUTCOMES:

ODD SEMESTER

ODD SEMESTER

EXPERIMENT -3

AIM:

Realization of desired wave shapes using clipper and clamper circuits. (Use sinusoidal

/square wave as an input signal.).

SL. NO.

1.

2.

3.

4.

5.

6.

7.

8.

0.1 MFD capacitor

100 K ohm resistance

10 K ohm resistance

1 K ohm resistance

Diodes IN4007

DC Power Supply

Breadboard

Quantity

01

01

01

01

02

01

01

Connecting wires

THEORY:

The circuit with which the waveform is shaped by removing (or clipping) a portion of the input

signal without distorting the remaining part of the alternating waveform is called a clipper.

Clipping circuits are also referred to as voltage (or current) limiters, amplitude selectors, or slicers.

These circuits find extensive use in radars, digital computers, radio and television receivers etc.

In a clipping circuit, the output voltage will be proportional to the input voltage as long as the

input lies between the specified reference levels. Outside this range, the output is clipped it

remains essentially constant, no longer dependent on the input. Clipping circuits find important

uses in wave shaping and signal processing applications.

Often in the development of electronic circuits it is required that voltages be limited in some

manner to avoid circuit damage. Furthermore, the limiting or clipping of voltages can be very

ODD SEMESTER

useful in the development of wave-shaping circuits. A typical clipper circuit is shown in Figure 1.

In this circuit the output voltage can never be greater than 3 V. The ideal diode becomes forward

biased at Vo equal to 3 V and this ties the output directly to the 3 V supply. The waveform can be

clipped on the negative side by placing the series combination of a diode and power supply in

parallel with the diode and power supply already shown.

While clipper circuits are concerned primarily with limiting or cutting off part of the waveform,

clampers are used primarily to shift the DC level. For example, if we have a clock signal that

swings between 0v and 5V but our application requires a clock signal from -5V to 0V, we can

provide the proper DC offset with a passive clamper circuit. A typical clamper circuit is shown in

Figure 2. For this circuit to work properly the pulse width needs to be much less than the RC time

constant of 10 ms. The input square wave with a frequency of 1 KHz and a pulse width of 0.5 ms

meets this requirement. The diode and power supply as shown will prevent the output voltage

from exceeding 3 V (i.e., all of the region above 3 V can be viewed as a forbidden region for

output voltage). Because of the time constant requirement the voltage across the capacitor cannot

change significantly during the pulse width, and after a short transient period the voltage across

the capacitor reached a steady state offset value. The output voltage is simply the input voltage

shifted by this steady state offset. Also, observe that the peak-to-peat output voltage is equal to the

peak-to-peak input voltage. This is true because the voltage across the capacitor cannot change

instantaneously and the full change of voltage on the input side of the capacitor will likewise be

seen on the output side of the capacitor.

ODD SEMESTER

PROCEDURE:

A. Clipper Circuits:

A.1: Connect the circuit in Figure 3.1 and set the input voltage Vs to a 1 kHz sine wave of at least

1V peak amplitude. Sketch the shape of the output voltage waveform for this "clipper" circuit.

A.2: Add a dc voltage source V1 as shown in Figure 3.2 to the circuit, and set the input signal to

a 10kHz triangular wave of 20 volts peak to peak. Vary V1 over the range 0 to 15 volts. For

each value of V1 , observe and sketch the output waveform .

A.3: Add a second diode and voltage source V2 (Figure 3.3). Connect V2 in the polarity shown

or you might burn the diodes! Experiment with different levels of V1 and V2. Make sketches and

comment. This circuit is similar to the limiting circuits used in FM radio receivers.

Set V1 to about +8V and reverse the polarity of V2 to a positive voltage of +5V. V1 and V2

now have the same polarity. (Note: V2 must be less than V1, or you

will burn the diodes). Sketch the waveform. Comment.

A.4: Connect the circuit in Figure 3.4. Let VS be a 1 kHz triangular wave with

amplitude of 20 V peak to peak. Sketch 3 output waveforms with differentvalues of V1

between 1V and 10 V.

ODD SEMESTER

Fig 3.1

Fig 3.2

Fig 3.3

Fig 3.4

B. Clamper Circuits:

B.1: Connect the circuit shown in Figure 4.1. Set Vi to a 50 Hz triangular wave with a peak

amplitude of 10V. Draw the output waveform.

B.2: Connect the circuit shown in Figure 4.2. Set Vi to a 50 Hz square wave with a peak

amplitude of 12V. Draw the output waveform.

0.1F

0.1F

Fig: 4.1

Fig: 4.2

OBSERVATIONS:

Draw the Output waveforms of the clipper circuit as obtained in steps A.1 to A.4, and the output

waveforms of the clamper circuits as obtained in steps B.1 and B.2.

RESULTS:

a). Did the outputs of the clipper circuits in the steps A.1 to A.4 of the procedure work as

expected?

b). Did the outputs of the clamper circuits in the steps B.1 to B.2 of the procedure work as

expected?

LEARNING OUTCOMES

ODD SEMESTER

EXPERIMENT - 4

AIM:

To study the forward and reverse bias volt-ampere characteristics of a zener diode. Also

determine the breakdown voltage, static and dynamic resistances.

SL. NO.

Quantity

1.

01

2.

Resistance 1K

01

3.

BreadBoard

01

4.

DC Power Supply

01

5.

Multimeter

01

6.

Connecting wires

THEORY:

The circuit diagram to plot the VI characteristics of a zener diode is shown. Zener diode is a

special diode with increased amounts of doping. This is to compensate for the damage that occurs

in the case of a pn junction diode when the reverse bias exceeds the breakdown voltage and

thereby current increases at a rapid rate.

Applying a positive potential to the anode and a negative potential to the cathode of the zener

diode establishes a forward bias condition. The forward characteristic of the zener diode is same

as that of a pn junction diode i.e. as the applied potential increases the current increases

exponentially. Applying a negative potential to the anode and positive potential to the cathode

reverse biases the zener diode.

As the reverse bias increases the current increases rapidly in a direction opposite to that of the

positive voltage region. Thus under reverse bias condition breakdown occurs. It occurs because

there is a strong electric filed in the region of the junction that can disrupt the bonding forces

within the atom and generate carriers. The breakdown voltage depends upon the amount of

doping. For a heavily doped diode depletion layer will be thin and breakdown occurs at low

reverse voltage and the breakdown voltage is sharp. Whereas a lightly doped diode has a higher

breakdown voltage. This explains the zener diode characteristics in the reverse bias region.

The maximum reverse bias potential that can be applied before entering the zener region is called

the Peak Inverse Voltage referred to as PIV rating or the Peak Reverse Voltage Rating (PRV

rating)

CIRCUIT DIAGRAM (REVERSE BIASE):

ODD SEMESTER

ODD SEMESTER

PROCEDURE:

1. Connect the circuit as shown in figure.

2. Apply DC supply as shown in the figure.

3. Measure the value of VZ and IZ, VR Reverse biased.

4. Reapeat the all step with opposite polarity of zener diode.

5 Measure the value of VZ and IZ, VF Reverse biased.

6 Plot the curve between Voltage and current for forward and reverse biased zener diode.

OBERVATION:

S.No

Forward biased

VF

VZ

IZ

Reverse biased

VR

VZ

IZ

1

2

3

5

RESULT:

Plot for reverse biased and forward biased zener diode: Break down voltage value:

Static resistance = Vz/Iz

Dynamic resistance value: change in zener voltage/change in current through zener diode.

LEARNING OUTCOMES:

ODD SEMESTER

EXPERIMENT: 5

AIM:

To study Zener voltage regulator and calculate percentage regulation for line regulation and

load regulation

SL.

NO.

Quantity

1.

01

2.

01

3.

Multimeter

01

4.

01

5.

01

6.

Connecting wire

THEORY:

Voltage Regulator:

A voltage regulator circuit is required to maintain a constant dc Output voltage across the load

terminals in spite of the variation:

Change in the load current

The voltage regulator circuit can be designed using zener diode. For that purpose, zener diode is

operated always in reverse biased condition. Here, zener is operated in breakdown region and is

used to regulate the voltage across a load when there are variations in the supply voltage or load

current.

The general circuit diagram for the zener voltage regulator is shown below.

ODD SEMESTER

It consists of a current limiting resistor RS connected in series with the input voltage VAA and

zener diode is connected in parallel with the load RL in reverse biased condition. The output

voltage is always selected with a breakdown voltage Vz of the diode.

The input source current, IS = IZ + IL.. (1)

The drop across the series resistance, Rs = Vin Vz .. (2)

And current flowing through it, Is = (Vin VZ) / RS .. (3) From

equation (1) and (2), we get, (Vin - Vz )/Rs = Iz +IL (4)

Regulation with a varying input voltage (line regulation): It is defined as the change in regulated

voltage with respect to variation in line voltage. The minimum value of input after which

regulation will start is given by the following formula.

RL*Vin(Min)/(RL + Rs) > VZ.

Once the zener enter into breakdown, the output voltage will be maintained at VZ. Since loads

resistance is constant so, the load current remains constant and as the input voltage increases, form

equation (3) Is (current in series resistance) also varies accordingly. Therefore, zener current Iz

will increase. The extra voltage is dropped across the Rs. Since, increased Iz will still have a

constant Vz and Vz is equal to Vout. The output voltage will remain constant.

The maximum value of Vin is decide by the IZmax as as given below.

Vin(Max) Vz = RS(I L+IZmax)

IL = VZ/RL

Regulation with the varying load (load regulation): It is defined as change in load voltage with

respect to variations in load current. To calculate this regulation, input voltage is constant and

output voltage varies due to change in the load resistance value. The minimum value of load

resistance after which regulation will start is given by the following formula.

RLMIN*Vin/(RLMIN + Rs) > VZ.

The left side of the equation (4) is constant as input voltage Vin, IS and Rs is constant. As load

current changes due to change in the value of resistance RL, the zener current Iz will also change

but in opposite way such that the sum of Iz and IL will remain constant. When Load resistance is

more then the RLMIN, load current decreases since output voltage is Constant at VZ. Due to this

Zener current must increase in order to satisfy eq. 1. The maximum value of load resistance is

decided by the Maximum current capability of the zener i.e. IZMAX

Vin Vz = RS(ILMin+IZmax)

ILMIN = VZ / RLMAX

ODD SEMESTER

PROCEDURE

A) Line Regulation:

1. Make the connections as shown in figure below.

2. Keep load resistance fixed value at 5K (By using variable resistance Pot); vary DC input

voltage from 0V to 10V.

3. Note down output voltage and zener current.

OBSERVATION TABLE:

Vary input signal from 0 to 10 with step size of 1V and measure the output voltage and the

current through the zener diode. Then calculate the value of IS and IL using the formula given

below and verify the equation 1.

S.No

1

2

.

10

VAA (Input

Voltage) V

Vout (Output

Voltage)

Zener Current

(IZ) mA

IL (mA) IS(mA)

IL=Vout/RL, IS=(VAA Vout)/Rs,

Plot: Plot the Vout versus VAA on graph sheet.

%

Regulation

(Use Eq. 5)

ODD SEMESTER

B) Load Regulation:

1. For finding load regulation, make connections as shown in figure below.

2. Keep input voltage at 8V; vary load resistance value from minimum to Maximum

3. Note down output voltage and zener current.

OBSERVATION TABLE:

Fixed the input voltage at 8V. Vary load resistance from Minimum to Maximum of the given

10K Pot, with step size of 50 in the range of (Minimum to 200 ), then with step of 100 till

5K and measure the output voltage and the current through the zener diode.

S.No

1

2

.

10

RL

()

Vout

(Output Zener Current (IZ) IL

Voltage)

mA

(Vout/RL)

Eq. 6

Plot: Plot the (a) Vout versus RL and (b) Vout versus IL on graph

sheet.

LEARNING OUTCOMES:

Iz+IL

%

Regulation

(Use Eq. 6)

ODD SEMESTER

EXPERIMENT: 6

AIM:

To plot input/output characteristics of a common emitter npn BJT.

SL. NO.

1.

2.

3.

4.

5.

Transistor BC547

Resistors : 1K and 10K

DC power supply

Digital multi-meters

Breadboard

Quantity

01

01

01

01

01

THEORY:

A transistor is a three terminal device. The terminals are emitter, base, collector. In common

emitter configuration, input voltage is applied between base and emitter terminals and output is

taken across the collector and emitter terminals. Therefore the emitter terminal is common to both

input and output

The input characteristic resembles that of a forward biased diode curve. This is expected since the

Base-Emitter junction of the transistor is forward biased. As compared to CB arrangement IB

increases less rapidly with VBE. Therefore input resistance of CE circuit is higher than that of CB

circuit.

The output characteristics are drawn between Ic and VCE at constant IB. the collector current Ic

varies with VCE upto few voltage only. After this the collector current becomes almost constant

and independent of VCE. The value of VCE upto which the collector current changes with VCE is

known as knee voltage. The transistor always operates in the region above knee voltage. Ic is

always constant and is approximately equal to IB.

The current amplification factor of CE configuration is given by

= IC/IB

ODD SEMESTER

CIRCUIT DIAGRAM:

INPUT CHARACTERISTIC

PROCEDURE:

1) Connect the circuit as per the circuit diagram

2) For plotting the input characteristics the output voltage VCE is kept constant at 1V and for

different values of VBE . Note down the values of IB

3) Repeat the above step by keeping VCE at 2V and 4V.

4) Tabulate all the readings.

5) Plot the graph between VBE and IB for constant VCE.

OBSERVATION TABLE:

SL.

NO.

VCE=

VBE

VCE=

IB

VBE

VCE=

IB

TABLE-1

VBE

IB

ODD SEMESTER

MODEL GRAPH

OUTPUT CHARACTERISTIC

PROCEDURE:

1) Connect the circuit as per the circuit diagram.

2) For plotting the output characteristics the input current IB is kept constant at 10A and for

different values of VCE note down the values of IC.

3) Repeat the above step by keeping IB at 20 A 40 A.

OBSERVATION TABLE:

SL.

NO.

IB1=10 A

VCE(mv)

IC(mA)

IB2=20 A

VCE(mv)

IC(mA)

TABLE-2

IB3=40A

VCE(mv)

IC(mA)

ODD SEMESTER

MODEL GRAPH

RESULT:

LEARNING OUTCOME:

ODD SEMESTER

EXPERIMENT: 8

AIM:

To Observe inverting and Non inverting amplifier Configuration using Op-amp IC741.

SL. NO.

Quantity

1.

Op Amp IC -741

2.

3.

Function Generator

4.

5.

CRO

6.

Bread Board

7.

Connecting wires

THEORY:

Figure shows a inverting amplifier. The o/p Voltage Vo is of the opposite polarity as the input

voltage Vin. The input signal is applied directly to the inverting (-ve) input terminal of the

amplifier and the feedback resistance is also connected between the output terminal, the ve input

terminal and ground.

The Gain of the Inverting Amplifier can be set below unity i.e. 1. Hence the inverting amplifier

configuration with feedbacks lends itself to a majority of applications as against those of the non

inverting amplifier.

Closed Loop Voltage Gain (AF):

The closed-loop voltage gain AF can be obtained by writing Kirchoffs Current equation at the

input node V2 as follows:

Iin = IF + IB .(1)

Since Ri is very large, the input bias current IB is negligibly small. For instance,

Ri = 2MW and IB = 0.5A for 741C. Therefore,

Iin IF

That is,

Vin V2 V2 V0

=

...........................(2)

R1

RF

However,

V1 V2 = Vo/A

Since V1 = 0V,

V2 = VO/A

ODD SEMESTER

Vin + Vo / A (V 0 / A) V0

=

R1

RF

V

AR F

AF = 0 =

.......... .......... ......(3)

Vin R1 + R F + AR1

Since the internal gain A of op-amp is very large (ideally infinity), AR1 >> R1 + RF.

Therefore equ. (3) can be rewritten as,

AF =

CIRCUIT SYMBOL

VO

R

= F (ideal)

Vin

R1

ODD SEMESTER

PROCEDURE:

1. Make the connections as per the circuit diagram.

2. Apply the i/p to the Inverting terminal and obtain the output on the CRO.

3. Take various readings by varying the input voltage and hence calculate the gain.

4. Calculate the gain using formula.

R

AF = F (Theoretica l )

R1

V

AF = O (Pr actical )

V in

ODD SEMESTER

OBSERVATION TABLE:

SR.

NO.

1

2

3

4

Vin (volts)

VO (volts)

AF= - Rf/Ri

(Theoretical)

AF= VO/Vin

(Practical)

RESULT:

Voltage Gain of the Inverting amplifier depends only on the feedback components and is

independent of the internal gain A of the op-amp. The value of AF can be less than unity. The

Theoretical and Practical values of the Gain are nearly matching.

THEORY:

Figure shows a non-inverting amplifier. The o/p Voltage Vo is of the same polarity as the input

voltage Vin. The input resistance of the non-inverting amplifier is very large (100MW) in this

case. The input signal is applied directly to the non-inverting (+ve) input terminal of the amplifier

and the feedback resistance are connected between the output terminal, the ve input terminal and

ground.

The Minimum Gain of the Non-Inverting Amplifier is 1.

Closed Loop Voltage Gain (AF):

AF = Vo/Vin

However, Vo = A (V1 V2)

Referring to figure,

V1 = Vin

V2 = VF =

R1.V0

(R1 + RF )

since Ri >>> R1

Therefore,

V0 = A(Vin

R1VO

R1 + RF

Rearranging, we get

VO =

Thus

A(R1 + RF ) Vin

R1 + RF + AR1

ODD SEMESTER

AF =

VO

A (R1 + R F )

=

V in

R1 + R F + AR 1

AR1>>(R1 + RF) and (R1 + RF + AR1) AR1

Thus

AF =

CIRCUIT DIAGRAM:

VO

R

=1+ F

V in

R1

(ideal)

ODD SEMESTER

PROCEDURE:

1. Make the connections as per the circuit diagram.

2. Apply the i/p to the Non-Inverting terminal and obtain the output on the CRO.

3. Take various readings by varying the input voltage and hence calculate the gain.

4. Calculate the gain using formula.

AF = 1 +

AF =

RF

R1

VO

Vin

(Practical)

OBERVATION TABLE:

SR.

NO.

1

2

3

4

Vin (volts)

VO (volts)

RESULT:

LEARNING OUTCOMES:

AF=1+(RFRI)

(Theoretical)

AF= VO/VIN

(Practical)

ODD SEMESTER

EXPERIMENT: 8

AIM:

To realize an adder and substractor circuits using Op-amp.

SL NO

Quantity

1.

IC741

01

2.

Resistance 1K

04

3.

DC Power Supply

01

4.

Multimeter

01

5.

Bread Board

6.

Connecting Wires

THEORY:

ADDER :

Op-amp can be used to design a circuit whose output is the sum of several input signals. Such a

circuit is called a summing amplifier or an adder. Summing amplifier can be classified as inverting

& non-inverting summer depending on the input applied to inverting & non-inverting terminals

respectively. Circuit Diagram shows a non-inverting adder with n inputs. Here the output will be

the linear summation of input voltages. The circuit can be used either as summing amplifier,

scaling amplifier, or as averaging amplifier.

From the circuit of adder, it can be noted that at pin3 I1+I2+I3+.In=0

V a V1 V a V 2 V a V 3

V Vn

+

+

=0

.......... ....... a

R

R

R

R

(V + V 2 + V 3 + .......... . + V n )

nV a 1

=0

R

V + V 2 + V 3 + .......... ...... + V n

Va = 1

=0

R

Rf

V a

V O = 1 +

R1

R f V1 + V 2 + V 3 + .......... ... + V n

V O = 1 +

R

n

V + V 2 + V 3 + .......... .... + V n

= 1 + (n 1) 1

V + V 2 + V 3 + .......... ........ + V n

= n 1

V O = V1 + V 2 + V 3 + .......... ......... + V n

ODD SEMESTER

This means that the output voltage is equal to the sum of all the input voltages.

SUBSTRACTOR

A subtractor is a circuit that gives the difference of the two inputs,

Vo =V2-V1, Where V1 and V2 are the inputs. By connecting one input voltage V1 to inverting

terminal and another input voltage V2 to the non inverting terminal, we get the resulting circuit

as the Subtractor. This is also called as differential or difference amplifier using op-amps.

Output of a differential amplifier (subtractor) is given as

Vo = (-Rf/R1) (V1-V2)

If all external resistors are equal in value, then the gain of the amplifier is equal to -1. The

output voltage of the differential amplifier with a gain of -1 is

Vo = (V2-V1)

Thus the output voltage Vo is equal to the voltage V2 applied to the non inverting

terminal minus the voltage V1 applied to the inverting terminal. Hence the circuit is called a

Subtractor.

RESULT:

LEARNING OUTCOMES

ODD SEMESTER

ODD SEMESTER

EXPERIMENT: 9

AIM:

To realize integrator and differentiator circuit using IC-741.

SL NO.

Apparatus and components required

1.

CRO

Quantity

01

2.

Function Generator

01

3.

01

4.

02

5.

IC741

01

THEORY:

Integrator:

A circuit in which the output voltage is the integration of the input voltage is called an

integrator.

In the practical integrator to reduce the error voltage at the output, a resistor R F is connected

across the feedback capacitor CF. Thus, RF limits the low-frequency gain and hence minimizes

the variations in the output voltage.

ODD SEMESTER

The frequency response of the integrator is shown in the fig. 2.1. fb is the frequency at which the

gain is 0 dB and is given by

fb = 1/2 R1Cf.

In this fig. there is some relative operating frequency, and for frequencies from f to

fa the gain RF/R1 is constant. However, after fa the gain decreases at a rate of 20 dB/decade.

In other words, between fa and fb the circuit of fig. 2.1 acts as an integrator. The gainlimiting frequency fa is given by

fa = 1/2 RfCf.

Normally fa<fb. From the above equation, we can calculate Rf by assuming fa & Cf.

This is very important frequency. It tells us where the useful integration range starts.

If fin < fa

If fin = fa

If fin = 10fa

Hz. Hence the input frequency is to be taken as 500Hz to get 99% accuracy results.

ODD SEMESTER

INTEGRATOR:

EXPECTED WAVEFORM

PROCEDURE:

1. Connect the components/equipment as shown in the circuit diagram.

2. Switch ON the power supply.

3. Apply sine wave at the input terminals of the circuit using function Generator.

4. Connect channel-1 of CRO at the input terminals and channel-2 at the output

terminals.

5. Observe the output of the circuit on the CRO which is a cosine wave (90o phase

shifted from the sine wave input) and note down the position, the amplitude and the

time period of Vin & Vo.

6. Now apply the square wave as input signal.

7. Observe the output of the circuit on the CRO which is a triangular wave and note

down the position, the amplitude and the time period of Vin & Vo.

8. Plot the output voltages corresponding to sine and square wave inputs.

ODD SEMESTER

DIFFERENTIATOR:

As the name suggests, the circuit performs the mathematical operation of

differentiation, i.e. the output voltage is the derivative of the input voltage.

Both the stability and the high-frequency noise problems can be corrected by the

addition of two components: R1 and Cf, as shown in the circuit diagram. This circuit is a

practical differentiator.

The input signal will be differentiated properly if the time period T of the input

signal is larger than or equal to RfC1. That is, T>= RfC1

Differentiator can be designed by implementing the following steps.

1. Select fa equal to the highest frequency of the input signal to be differentiated.

2. Then, assuming a value of C1<1 F , calculate the value of Rf

3. Calculate the values of R1and Cf so that R1C1=RfCf.

ODD SEMESTER

PROCEDURE:

1. Connect the components/equipment as shown in the circuit diagram.

2. Switch ON the power supply.

3. Apply sine wave at the input terminals of the circuit using function Generator.

4. Connect channel-1 of CRO at the input terminals and channel-2 at the output

Terminals.

5. Observe the output of the circuit on the CRO which is a cosine wave (90o phase

Shifted from the sine wave input) and note down the position, the amplitude and the

time period of Vin & Vo.

6. Now apply the square wave as input signal.

7. Observe the output of the circuit on the CRO which is a spike wave and note down

the position, the amplitude and the time period of Vin & Vo.

8. Plot the output voltages corresponding to sine and square wave inputs.

EXPECTED WAVEFORM

RESULT:

LEARNING OUTCOME

ODD SEMESTER

EXPERIMENT: 10

AIM:

To realize wein bridge oscillator circuit and calculate the frequency of oscillation.

APPARATUS AND COMPONENTS REQUIRED:

SL NO.

Apparatus and components required

1.

CRO

Quantity

01

2.

IC741

01

3.

04

4.

Capacitor .047f

01

5.

Connecting wires

DESCREPTION:Fig-1 or Fig-2 is the circuit of the Wien bridge oscillator ( as these two circuits are same). A

resistor R4 is connected to the inverting terminal (2) of the operational amplifier from the ground.

Similarly a parallel combination of a resistance R2 and a capacitor C2 is connected to the noninverting terminal (3) of the operational amplifier from the ground. The output terminal (6) of the

amplifier is fed back to inverting terminal (2) through a variable resistor R3. A series combination

of a resistance R1 and a capacitor C1 is connected between non-inverting terminal (3) and the

output of operational amplifier. To observe the out put wave form, the output terminal (6) is

connected to CRO Y- Plates phase terminal and the other terminal of CRO is grounded. The

terminals (7) and (4) of the op. amp. are connected to +12 V and -12 V of the D.C. power supplies

separately.

CIRCUIT DIAGRAM

ODD SEMESTER

THEORY:A Wien bridge oscillator is a type of electronic oscillator that generates sine waves without having

any input source. It can output a large range of frequencies. The bridge comprises four resistors

and two capacitors.

An oscillator consists of an amplifier and a feedback network.

1. 'Active device' i.e. Op Amp is used as an amplifier.

2. Passive components such as R-C or L-C combinations are used as feedback net work.

To start the oscillation with the constant amplitude, positive feedback is not the only sufficient

condition. Oscillator circuit must satisfy the following two conditions known as Barkhausen

conditions:

i. The first condition is that the magnitude of the loop gain (A) =1 A

= Amplifier gain and = Feedback gain.

ii. The second condition is that the phase shift around the loop must be 360 or 0.

The feedback signal does not produce any phase shift. This is the basic principle of a Wien

bridge oscillator

ODD SEMESTER

LEAD LAG CIRCUIT:The given circuit shows the RC combination used in Wien bridge oscillator. This circuit is also

known as lead-lag circuit. Here, resistor R1 and capacitor C1 are connected in the series while

resistor R2and capacitor C2 is connected in parallel.

Working of lead lag circuit:- At higher frequencies the reactance of capacitor C1 and C2

approaches zero. These causes C1 and C2 appear shot. Here capacitor C2 shots the resistor R2.

Hence the output voltage Vo will be zero since output is taken across R2 and C2 combined so at

high frequencies, circuits acts as a lag circuit.

At low frequencies, both capacitors act as open because capacitor offers very high

reactance. Again output voltage will be zero because the input signal is dropped across the R1 and

C1combination. Here, the circuit acts like a 'lead circuit'.

But at one particular frequency between the two extremes, the output voltage reaches to the

maximum value. At this frequency only, resistance value becomes equal to capacitive reactance

and gives maximum output. Hence, this particular frequency is known as resonant frequency or

oscillating frequency.

The maximum output would be produced if R = Xc.

R = XC =

1

2fC

f =

1

HZ

2RC

Due to limitations of the op-amp, frequencies above 1MHz are not achievable.

The basic version of Wien Bridge has four arms. The two arms are purely resistive and

other two arms are frequency sensitive arms. These two arms are nothing but the lead-lag circuit.

The series combination of R1 and C1 is connected between terminal a and d. The parallel

combination of R2 and C2 is connected between terminals D and C. So the two circuits (Fig.1 and

Fig.2) are same except in shape.

ODD SEMESTER

Here, bridge does not provide phase shift at oscillating frequency as one arm consists of lead

circuit and other arm consists of lag circuit. There is no need to introduce phase shift by the

operational amplifier. Therefore, non inverting amplifier is used.

PROCEDURE:Connect the circuit is as shown in the Fig-1. Keep the resistance and capacitor values R1 = R2 = R and

C1 = C2 = C and switch on the power. Adjust the voltage sensitivity band switch and time base band

switch such that at lea st two or more complete sine waves are observed on the screen of CRO. Also

adjust the resistance R3 value till the wave formed on the CRO screen is stationary. Note R and C

values in the table and measure the peak to peak horizontal length (l) of one sine wave. Multiply this

value with the corresponding time-base (t) value. This product ( l x t ) gives the time period (T) of the

generated sine wave. The reciprocal of time period gives the experimental frequency of the sine wave.

On substitution of Rand C values in the above equation, it gives theoretical frequency. The theoretical

and experimental frequencies are equal. The experiment is repeated by changing the value of R or C.

OBSERVATIONS:

Table:

RESULTS:

LEARNING OUTCOMES:

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