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Formal Verification Based

Automated Approaches To SOC


DFT Logic Verification
Subir K. Roy
Rubin A. Parekhji
Texas Instruments
Bangalore, India
(Presenter : Sarveswara Tammali)
DAC User Track 2009 Poster Session

Motivation
Automate integration verifications of DFT
Logic and IPs towards
Cycle time reduction in verification by
minimizing usage of simulation based
SOC level verification requirements.
(Minimum 2X)
Si quality improvement by elimination of
all connectivity logic related bugs.
Deployment through common
infrastructure
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Simulation vis--vis FV

Limitations of Simulation - Limited input test


vectors/ Manual test bench creation / Only end-toend bugs found Larger debug time/ Larger
regression runtimes

Advantages of formal verification - No test bench


generation/ Comprehensive verification and
coverage/ Faster verification/ Properties are
generic/ Pin-points source of bug

Issues in FV Intrinsic capacity limitations (1000


flops) => Rules out use of embedded
memory/memory models/IPs => Needs
partitioning and abstraction.

SOC DFT Logic Structure &


Different types of Integration
SOC DFT Logic Structure & Behavior
Canonical & Regular Largely Independent of SOC
Reasonably generic nature of its interconnection

to rest of logic in SOC

Different Types of Integration


Static integration

Example : Pure connectivity

Dynamic integration

Temporal (Example : Pipeline registers in DPs)

Functional (Example : Switching between functional


and test modes)
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Case Study in Pure Connectivity Verification


SOC design complexity

Total IPs in the design = 42

Total Instances at top level = 117

Total integration bugs found by simulation = 180

Total effort = 6 months/8 persons (1136 man days)

Total PSL assertions for CBA sub-system = 6480

Total FV runtime = 180 minutes (3-4 secs/property)


Bug Classes

Total/%

Specification

18/10%

Pure
Connectivity

150/83.33%

Non-IP SOC
logic

12/6.66%

Results
FV performance boost on the CBA
Sub-system - 33X
FV performance boost on the whole
SOC (extrapolated) - 38X

Advantages of using FV for SoC Level


Connectivity checks
Modeling and property generation are simple
Allows concurrent efforts on RTL flow and

Connectivity verification flow


Can be used very early in the design cycle to

extract maximum benefit, as it does not require


RTL to be complete or functionally mature.
Can be carried out selectively on sub-systems

with high bug risks due to variability in choosing


IP configurations (Eg. Auto-generated
parameterized/configurable IPs)
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FV of Memory Data Path (Dynamic Integration - Temporal)

Flow of Data between PBIST Controller


And Embedded Memories

Automated Flow
Command Line Arg

Input_Info.xls

script

Generated
Properties &
FV env

FV of Testmode Entry Sequence


(Dynamic Integration - Functional)
SOC Top Level Verification Approach Through Partitioning

RST
nRESET
TDI

Icepick Top

DFT

Icepick Cntr

TCK
TMS

FSM
Jtag Reg Mod
TM Reg

CVL

Decode
logic

TM

SOC MDP + Test Mode Entry Sequence Results


IPs/
Subsystems

Properties

Pass

Fail

148

144

68

67

1344

1312

32

158

155

1363

1324

37

48

46

670

660

10

172

168

38

33

10 (Hard IP)*

29

21

11 (Hard IP)*

29

25

12 (Hard IP)**

NA

NA

NA

13 (Hard IP)**

NA

NA

NA

14 (Hard IP)**

NA

NA

NA

Total

4067

3906

161

* - Only Pure Connectivity Checks


** - Connectivity information unavailable
during first iteration of DFT FV

Block Level /
Connectivity

Properties

Verification

Average

CPU
Time

FlipFlops

[mins.]

ICEPick IP

61

170

38

JTAG Regs

10

90

20

Connectivity

14

In one SoC MDP, due to a


wrongly placed inverter, writeenable pin of a memory was not
being de-asserted properly
caught by de-assertion property

WZ0

Wrongly
Placed
Inverter

Mux

Reg

Mux

Reg

twen
Should be
here

RGS
CSR

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Automated DFT FV Regression Flows


DFT logics to be verified

IFV

IFV

Types of DFT checks to be performed


(Connectivity/MDP/Safe Val/TME/TAM etc.)

IFV

IFV

FV
Regression
Runs

Individual
Run
Reports

Consolidated
Regression
Report
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Summary
For standardized SOC connectivity and DFT

logic architecture formal verification can be


easily automated and extremely efficient
Enormous Reduction in Verification Cycle Time
+ High Quality Verification.
Person month reduction to complete DFT FV

after deployment of automation :


For Large Sized SOCs --- Factor of 4
Only 1 resource needed.
[Acknowledgement : Thanks to Bijitendra Mittra, Amit Roy, Supriya
Bhattacharjee, Deepanjan Roy and Lopamudra Sen from Interra India
Private Limited, Bangalore]
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