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# Home Work-2

ARCHITECTURE

## REGD NO- 10806601

PART-A
Q1. Design a four bit combinational circuit incrementer and decrementer using full adders.

Q2. Register A holds the 8 bit binary 11011001. Determine the B operand and the logic
micro operations to be performed in order to change the value in A to

## a) the given register has 8-bit: 11011001. This is the value of A

B3
the requirement is the b’s operand. With the help of the givenoutput and the a’s value. The output
is -01101101,
A
a’s value-- 11011001

## in the following function the XOR function is applied:

a(+)b -- 01101101

## b) the given input of the a is 11011001

the b’s input is put. 10110100 then we get 11111101 by using the or operation we can get the
required output

a -- 11011001

b --00100100

## the output will get as following OR AVB

A or B 11111101

Q3. Starting from initial value of R=11011101, determine the sequence of binary values in R
after a logic shift left followed by circular shift right, followed by a logical shift right and a
circular shift

## The above shifting is complete

PART-B

Q4. Determine the micro operation that will be executed in the processor when following 14
bit control words are applies

(a) 00101001100101
(b) 00000000000000

(a) 00101001100101:

r1 r2 r3 sub

## micrOoperation = r3 r1— r2

(b) 00000000000000:

microoperation:

output  input

## Q5.Convert the following arithmetic expressions from infix to RPN

(a) A*B+C*D+E*F
(b) A*B+A*(B*D+C*E)
(c) A+B*[C*D+E*(F+G)]
(d) A*[B+C*(D+E)]
F*(G+H)

A*B+C*D+E*F

A*B+C*D+EF*

A*B+C*DEF*+

A*B+CD*EF*+

AB*CD*EF*++
A*B+A*(B*D+C*E)

A*B+A*(BD*CE*+)

A*B+A(BD*CE*+)*

AB*A(BD*CE*+)*+

AB*ABD*ACE*+*+

A + B* [ C * D + E * ( F + G )]

A +B *[C * D + E * F G + ]

A + B * [ C D * + E * F G +]

FG+E*CD*+B*A+

A*[B+C*(D+E)]

F*(G+H))

A*[B+C*(D+ E)]FGH+*/

A*[B+ CD E+*]FGH+*/

ABCDE +*+*FGH+*/

## Q6. Convert the following from RPN to infix

(a) ABCDE+*-/
(b) ABC*/D-EF/+

ABCDE+*-/

ABCD+E *-/

ABC*D+E-/

A B – C * ( D + E) /

A/B–C*(D+E)

ABC*/D -EF/+

AB*C/D–EF/+

A/B*CD–EF/+

A / (B * C – D) E F / +

A / (B * C – D) E / F +

A / (B * C) – D + E / F