Investigation of Ultra-thin BOX Junctionless Transistor at

Channel Length of 20 nm
Chitrakant Sahu, Student Member, IEEE

Jawar Singh, Member, IEEE

P.N. Kondekar, Member, IEEE

Department of
Electronics and Communication Engg.
PDPM IIITDM, Jabalpur, India
Email: chitrakant@iiitdmj.ac.in

Department of
Electronics and Communication Engg.
PDPM IIITDM, Jabalpur, India
Email: jawar@iiitdmj.ac.in

Department of
Electronics and Communication Engg.
PDPM IIITDM, Jabalpur, India
Email: pnkondekar@iiitdmj.ac.in

AbstractSilicon-on-insulator junctionless transistor (SOI-JLT) have

been considered a promising candidate to extend planer CMOS scaling. This technology allows significant improvement of the transistors
electrostatic control and variability below 20 nm regime. This paper
presents ultra-thin back oxide (BOX) SOI-JLT device with gate length
of 20 nm. We reported that thin BOX is effective in adjusting threshold
voltage (Vth ) by means of BOX thickness scaling and substrate doping
concentration. Its characteristics like ION /IOF F , DIBL and subthreshold
slope are investigated in detail as BOX thickness varied from 5 nm
to 50 nm with substrate doping variation from 1016 cm3 to 1019
cm3 . The simulation results show ION /IOF F ratio improved by factor
1.2 104 (NJLT) and 6 103 (PJLT) with BOX thickness scaling from
50 nm to 5 nm at substrate doping 1019 cm3 . Threshold voltage is
increased by 427 mV (NJLT) and 421 mV (PJLT), while DIBL variation
is reduced by 71 mV /V (NJLT) and 83 mV /V (PJLT) with less than 5%
variation in subthreshold swing for both NJLT and PJLT. An inverter
circuit is designed and simulated based on the concept of ultra thin BOX
junctionless transistor. The transistor operation is in accumulation mode,
different from the conventional CMOS devices with inversion mode of
operation. Simulations results show good DC and transient characteristics
for gate length of 20 nm and 10 nm at Vdd = 0.9 V .

Junctionless transistors (JLTs) are being studied as a promising

candidate for replacement of conventional metal oxide semiconductor field-effect-transistor (MOSFET) in sub-20 nm channel length
regime. JLTs have many advantages over conventional MOSFETs
such as better short-channel effects (SCEs) performance which includes reduced drain induced barrier lowering (DIBL) and less
subthreshold slope (SS) degradation. As a result, it yields better
scalability, less sensitive to mobility degradation, better negative bias
thermal instability, greatly simplified process flow and low thermal
budgets after gate formation [1]. JLTs have homogeneous and uniform
doping throughout the source-channel-drain regions. The OFF state of
the device is attained by fully depleting the channel region and in the
ON state the channel is either in flat band or in accumulation region.
The JLT needs to be highly doped to ensure a high current level with
low source/drain contact resistance and small cross section is required
for full depletion of carriers at OFF state. The electrical properties
ultra-thin-boby (UTB) SOI-JLT are reported in [2] which included
effect of BOX thickness and substrate doping on threshold voltage
with different substrate bias for long channel JLT. In [3] impact of
BOX thickness scaling on 30 nm gate length FDSOI MOSFETs
analyzed and observed variation in threshold voltage, subthreshold
slope and drive current. Comparison of thick and thin BOX is also
provided in [4].
Device structure and inverter circuit simulation: Figure 1 shows
both p-type (left) and n-type (right) SOI-JLT. These are uniformly
doped, i.e. the source, drain, and the channel have identical doping
with concentration Nd = 1019 cm3 (NJLT) and Na = 1019 cm3
(PJLT) at channel length Lg = 20 nm and thickness Tsi = 5 nm.

978-1-4673-2523-3/13/$31.00 2013 IEEE

The gate metal is complementary p+ poly-silicon for n-type channel

and n+ poly-silicon for p-type channel separated from the channel
by a thin SiO2 dielectric of thickness Tox = 1nm. Substrate is
doped with p-type material (NJLT) and n-type material (PJLT) having
concentration Nsub = 1019 cm3 . 2-D numerical device simulations
are performed for both devices using ATLAS simulator [5]. The
simulations are carried out using two carriers fermi-dirac model without impact ionization to account for highly doped channel, band-gap
narrowing (BGN), schottky read hall (SRH) and auger recombination
models are included in simulations. The mobility model includes both
doping and transverse-field dependence.
Figure 2 show variation of Vth and ION /IOF F ratio with different
substrate concentration (1016 to 1019 cm3 ) and BOX thickness
scaling (50 to 5 nm). ION and IOF F current are observed at Vgs =
0 V and Vgs = 0.9 V with Vds = 0.9 V . Vth shift around 427 mV
(NJLT) and 421 mV (PJLT) is observed when BOX is scaled 50
nm to 5 nm even when the substrate voltage is fixed at ground for
substrate doping 1019 cm3 . IOF F current is drastically reduced by
5104 times (NJLT) and 105 times (PJLT) also ION current reduced
8 times (NJLT) and 5 times (PJLT). Thus ION /IOF F ratio increased
from 4.6 103 to 5.6 107 (NJLT) and 2 104 to 1.4 108 (PJLT)
with BOX thickness scaling from 50 nm to 5 nm at Nsub = 1019
cm3 . From Figure 3 we observed that SS is a weak function of low
substrate doping and thick back oxides but degrades somewhat as
the BOX thickness is lowered down to 5 nm. At large doping levels
1019 cm3 , the inverse subthreshold slope is 97 mV /dec (NJLT)
and 96 mV /dec (PJLT) at Lg = 20 nm and TBOX = 5 nm. Hence,
3% (NJLT) and 5% (PJLT) variation in subthreshold swing is due to
increase of BOX capacitance and can be adjusted by proper substrate
doping level. The DIBL is defined as the difference in threshold
voltage extracted at Vds = 0.04 V and Vds = 0.9 V and normalized
by this difference of drain voltage. Figure 3 clearly shows that the
DIBL can be reduced by increasing substrate doping and by reducing
BOX thickness. As compared to extremely thick BOX, a superior
short-channel control is achieved at UTB. A clear improvement of
electrostatic control is observed in JLTs with DIBL 69 mV /V (NJLT)
and 78 mV /V at UTB with 1019 cm3 .
Figure 4 and 5 show the Id -Vg and Id -Vd of p-channel(left) and nchannel(right) SOIJLT with Lg = 20 nm. The simulation parameters
are Nd = Na = Nsub = 1019 cm3 , TBOX = 5 nm and Tox =
2 nm. Vth is increased due to BOX thickness scaling and high
substrate doping concentration. This increase in Vth can be adjusted
by two method (a) workfunction engineering (b) oxide thickness
variation. High work function 5.3 eV (NJLT) and 4.1 eV (PJLT) gate
metal requires expensive material and process steps in fabrication but

proposed device structure reduces process cost and complexity by use

of small work function 5.1 eV (NJLT) and 4.2 eV (PJLT) metal gate.
Second method of Vth adjustment is to increase oxide thickness (Tox
= 2 nm) that will reduce tunneling leakage current as compare to (Tox
= 1 nm) used for thick BOX device. It also relaxes the requirement
of ultra thin oxide layer to some extent in device fabrication. The
inverter proposed is designed by connecting drain and gate terminal
of both NJLT and PJLT similar to CMOS technology and inverter
characteristics are obtained by ATLAS mixed mode simulation [5].
Figure 6 shows transfer and transient characteristics of inverter with
Lg = 20 nm and 10 nm, respectively. Good switching characteristic
is observed at load capacitance of 3 f F . The fast transient behavior
for the inverter is observed at Lg = 10 nm as compared to 20 nm.
UTB SOI-MOSFET suffer from large delay due to low current and
large oxide capacitance (at Tox = 1 nm) but proposed deice have
large drain current and small oxide capacitance (at Tox = 2 nm).
Hence, it speeds up inverter performance.
In summary, impact of BOX thickness scaling and substrate
doping concentration on short channel junctionless transistor characteristics is observed. Increased Vth due to TBOX and Nsub variation
can be adjusted by choosing the appropriate set of workfunction
gate metal and oxide thickness. Also a new-type of inverter with
UTB junctionless transistor is simulated, it exhibits features of good
ION /IOF F ratio, better short channel control, and Vth tuning ability.
This inverter will be a good candidate for future generation low power
CMOS applications.

Fig. 1.

Fig. 3.

SS and DIBL Vs substrate doping profile with BOX scaling.

Fig. 4.

Transfer characteristics of NJLT(right) and PJLT(left)

Device structure of PJLT(left) and NJLT(right).

Fig. 5.

Output characteristics of NJLT(right) and PJLT(left).

Fig. 2. Vth and ION /IOF F Vs substrate doping profile with BOX scaling.

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Fig. 6. Inverter DC and transient characteristics at Lg = 20 nm and Lg =

10 nm.

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