Lecture 5

VLSI Circuit Design
Lecture 5: Circuit Operation of

CMOS Inverter
Dr. Ke Huang
COMPE 572
VLSI Circuit Design
Fall 2015
9/8/2015
COMPE 270 Digital Systems
Project assignments
You will have 4 project assignments in total
No dedicated lab sessions, i.e., you need to perform
labs and write lab reports on your own time
The lab assignments are performed by groups of 2 or 3
students, find your team members!
Log into Blackboard account for tutorial and

assignment info
9/8/2015
What you should do

1. Find your colleagues to form your groups (2 or 3
students per group)
2. Log into your SDSU student account and run the
simulation tools as shown in the tutorials
3. Log into your Blackboard account to read lab tutorials
and assignment info
4. Perform your lab projects, write your report (one
report per group), and return your report by the due
date specified on your blackboard account, section
Important Dates
9/8/2015
Review
Power dissipation of logic inverter
Propagation delay of logic inverter
Power-delay and energy-delay products
Digital IC technologies and logic-circuit families
9/8/2015

Inverter implementation
Load capacitance in complemented inverter
Dynamic power dissipation: during switch activities due to capacitance
9/8/2015

Dynamic power dissipation
Equivalent circuits for calculating the dynamic power dissipation
for complemented inverter
goes from high to low
9/8/2015

Instantaneous power
Energy delivered by the power
supply to charge the capacitor
Charge delivered to the capacitor
9/8/2015

Charge in the capacitor after switch
Total energy delivered by the
power supply
Energy stored in the capacitor
Energy dissipated by the resistance
9/8/2015

goes from low to high
1
2
1
2
2
2
Energy stored in the capacitor goes from
to 0,
dissipated
9/8/2015
10

Energy dissipated per inversion cycle
Input
Output
2
Energy dissipated in the resistance per cycle is
2
Dynamic power dissipation of the inverter:
Q: How to reduce dynamic power dissipation of inverter
9/8/2015
11

Propagation delay for input pulse with finite (nonzero) rise and fall
times
9/8/2015
12

Power-delay product (PDP)
Power-delay product (PDP): a figure of merit for comparing logiccircuit technologies
Dynamic power of CMOS
PDP of CMOS
PDP of CMOS at maximum frequency
9/8/2015
13

Energy-delay product (EDP)
Energy-delay product (EDP): another figure of merit for comparing
logic-circuit technologies
9/8/2015
14
IC technologies and logic-circuit families

Digital IC technologies and logic-circuit families
Digital IC technologies and logic-circuit families chart
9/8/2015
15
Learning objectives
Static circuit operation of CMOS inverter
Voltage-transfer characteristic of CMOS inverter
Unmatched CMOS inverter
9/8/2015
16
Circuit operation of CMOS inverter

Circuit-level diagram of CMOS inverter
9/8/2015
17

Circuit operation of CMOS inverter: when input is high
= : NMOS in saturation or
triode region
= 0: PMOS in cut-off region, then
=0
= 0: NMOS not connected to ,
NMOS in triode region
9/8/2015
18

On resistance of NMOS in triode region: a review
=
1 2
[ ]
[ ]
often neglected
9/8/2015
19

Equivalent circuit of CMOS inverter with high input
No current flowing in the circuit:

No static power dissipation
9/8/2015
20

Equivalent circuit of CMOS inverter with low input
9/8/2015
21
Learning objectives
9/8/2015
22
VTC of CMOS inverter

Voltage-Transfer Characteristic of CMOS inverter
When < tn , is off and is in triode

region, no current
When is slightly greater than tn , current is
small small voltage drop on ,
value is large is in saturation region
When continues to increase, current
increases, , decreases and |, |
increases, at some point both and are in
saturation region
Similarly, when continues to increase,
turns to triode, turns to saturation
region
When | | < tp , is in triode region
and is off
9/8/2015
23

Equivalent circuit of CMOS inverter with low input
9/8/2015
24

Noise margins: review
Important parameters of the voltage transfer characteristics of
the logic inverter
: Output low level
: Output high level
: Maximum value of input
interpreted by the inverter as a
logic 0
: Minimum value of input
interpreted by the inverter as a
logic 1
: Noise margin for low input
: Noise margin for high input
9/8/2015
25
Digital logic inverter

Noise margins: review
Formal definitions of the threshold voltages and
9/8/2015
26

Formal definition of noise margin in CMOS inverter
9/8/2015
27

1 2
=
2
1

2
PMOS in saturation region
If NMOS and PMOS match

= =
1 2 1
=
2
2
9/8/2015
28

1 2 1
=
2
2
Differentiating both sides relative to results in

+
=
in which we substitute = and
=
2
= 1, then we obtain
9/8/2015
29

Substituting = and = in
2
1 2 1
= 2
2
2
we have
1
= (5 2 )
8
Similarly, we can obtain
1
= (3 + 2 )
8
9/8/2015
30

Determination of noise margin in CMOS inverter
9/8/2015
31
Learning objectives
9/8/2015
32

Advantage of having matched inverters
Both low and high inputs can have the same tolerance for noise
9/8/2015
33

1 2
=
2
1

2
PMOS in saturation region
If NMOS and PMOS match

= =
1 2 1
=
2
2
9/8/2015
34

Penalties for having matched inverters
Width of the p-channel device can be three to four times as
large as that of the n-channel device, since is much
smaller than larger silicon area
Increased device capacitances increase in the propagation
delay
It is useful to design unmatched CMOS inverter
9/8/2015
35

Design of unmatched CMOS inverter
1
=
2
1
=
2
( )2
( | |)2
9/8/2015
36

1
)2 =
( | |)2
Substituting = = , we have
+
=
+1
where
=
9/8/2015
37

+
+1
= , =
If we want to keep the same minimum length =
Both PMOS and NMOS are fabricated on the same substrate same
We can change and to control , thus the value of
9/8/2015
38

+
=
+1
=
often 3 to 4 times smaller than

What happens if we reduce , say by a factor of 3?
9/8/2015
39
Summary

Lecture 5

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Lecture 5

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VLSI Circuit Design

Lecture 5: Circuit Operation of

COMPE 270 Digital Systems

Log into Blackboard account for tutorial and

COMPE 270 Digital Systems

What you should do

COMPE 270 Digital Systems

Digital IC technologies and logic-circuit families

COMPE 270 Digital Systems

Power dissipation of logic inverter

Dynamic power dissipation: during switch activities due to capacitance

COMPE 270 Digital Systems

Power dissipation of logic inverter

goes from high to low

COMPE 270 Digital Systems

Power dissipation of logic inverter

Charge delivered to the capacitor

COMPE 270 Digital Systems

Power dissipation of logic inverter

Energy dissipated by the resistance

COMPE 270 Digital Systems

Power dissipation of logic inverter

goes from low to high

COMPE 270 Digital Systems

Power dissipation of logic inverter

Q: How to reduce dynamic power dissipation of inverter

COMPE 270 Digital Systems

Propagation delay of logic inverter

COMPE 270 Digital Systems

Power-delay and energy-delay products

COMPE 270 Digital Systems

Power-delay and energy-delay products

COMPE 270 Digital Systems

IC technologies and logic-circuit families

COMPE 270 Digital Systems

COMPE 270 Digital Systems

Circuit operation of CMOS inverter

COMPE 270 Digital Systems

Circuit operation of CMOS inverter

COMPE 270 Digital Systems

Circuit operation of CMOS inverter

COMPE 270 Digital Systems

Circuit operation of CMOS inverter

No current flowing in the circuit:

COMPE 270 Digital Systems

Circuit operation of CMOS inverter

COMPE 270 Digital Systems

COMPE 270 Digital Systems

VTC of CMOS inverter

When < tn , is off and is in triode

COMPE 270 Digital Systems

VTC of CMOS inverter

COMPE 270 Digital Systems

VTC of CMOS inverter

COMPE 270 Digital Systems

Digital logic inverter

COMPE 270 Digital Systems

VTC of CMOS inverter

COMPE 270 Digital Systems

VTC of CMOS inverter

NMOS in triode region

PMOS in saturation region

If NMOS and PMOS match