A Low Power and High Speed Level Shifter with Delay Circuits

Jia Yaoyao, Zhang Leiming, Chen Yiwen, Fang Jian, Zhang Bo

University of Electronic Science and Technology of China, Chengdu, Sichuan, 610054, China
Henan University of Science and Technology, Luoyang, Henan, 471003, China

annajyy116@gmail.com

AbstractA level shifter with low power and high speed

characteristics is proposed, which is simulated in the 0.18m
standard CMOS process. The proposed level shifter minimizes
the contention problem between the pull-up PMOS transistors
and pull-down NMOS transistors by using delay circuits.
Compared with the conventional level shifter, the simulation
results show that the proposed level shifter can achieve about
42.8% power reduction, 6.7% falling time of output level signal
saving and 20.0% high-to-low propagation delay speed-up for
the output load capacitance in the range of 0.2pF to 2pF when
converting 1.8V to 3.3V. Besides, the proposed level shifter has
about 38.4% improvement in the overall performance. Hence,
the proposed level shifter is suited for low power, high speed
applications.

supply VDDL and ground and provides the complementary

input signals. The cross-coupled pair of PMOS transistors
acts as the circuit load. When the output level signal at one
side is pulled low, then the opposite PMOS transistor will be
turned on, and the complimentary output level signal at the
other side will be pulled high. Below the cross-coupled pair
of PMOS transistors, the two NMOS transistors are
controlled by the complementary input signals.

I. INTRODUCTION

ITH the wide application of portable electronic

systems, power consumption has become a critical
design concern in todays VLSI circuits and system designs,
which drives numerous research efforts to address power
reduction techniques [1-3]. One of the most common
techniques for low power design is the multiple supply
voltages technique [4]. It is possible that the output of the
low-voltage circuit connects directly to the input of the
high-voltage circuit. However, there exists a static current
flowing from the applied voltage supply to ground, which
causes substantial power consumption [5]. To solve this
problem, a level shifter is used for modifying the voltage
levels at the interface of low-to high voltage blocks [6]. Due
to the fact that level shifter also has power consumption,
switching time and propagation delay which are the result of
contention problem between the pull-up PMOS transistors
and the pull-down NMOS transistors, the methods of
reducing the contention problem are of importance in level
shifter with low power consumption and high speed [7-8].
In this paper, a novel level shifter with delay circuits is
proposed. Adding extra cross-coupled pair of PMOS
transistors to reduce the contention problem, the proposed
level shifter achieves superior power-delay product.

Fig.1. The conventional Level Shifter

When input signal IN is a logic low level, MN1 is in cutoff

while MN2 is biased in active and provides a conducting path
to ground. This will pull the node OUT down to ground,
which in turn bias MP1 into conduction. When the input
signal IN is switched to logic high level, the operation of the
conventional level shifter is forced to reverse state [9].
However, the conventional level shifter has relatively high
power consumption, long switching time and propagation
delay due to the contention problems at nodes OUT and OUT
between pull-up transistor MP1/MP2 and pull-down
transistor MN1/MN2, which leads to high transient current
during the transient switching.
III. THE PROPOSED LEVEL SHIFTER

II. THE CONVENTIONAL LEVEL SHIFTER

The conventional level shifter is shown in Figure 1. In this
circuit, there is an inverter, two cross-coupled PMOS
transistors MP1 and MP2, and two NMOS transistors MN1
and MN2. The inverter is connected between the voltage
This work was supported in part by the Power Integrated Technology Lab
of University of Electronic Science and Technology of China.
.

978-1-4799-3051-7/13/$31.00 2013 IEEE

The proposed level shifter, shown in figure 2, employs the

same cross-coupled pair of PMOS transistors (MP1, MP2) as
the conventional level shifter, however, by adding the extra
cross-coupled pair of PMOS transistors (MP3, MP4) and
resistances R1 and R2. The upper cross-coupled pair of
PMOS transistors (MP3, MP4) are placed above the lower
cross-coupled pair of PMOS transistors (MP1, MP2) to
reduce the contention problem at the nodes OUT and OUT

378

by delaying the switching time of MP3/MP4 compared to

MP1/MP2 respectively. Furthermore the delay circuits are
composed of the resistance R1/R2 and the gate capacitance of
MP4/MP3 (Cop4 /Cop3) respectively.

time of the output level signal and the high-to-low

propagation delay. In short, it is clear that the output level
signal transition and the propagation delay are speed up based
on the delay circuits. As such, the proposed level shifter can
reduce the contention problem between pull-up PMOS
transistors and pull-down NMOS transistors to make power
saving.
IV.

Fig.2. The proposed Level Shifter.

To analyze the proposed level shifter, it is necessary to

consider the both conditions of the input signal IN. When the
input signal IN swings from low to high, MN1 turns on and
MN2 turns off. The node OUT is then discharged to ground.
The ground level on the node OUT turns MP2 and MP4 on,
but the turn-on time of MP4 is delayed due to the delay circuit
composed of R1 and Cop4. After that, the node OUT then will
be charged to high level. In branch (MP4, MP2, MN2), it is
possible to set the delay time by modifying R1 to make the
turn-on time of MP4 stagger the turn-off time of MN2. Hence,
the contention between the pull-up PMOS transistors (MP4,
MP2) and the pull-down NMOS transistor MN2 can be
weakened. Since the short circuit current flowing through the
branch (MP4, MP2, MN2) during the transition switching is
much smaller in the proposed level shifter, the power saving
in the proposed level shifter is superior to the conventional
level shifter. However, it is further seen that the rising time of
the output level signal and the low-to-high propagation delay
are increased in the proposed level shift compared to the
conventional level shifter due to the delayed turn-on time of
MP4.
For the inverse condition, when the input signal IN swings
from high to low, MN1 turns off and MN2 turns on. The node
OUT is then discharged toward low level. The low level at the
node OUT turns MP1 on and makes MP3 turn on later. Thus
the node OUT will then be charged to high level. The high
level at the node OUT turns MP2 and MP4 off, but the
turn-off time of MP4 is delayed. After that, the node OUT
then will be further discharged to ground. In the branch (MP4,
MP2, MN2), since part of charges can be extracted through
MP4 to VDDH during the delayed turn-off time of MP4, the
proposed level shifter will achieve reduction in the falling

SIMULATION RESULTS AND ANALYSIS

The proposed level shifter and the conventional level

shifter are optimized and simulated for output load
capacitance in the range of 0.2pF to 2pF, using the 0.18m
standard CMOS process. In the simulation, a 500KHz input
signal IN, swinging between 0V to 1.8V, is applied through
an inverter since the output signal of the inverter is more
realistic in an actual design. The output level signal, swinging
between 0V and 3.3V is obtained at the node OUT.
Figure 3 shows the power consumption versus the different
output load capacitances for the proposed level shifter and the
conventional level shifter. The proposed level shifter has
increase in power consumption with the increasing output
load capacitance because it takes PMOS transistors more time
to turn off for the increasing output load capacitance. Owing
to the delayed switching time of MP3 and MP4 respectively,
the convention problem during the transition is reduced
significantly. Hence the proposed level shifter gives better
performance in power saving for all output load capacitances
and the maximum power reduction is 42.8% at the 0.2pF load
capacitance.

Fig.3. The power consumption versus output load capacitance.

Figure 4 presents the switching time of output level signal

at the node OUT, including the rising time and the falling time,
versus the different output load capacitances for the proposed
level shifter and the conventional level shifter. In figure 4(a),
the rising time of the proposed level shifter is longer than that
of the conventional level shifter and the maximum is to 7.4%
at 0.3pF load capacitance due to the delayed turn-on time of
MP4 caused by R1 and Cop4. In figure 4(b), it can be seen that
the maximum saving in falling time of the proposed level
shifter is to 6.7% at 1.5pF load capacitance since part of
charges being extracted through MP4 to VDDH before MP4
turns off.

379

(a) The rising time versus output load capacitance.

(b) The high-to-low propagation delay versus output load capacitance.
Fig.5. The propagation delay versus output load capacitance.

Figure 6 displays the products of the power consumption

times the switching time of the output level signal times the
propagation delay versus the different load capacitances for
the proposed level shifter and the conventional level shifter.
In figure 6, it can be seen that the overall performance of the
proposed level shifter has improved to about 38.4%.

(b) The falling time versus output load capacitance.

Fig.4. The switching time of output level signal versus output load
capacitance.

Figure 5 describes the propagation delay versus the

different load capacitances for the proposed level shifter and
the conventional level shifter. Figure 5(a) compares the
low-to-high propagation delay of the two level shifters. It is
noted that the low-to-high propagation delay of the proposed
level shifter is delayed compared to the conventional one and
the maximum is about 26.1% at the 0.3pF load capacitance,
which is caused by R1 and Cop4. In figure 5(b), due to the
discharging process in advance through MP4, the proposed
level shifter can achieve about 20.0% saving in high-to-low
propagation delay at the 0.2pF load capacitance.

Fig.6. The product of power consumption, switching time and propagation

delay versus output load capacitance.

V.

CONCLUSION

This paper presents a novel high performance level shifter

for driving load capacitance from 0.2pF to 2pF. The proposed
level shifter weakens the contention problem between the
pull-up PMOS transistors and pull-down NMOS transistors
by delay circuit. Under the condition of VDDL=1.8V,
VDDH=3.3V power supplies, the proposed level shifter
achieves the maximum power reduction of 42.8%, the
maximum falling time saving of 6.7%, the maximum
high-to-low propagation delay decrease of 20.0% and the
maximum overall performance improvement of 38.4%.
Therefore, the proposed level shifter is suitable for using in
low power, high speed applications.
(a) The low-to-high propagation delay versus output load capacitance.

380

ACKNOWLEDGMENT
The authors wish to thank Gu Hongbo and Zheng
Xiaochen for the valuable discussions. Besides, the authors
also want to thank the other colleagues in the Power
Integrated Technology Lab of UESTC for their help.
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