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First block (block address 00h) is valid when shipped from factory with ECC. For minimum required
ECC, see Error Management.
RESET (FFh) required as first command after power-on
Alternate method of device initialization after power up (contact factory)
Internal data move operations supported within the
plane from which data is read
Quality and reliability
Data retention: JESD47G-compliant; see qualification report
Endurance: See Qualification Report
Operating voltage range
VCC: 2.73.6V
VCC: 1.71.95V
Operating temperature:
Commercial: 0C to +70C
Industrial (IT): 40C to +85C
Package
48-pin TSOP type 1, CPL 2
63-ball VFBGA
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Notes:
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
A WP xx
Micron Technology
xx
ES
:E
Design Revision (shrink)
Product Family
Production Status
Blank = Production
ES = Engineering sample
Density
MS = Mechanical sample
4G = 4Gb
QS = Qualification sample
Device Width
08 = 8-bit
Blank
16 = 16-bit
A = SLC
Classification
Mark Die
B
Speed Grade
nCE
RnB
I/O Channels
Blank
Package Code
Operating Voltage Range
A = 3.3V (2.73.6V)
B = 1.8V (1.71.95V)
Interface
Feature Set
A = Async only
E = Feature set E
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Contents
General Description ......................................................................................................................................... 8
Signal Descriptions ........................................................................................................................................... 8
Signal Assignments ........................................................................................................................................... 9
Package Dimensions ....................................................................................................................................... 12
Architecture ................................................................................................................................................... 14
Device and Array Organization ........................................................................................................................ 15
Asynchronous Interface Bus Operation ........................................................................................................... 17
Asynchronous Enable/Standby ................................................................................................................... 17
Asynchronous Commands .......................................................................................................................... 17
Asynchronous Addresses ............................................................................................................................ 19
Asynchronous Data Input ........................................................................................................................... 20
Asynchronous Data Output ......................................................................................................................... 21
Write Protect# ............................................................................................................................................ 22
Ready/Busy# .............................................................................................................................................. 22
Device Initialization ....................................................................................................................................... 27
Power Cycle Requirements .............................................................................................................................. 28
Command Definitions .................................................................................................................................... 29
Reset Operations ............................................................................................................................................ 32
RESET (FFh) ............................................................................................................................................... 32
Identification Operations ................................................................................................................................ 33
READ ID (90h) ............................................................................................................................................ 33
READ ID Parameter Tables .............................................................................................................................. 34
READ PARAMETER PAGE (ECh) ...................................................................................................................... 36
Parameter Page Data Structure Tables ............................................................................................................. 37
READ UNIQUE ID (EDh) ................................................................................................................................ 40
Feature Operations ......................................................................................................................................... 41
SET FEATURES (EFh) .................................................................................................................................. 41
GET FEATURES (EEh) ................................................................................................................................. 42
Status Operations ........................................................................................................................................... 45
READ STATUS (70h) ................................................................................................................................... 45
READ STATUS ENHANCED (78h) ................................................................................................................ 46
Column Address Operations ........................................................................................................................... 47
RANDOM DATA READ (05h-E0h) ................................................................................................................ 47
RANDOM DATA READ TWO-PLANE (06h-E0h) ............................................................................................ 48
RANDOM DATA INPUT (85h) ...................................................................................................................... 49
PROGRAM FOR INTERNAL DATA INPUT (85h) ........................................................................................... 50
Read Operations ............................................................................................................................................. 52
READ MODE (00h) ..................................................................................................................................... 54
READ PAGE (00h-30h) ................................................................................................................................ 54
READ PAGE CACHE SEQUENTIAL (31h) ...................................................................................................... 55
READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 56
READ PAGE CACHE LAST (3Fh) .................................................................................................................. 58
READ PAGE TWO-PLANE 00h-00h-30h ....................................................................................................... 59
Program Operations ....................................................................................................................................... 61
PROGRAM PAGE (80h-10h) ......................................................................................................................... 62
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. 62
PROGRAM PAGE TWO-PLANE (80h-11h) .................................................................................................... 65
Erase Operations ............................................................................................................................................ 67
ERASE BLOCK (60h-D0h) ............................................................................................................................ 67
ERASE BLOCK TWO-PLANE (60h-D1h) ....................................................................................................... 68
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
List of Figures
Figure 1: Marketing Part Number Chart ............................................................................................................ 2
Figure 2: 48-Pin TSOP Type 1, CPL (Top View) ................................................................................................ 9
Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View) ........................................................................................ 10
Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View) ...................................................................................... 11
Figure 5: 48-Pin TSOP Type 1, CPL ............................................................................................................... 12
Figure 6: 63-Ball VFBGA ................................................................................................................................ 13
Figure 7: NAND Flash Die (LUN) Functional Block Diagram ............................................................................ 14
Figure 8: Array Organization MT29F4G (x8) ................................................................................................. 15
Figure 9: Array Organization MT29F4G (x16) ................................................................................................ 16
Figure 10: Asynchronous Command Latch Cycle ............................................................................................ 18
Figure 11: Asynchronous Address Latch Cycle ................................................................................................ 19
Figure 12: Asynchronous Data Input Cycles .................................................................................................... 20
Figure 13: Asynchronous Data Output Cycles ................................................................................................. 21
Figure 14: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 22
Figure 15: READ/BUSY# Open Drain .............................................................................................................. 23
Figure 16: tFall and tRise (3.3V V CC) ................................................................................................................ 24
Figure 17: tFall and tRise (1.8V V CC) ................................................................................................................ 24
Figure 18: IOL vs. Rp (VCC = 3.3V V CC) .............................................................................................................. 25
Figure 19: IOL vs. Rp (1.8V V CC) ....................................................................................................................... 25
Figure 20: TC vs. Rp ....................................................................................................................................... 26
Figure 21: R/B# Power-On Behavior ............................................................................................................... 27
Figure 22: RESET (FFh) Operation .................................................................................................................. 32
Figure 23: READ ID (90h) with 00h Address Operation .................................................................................... 33
Figure 24: READ ID (90h) with 20h Address Operation .................................................................................... 33
Figure 25: READ PARAMETER (ECh) Operation .............................................................................................. 36
Figure 26: READ UNIQUE ID (EDh) Operation ............................................................................................... 40
Figure 27: SET FEATURES (EFh) Operation .................................................................................................... 42
Figure 28: GET FEATURES (EEh) Operation .................................................................................................... 42
Figure 29: READ STATUS (70h) Operation ...................................................................................................... 46
Figure 30: READ STATUS ENHANCED (78h) Operation ................................................................................... 46
Figure 31: RANDOM DATA READ (05h-E0h) Operation ................................................................................... 47
Figure 32: RANDOM DATA READ TWO-PLANE (06h-E0h) Operation .............................................................. 48
Figure 33: RANDOM DATA INPUT (85h) Operation ........................................................................................ 49
Figure 34: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation .............................................................. 51
Figure 35: READ PAGE (00h-30h) Operation ................................................................................................... 55
Figure 36: READ PAGE CACHE SEQUENTIAL (31h) Operation ......................................................................... 56
Figure 37: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 57
Figure 38: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 58
Figure 39: READ PAGE TWO-PLANE (00h-00h-30h) Operation ........................................................................ 60
Figure 40: PROGRAM PAGE (80h-10h) Operation ............................................................................................ 62
Figure 41: PROGRAM PAGE CACHE (80h15h) Operation (Start) ..................................................................... 64
Figure 42: PROGRAM PAGE CACHE (80h15h) Operation (End) ...................................................................... 64
Figure 43: PROGRAM PAGE TWO-PLANE (80h11h) Operation ....................................................................... 66
Figure 44: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 67
Figure 45: ERASE BLOCK TWO-PLANE (60hD1h) Operation .......................................................................... 68
Figure 46: READ FOR INTERNAL DATA MOVE (00h-35h) Operation ................................................................ 70
Figure 47: READ FOR INTERNAL DATA MOVE (00h35h) with RANDOM DATA READ (05hE0h) ..................... 70
Figure 48: PROGRAM FOR INTERNAL DATA MOVE (85h10h) Operation ........................................................ 71
Figure 49: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) .................... 71
Figure 50: PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) Operation .................................... 72
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2010 Micron Technology, Inc. All rights reserved.
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2010 Micron Technology, Inc. All rights reserved.
List of Tables
Table 1: Signal Definitions ............................................................................................................................... 8
Table 2: Array Addressing (MT29F4G08) ......................................................................................................... 15
Table 3: Array Addressing (MT29F4G16xxx x16) ............................................................................................ 16
Table 4: Asynchronous Interface Mode Selection ............................................................................................ 17
Table 5: Power Cycle Requirements ................................................................................................................ 28
Table 6: Command Set .................................................................................................................................. 29
Table 7: Two-Plane Command Set .................................................................................................................. 30
Table 8: READ ID Parameters for Address 00h ................................................................................................. 34
Table 9: READ ID Parameters for Address 20h ................................................................................................. 35
Table 10: Parameter Page Data Structure ........................................................................................................ 37
Table 11: Feature Address Definitions ............................................................................................................. 41
Table 12: Feature Address 90h Array Operation Mode ................................................................................... 41
Table 13: Feature Addresses 01h: Timing Mode ............................................................................................... 43
Table 14: Feature Addresses 80h: Programmable I/O Drive Strength ................................................................ 44
Table 15: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ...................................................... 44
Table 16: Status Register Definition ................................................................................................................ 45
Table 17: Block Lock Address Cycle Assignments ............................................................................................ 75
Table 18: Block Lock Status Register Bit Definitions ........................................................................................ 78
Table 19: Error Management Details .............................................................................................................. 97
Table 20: Absolute Maximum Ratings ............................................................................................................. 98
Table 21: Recommended Operating Conditions .............................................................................................. 98
Table 22: Valid Blocks .................................................................................................................................... 98
Table 23: Capacitance .................................................................................................................................... 99
Table 24: Test Conditions ............................................................................................................................... 99
Table 25: DC Characteristics and Operating Conditions (3.3V) ....................................................................... 100
Table 26: DC Characteristics and Operating Conditions (1.8V) ....................................................................... 101
Table 27: AC Characteristics: Command, Data, and Address Input (3.3V) ........................................................ 102
Table 28: AC Characteristics: Command, Data, and Address Input (1.8V) ........................................................ 102
Table 29: AC Characteristics: Normal Operation (1.8V) .................................................................................. 103
Table 30: AC Characteristics: Normal Operation (3.3V) .................................................................................. 104
Table 31: Program/Erase Characteristics ....................................................................................................... 105
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General Description
Micron NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer
commands, address, and data. There are five control signals used to implement the
asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control
hardware write protection and monitor device status (R/B#).
This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or
more NAND Flash die. A NAND Flash die is the minimum unit that can independently
execute commands and report status. A NAND Flash die, in the ONFI specification, is
referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable
signal. For further details, see Device and Array Organization.
Signal Descriptions
Table 1: Signal Definitions
Signal1
Type
Description2
ALE
Input
Address latch enable: Loads an address from I/O[7:0] into the address register.
CE#
Input
CLE
Input
Command latch enable: Loads a command from I/O[7:0] into the command register.
LOCK
Input
When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable the
BLOCK LOCK, connect LOCK to VSS during power-up, or leave it disconnected (internal
pull-down).
RE#
Input
Read enable: Transfers serial data from the NAND Flash to the host system.
WE#
Input
Write enable: Transfers commands, addresses, and serial data from the host system to the
NAND Flash.
WP#
Input
I/O[7:0] (x8)
I/O[15:0] (x16)
I/O
Data inputs/outputs: The bidirectional I/Os transfer address, data, and command information.
R/B#
Output
VCC
Supply
VSS
Supply
NC
No connect: NCs are not internally connected. They can be driven or left unconnected.
DNU
Notes:
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Signal Assignments
Figure 2: 48-Pin TSOP Type 1, CPL (Top View)
x16
x8
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
Vcc
Vss
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
Vcc
Vss
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
Notes:
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48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
x8
x16
Vss1
DNU
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
Vcc1
DNU2
Vcc
Vss
NC
Vcc1
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
Vss1
Vss
I/O15
I/O14
I/O13
I/O7
I/O6
I/O5
I/O4
I/O12
Vcc
DNU2
Vcc
Vss
NC
Vcc
I/O11
I/O3
I/O2
I/O1
I/O0
I/O10
I/O9
I/O8
Vss
1. These pins might not be bonded in the package; however, Micron recommends that the
customer connect these pins to the designated external sources for ONFI compatibility.
2. For the 3V device, pin 38 is DNU. For the 1.8V device, pin 38 is LOCK.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
NC
NC
NC
WP#
ALE
Vss
CE#
WE#
R/B#
Vcc2
RE#
CLE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Vss2
NC
DNU
Vcc2
LOCK1
NC
NC
DNU
NC
I/O0
NC
NC
NC
Vcc
NC
I/O1
NC
Vcc
I/O5
I/O7
Vss
I/O2
I/O3
I/O4
I/O6
Vss
10
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Notes:
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1. For the 3V device, G5 changes to DNU. NO LOCK function is available on the 3.3V device.
2. These pins might not be bonded in the package; however, Micron recommends that the
customer connect these pins to the designated external sources for ONFI compatibility.
10
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2010 Micron Technology, Inc. All rights reserved.
NC
NC
NC
WP#
ALE
Vss
CE#
WE#
R/B#
Vcc
RE#
CLE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Vss
NC
DNU
Vcc
LOCK1
I/O13
I/O15
DNU
I/O8
I/O0
I/O10
I/O12
I/O14
Vcc
I/O9
I/O1
I/O11
Vcc
I/O5
I/O7
Vss
I/O2
I/O3
I/O4
I/O6
Vss
10
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Note:
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1. For the 3V device, G5 changes to DNU. NO LOCK function is available on the 3.3V device.
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Package Dimensions
Figure 5: 48-Pin TSOP Type 1, CPL
20.00 0.25
18.40 0.08
48
0.25
for reference only
0.50 TYP
for reference
only
Mold compound:
Epoxy novolac
Plated lead finish:
100% Sn
Package width and length
do not include mold
protrusion. Allowable
protrusion is 0.25 per side.
12.00 0.08
0.27 MAX
0.17 MIN
24
25
0.25
0.10
0.15
+0.03
-0.02
See detail A
1.20 MAX
0.10
Gage
plane
+0.10
-0.05
0.50 0.1
0.80
Detail A
Note:
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Seating
plane
0.1 A
63X 0.45
Dimensions apply
to solder balls postreflow on 0.4 SMD
ball pads.
Solder ball material:
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
10 9
Ball A1 ID
(covered by SR)
Ball A1 ID
A
B
C
D
E
F
8.8 CTR
11 0.1
H
J
K
L
0.8 TYP
1.0 MAX
0.8 TYP
0.25 MIN
7.2 CTR
9 0.1
Note:
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Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins and received by I/O control circuits.
The commands received at the I/O control circuits are latched by a command register
and are transferred to control logic circuits for generating internal signals to control device operations. The addresses are latched by an address register and sent to a row decoder to select a row address, or to a column decoder to select a column address.
Data is transferred to or from the NAND Flash memory array, byte by byte (x8) or word
by word (x16), through a data register and a cache register.
The NAND Flash memory array is programmed and read using page-based operations
and is erased using block-based operations. During normal page operations, the data
and cache registers act as a single register. During cache operations, the data and cache
registers operate independently to increase data throughput. The status register reports
the status of die operations.
Figure 7: NAND Flash Die (LUN) Functional Block Diagram
VCC
I/Ox
I/O
control
VSS
Address register
Status register
Command register
CE#
Column decode
CLE
WE#
Control
logic
Row decode
ALE
RE#
WP#
LOCK1
Data register
R/B#
Cache register
Note:
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NAND Flash
array
(2 planes)
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4320 bytes
DQ7
Cache Registers
4096
224
4096
224
Data Registers
4096
224
4096
224
DQ0
1 Block
1 Block
I/07
I/06
I/05
I/04
I/03
I/02
I/01
I/00
First
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
Second
LOW
LOW
LOW
CA12
CA11
CA10
CA9
CA8
Third
BA7
BA6
PA5
PA4
PA3
PA2
PA1
PA0
Fourth
BA15
BA14
BA13
BA12
BA11
BA10
BA9
BA8
Fifth
LOW
LOW
LOW
LOW
LOW
LOW
LOW
BA16
Notes:
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1. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address.
2. If CA12 is 1, then CA[11:8] must be 0.
3. BA6 controls plane selection.
15
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2010 Micron Technology, Inc. All rights reserved.
2160 words
DQ15
Cache Register
2048
112
2048
112
Data Register
2048
112
2048
112
1024 blocks
per plane
1 block
1 block
2048 blocks
per device
Plane of
even-numbered blocks
(0, 2, 4, 6, ..., 2044, 2046)
DQ0
1 page
1 block
= 128K + 7K words
1 plane
1 device
= 2160Mb x 2 planes
= 4320Mb
Plane of
odd-numbered blocks
(1, 3, 5, 7, ..., 2045, 2047)
I/O[15:8]
I/07
I/06
I/05
I/04
I/03
I/02
I/01
I/00
First
LOW
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
Second
LOW
LOW
LOW
LOW
LOW
CA11
CA10
CA9
CA8
Third
LOW
BA7
BA6
PA5
PA4
PA3
PA2
PA1
PA0
Fourth
LOW
BA15
BA14
BA13
BA12
BA11
BA10
BA9
BA8
Fifth
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
BA16
Notes:
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1. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address.
2. If CA11 = 1, then CA[10:7] must be 0.
3. BA6 controls plane selection.
16
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CE#
CLE
ALE
WE#
RE#
I/Ox
WP#
Standby2
0V/VCC
Command input
Address input
Data input
Data output
Write protect
Notes:
1. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH
or VIL.
2. WP# should be biased to CMOS LOW or HIGH for standby.
Asynchronous Enable/Standby
When the device is not performing an operation, the CE# pin is typically driven HIGH
and the device enters standby mode. The memory will enter standby if CE# goes HIGH
while data is being transferred and the device is not busy. This helps reduce power consumption.
The CE# Dont Care operation enables the NAND Flash to reside on the same asynchronous memory bus as other Flash or SRAM devices. Other devices on the memory
bus can then be accessed while the NAND Flash is busy with internal operations. This
capability is important for designs that require multiple NAND Flash devices on the
same bus.
A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal
signifies that an ADDRESS INPUT cycle is occurring.
Asynchronous Commands
An asynchronous command is written from I/O[7:0] to the command register on the rising edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.
Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
commands, including READ STATUS (70h) and READ STATUS ENHANCED (78h), are
accepted by die (LUNs) even when they are busy.
For devices with a x16 interface, I/O[15:8] must be written with zeros when a command
is issued.
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CLE
tCLS
tCS
tCLH
tCH
CE#
tWP
WE#
tALS
tALH
tDS
tDH
ALE
I/Ox
COMMAND
Dont Care
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CLE
tCLS
tCS
CE#
tWP
tWC
tWH
WE#
tALS
tALH
ALE
tDS tDH
I/Ox
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Dont Care
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19
Row
add 3
Undefined
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2010 Micron Technology, Inc. All rights reserved.
CLE
tCLH
CE#
tALS
tCH
ALE
tWC
tWP
tWP
tWP
WE#
tWH
tDS
I/Ox
tDH
DIN M
tDS
tDH
DIN M+1
tDS
tDH
DIN N
Dont Care
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CE#
tREA
tREA
tRP
tCHZ
tREA
tREH
tCOH
RE#
tRHZ
tRHZ
tRHOH
DOUT
I/Ox
tRR
DOUT
DOUT
tRC
RDY
Dont Care
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CE#
tRC
tRP
tCHZ
tREH
tCOH
RE#
tREA
tCEA
I/Ox
tREA
tRHZ
tRLOH
tRHOH
DOUT
DOUT
DOUT
tRR
RDY
Dont Care
Write Protect#
The write protect# (WP#) signal enables or disables PROGRAM and ERASE operations
to a target. When WP# is LOW, PROGRAM and ERASE operations are disabled. When
WP# is HIGH, PROGRAM and ERASE operations are enabled.
It is recommended that the host drive WP# LOW during power-on until V CC is stable to
prevent inadvertent PROGRAM and ERASE operations (see Device Initialization for additional details).
WP# must be transitioned only when the target is not busy and prior to beginning a
command sequence. After a command sequence is complete and the target is ready,
WP# can be transitioned. After WP# is transitioned, the host must wait tWW before issuing a new command.
The WP# signal is always an active input, even when CE# is HIGH. This signal should
not be multiplexed with other signals.
Ready/Busy#
The ready/busy# (R/B#) signal provides a hardware method of indicating whether a target is ready or busy. A target is busy when one or more of its die (LUNs) are busy
(RDY = 0). A target is ready when all of its die (LUNs) are ready (RDY = 1). Because each
die (LUN) contains a status register, it is possible to determine the independent status
of each die (LUN) by polling its status register instead of using the R/B# signal (see Status Operations for details regarding die (LUN) status).
This signal requires a pull-up resistor, Rp, for proper operation. R/B# is HIGH when the
target is ready, and transitions LOW when the target is busy. The signal's open-drain
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The fall time of the R/B# signal is determined mainly by the output impedance of the
R/B# signal and the total load capacitance. Approximate Rp values using a circuit load
of 100pF are provided in Figure 20 (page 26).
The minimum value for Rp is determined by the output drive capability of the R/B# signal, the output voltage swing, and V CC.
V (MAX) - VOL (MAX)
Rp = CC
IOL + IL
Where IL is the sum of the input currents of all devices tied to the R/B# pin.
Rp
VCC
R/B#
Open drain output
IOL
VSS
Device
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tFall tRise
2.00
1.50
1.00
0.50
0.00
1
TC
Notes:
6
VCC 3.3V
tFall
2.00
tRise
1.50
1.00
0.50
0.00
-1
0
TC
Notes:
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1.
2.
3.
4.
6
VCC1.8V
tFall
24
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2010 Micron Technology, Inc. All rights reserved.
1.50
1.00
0.50
0.00
0
2000
400 0
6000
8000
10,000
12,000
Rp ()
IOL at VCC (MAX)
I (mA)
1.50
1.00
0.50
0.00
0
2000
4000
6000
8000
10,000
12,000
Rp ()
IOL at VCC (MAX)
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1200
1000
800
T(ns)
600
400
200
0
0
2000
4000
6000
8000
Rp ()
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26
10,000
12,000
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2010 Micron Technology, Inc. All rights reserved.
Device Initialization
Micron NAND Flash devices are designed to prevent data corruption during power
transitions. V CC is internally monitored. (The WP# signal supports additional hardware
protection during power transitions.) When ramping V CC, use the following procedure
to initialize the device:
1. Ramp V CC.
2. The host must wait for R/B# to be valid and HIGH before issuing RESET (FFh) to
any target. The R/B# signal becomes valid when 50s has elapsed since the beginning the V CC ramp, and 10s has elapsed since V CC reaches V CC (MIN).
3. If not monitoring R/B#, the host must wait at least 100s after V CC reaches V CC
(MIN). If monitoring R/B#, the host must wait until R/B# is HIGH.
4. The asynchronous interface is active by default for each target. Each LUN draws
less than an average of 10mA (IST) measured over intervals of 1ms until the RESET
(FFh) command is issued.
5. The RESET (FFh) command must be the first command issued to all targets (CE#s)
after the NAND Flash device is powered on. Each target will be busy for 1ms after a
RESET command is issued. The RESET busy time can be monitored by polling
R/B# or issuing the READ STATUS (70h) command to poll the status register.
6. The device is now initialized and ready for normal operation.
Figure 21: R/B# Power-On Behavior
50s (MIN)
VCC
R/B#
100s (MAX)
VCC ramp
starts
Reset (FFh)
is issued
Invalid
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Value
Unit
Maximum VCC/VCCQ
100
mV
100
ns
28
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Command Definitions
Table 6: Command Set
Command
Cycle #1
Number of
Valid
Address
Cycles
Data
Input
Cycles
FFh
Yes
Yes
READ ID
90h
No
No
ECh
No
No
READ UNIQUE ID
EDh
No
No
GET FEATURES
EEh
No
No
SET FEATURES
EFh
No
No
READ STATUS
70h
Yes
78h
Yes
Yes
Command
Valid While
Selected LUN
Command is Busy on page
Cycle #2
Valid While
Other LUNs
are Busy on
page
Notes
Reset Operations
RESET
Identification Operation
Feature Operations
Status Operations
05h
E0h
No
Yes
85h
Optional
No
Yes
PROGRAM FOR
INTERNAL DATA MOVE
85h
Optional
No
Yes
READ MODE
00h
No
Yes
READ PAGE
00h
30h
No
Yes
31h
No
Yes
00h
31h
No
Yes
3Fh
No
Yes
PROGRAM PAGE
80h
Yes
10h
No
Yes
80h
Yes
15h
No
Yes
60h
D0h
No
Yes
35h
No
Yes
READ OPERATIONS
Program Operations
5
Erase Operations
ERASE BLOCK
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00h
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Command
Cycle #1
Number of
Valid
Address
Cycles
Data
Input
Cycles
85h
Optional
10h
No
Yes
23h
No
Yes
24h
No
Yes
BLOCK LOCK
2Ah
No
Yes
BLOCK LOCK-TIGHT
2Ch
No
Yes
7Ah
No
Yes
Command
PROGRAM FOR INTERNAL DATA MOVE
Valid While
Selected LUN
Command is Busy on page
Cycle #2
Valid While
Other LUNs
are Busy on
page
Notes
80h
No
10h
No
No
80h
Yes
10h
No
No
00h
No
30h
No
No
Notes:
Number of
Valid
Address
Cycles
Command
Cycle #2
Number of
Valid
Address
Cycles
Command
Cycle #3
00h
00h
30h
No
Yes
00h
00h
35h
No
Yes
Command
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Number of
Valid
Address
Cycles
Command
Cycle #2
Number of
Valid
Address
Cycles
Command
Cycle #3
RANDOM DATA
READ TWO-PLANE
06h
E0h
No
Yes
PROGRAM PAGE
TWO-PLANE
80h
11h-80h
10h
No
Yes
PROGRAM PAGE
CACHE MODE TWOPLANE
80h
11h-80h
15h
No
Yes
PROGRAM FOR
TWO-PLANE INTERNAL DATA MOVE
85h
11h-85h
10h
No
Yes
60h
D1h-60h
D0h
No
Yes
Command
Notes:
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1. Do not cross plane boundaries when using READ FOR INTERNAL DATA MOVE TWOPLANE or PROGRAM FOR TWO-PLANE INTERNAL DATA MOVE.
2. The RANDOM DATA READ TWO-PLANE command is limited to use with the PAGE READ
TWO-PLANE command.
3. D1h command can be omitted.
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Reset Operations
RESET (FFh)
The RESET command is used to put the memory device into a known condition and to
abort the command sequence in progress.
READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy
state. The contents of the memory location being programmed or the block being
erased are no longer valid. The data may be partially erased or programmed, and is invalid. The command register is cleared and is ready for the next command. The data
register and cache register contents are marked invalid.
The status register contains the value E0h when WP# is HIGH; otherwise it is written
with a 60h value. R/B# goes LOW for tRST after the RESET command is written to the
command register.
The RESET command must be issued to all CE#s as the first command after power-on.
The device will be busy for a maximum of 1ms.
Figure 22: RESET (FFh) Operation
Cycle type
I/O[7:0]
Command
FF
tWB
tRST
R/B#
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Identification Operations
READ ID (90h)
The READ ID (90h) command is used to read identifier codes programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are
idle.
Writing 90h to the command register puts the target in read ID mode. The target stays in
this mode until another valid command is issued.
When the 90h command is followed by an 00h address cycle, the target returns a 5-byte
identifier code that includes the manufacturer ID, device configuration, and part-specific information.
When the 90h command is followed by a 20h address cycle, the target returns the 4-byte
ONFI identifier code.
Figure 23: READ ID (90h) with 00h Address Operation
Cycle type
Command
Address
DOUT
DOUT
DOUT
DOUT
DOUT
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
tWHR
I/O[7:0]
Note:
90h
00h
Command
Address
DOUT
DOUT
DOUT
DOUT
4Fh
4Eh
46h
49h
tWHR
I/O[7:0]
Note:
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90h
20h
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I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Value1
Micron
2Ch
MT29F4G08ABBEA
ACh
MT29F4G16ABBEA
BCh
MT29F4G08ABAEA
DCh
MT29F4G16ABAEA
CCh
00b
Options
Byte 0 Manufacturer ID
Manufacturer
Byte 1 Device ID
Byte 2
Number of die per CE
Cell type
SLC
Not supported
Cache programming
Supported
Byte value
MT29F4G
00b
01b
0b
1b
90h
10b
Byte 3
Page size
4KB
224B
256KB
Organization
x8
x16
1
1
1b
10b
0b
1.8V
30ns
0xxx0b
3.3V
20ns
MT29F4G08ABBEA
26h
MT29F4G16ABBEA
66h
MT29F4G08ABAEA
A6h
MT29F4G16ABAEA
E6h
00b
1xxx0b
Byte 4
Reserved
Planes per CE#
Plane size
2Gb
0
1
Reserved
01b
101b
Byte value
MT29F4G
Note:
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0b
0
54h
1. b = binary; h = hexadecimal.
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Options
I/07
I/06
I/05
I/04
I/03
I/02
I/01
I/00
Value
Notes
4Fh
4Eh
46h
49h
Undefined
XXh
Note:
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1. h = hexadecimal.
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I/O[7:0]
Command
Address
ECh
00h
tWB
tR
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
P00
P10
P01
P11
tRR
R/B#
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Description
Value
03
45
Revision number
67
Features supported
89
02h, 00h
MT29F4G08ABBEA3W
18h, 00h
MT29F4G16ABBEA3W
19h, 00h
MT29F4G08ABAEA3W
18h, 00h
MT29F4G16ABAEA3W
19h, 00h
MT29F4G08ABBEAH4
18h, 00h
MT29F4G16ABBEAH4
19h, 00h
MT29F4G08ABAEAWP
18h, 00h
MT29F4G16ABAEAWP
19h, 00h
MT29F4G08ABAEAH4
18h, 00h
MT29F4G16ABAEAH4
19h, 00h
3Fh, 00h
1031
Reserved
00h
3243
Device manufacturer
4Dh, 49h, 43h, 52h, 4Fh, 4Eh, 20h, 20h, 20h, 20h, 20h,
20h
4463
Device model
64
6566
MT29F4G08ABBEA3W
4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h,
42h, 45h, 41h, 33h, 57h, 20h, 20h, 20h, 20h
MT29F4G16ABBEA3W
4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h,
42h, 45h, 41h, 33h, 57h, 20h, 20h, 20h, 20h
MT29F4G08ABAEA3W
4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h,
41h, 45h, 41h, 33h, 57h, 20h, 20h, 20h, 20h
MT29F4G16ABAEA3W
4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h,
41h, 45h, 41h, 33h, 57h, 20h, 20h, 20h, 20h
MT29F4G08ABBEAH4
4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h,
42h, 45h, 41h, 48h, 34h, 20h, 20h, 20h, 20h
MT29F4G16ABBEAH4
4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h,
42h, 45h, 41h, 48h, 34h, 20h, 20h, 20h, 20h
MT29F4G08ABAEAWP
4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h,
41h, 45h, 41h, 57h, 50h, 20h, 20h, 20h, 20h
MT29F4G16ABAEAWP
4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h,
41h, 45h, 41h, 57h, 50h, 20h, 20h, 20h, 20 h
MT29F4G08ABAEAH4
4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h,
41h, 45h, 41h, 48h, 34h, 20h, 20h, 20h, 20h
MT29F4G16ABAEAH4
4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h,
41h, 45h, 41h, 48h, 34h, 20h, 20h, 20h, 20h
Manufacturer ID
2Ch
Date code
00h, 00h
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Description
Value
6779
Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h
8083
8485
E0h, 00h
8689
9091
38h, 00h
9295
9699
100
01h
101
23h
102
01h
28h, 00h
06h, 04h
107
01h
00h, 00h
110
04h
111
00h
112
08h
113
01h
114
0Eh
115127 Reserved
128
00h
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0Ah
MT29F4G08ABBEA3W
1Fh, 00h
MT29F4G16ABBEA3W
1Fh, 00h
MT29F4G08ABAEA3W
3Fh, 00h
MT29F4G16ABAEA3W
3Fh, 00h
MT29F4G08ABBEAH4
1Fh, 00h
MT29F4G16ABBEAH4
1Fh, 00h
MT29F4G08ABAEAWP
3Fh, 00h
MT29F4G16ABAEAWP
3Fh, 00h
MT29F4G08ABAEAH4
3Fh, 00h
MT29F4G16ABAEAH4
3Fh, 00h
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Description
133134
tPROG
135136
tBERS
137138
tR
139140
tCCS
Value
MT29F4G08ABBEA3W
1Fh, 00h
MT29F4G16ABBEA3W
1Fh, 00h
MT29F4G08ABAEA3W
3Fh, 00h
MT29F4G16ABAEA3W
3Fh, 00h
MT29F4G08ABBEAH4
1Fh, 00h
MT29F4G16ABBEAH4
1Fh, 00h
MT29F4G08ABAEAWP
3Fh, 00h
MT29F4G16ABAEAWP
3Fh, 00h
MT29F4G08ABAEAH4
3Fh, 00h
MT29F4G16ABAEAH4
3Fh, 00h
58h, 02h
10h, 27h
19h, 00h
Minimum
64h, 00h
141163 Reserved
00h
01h, 00h
166253 Vendor-specific
01h, 00h, 00h, 02h, 04h, 80h, 01h, 81h, 04h, 01h, 02h,
01h, 0Ah, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
Set at test
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tR.
After tR completes, the host enables data output mode to read the unique ID. When the
asynchronous interface is active, one data byte is output per RE# toggle.
Sixteen copies of the unique ID data are stored in the device. Each copy is 32 bytes. The
first 16 bytes of a 32-byte copy are unique data, and the second 16 bytes are the complement of the first 16 bytes. The host should XOR the first 16 bytes with the second 16
bytes. If the result is 16 bytes of FFh, then that copy of the unique ID data is correct. In
the event that a non-FFh result is returned, the host can repeat the XOR operation on a
subsequent copy of the unique ID data. If desired, the RANDOM DATA READ (05h-E0h)
command can be used to change the data output location.
The upper eight I/Os on a x16 device are not used and are a Dont Care for x16 devices.
Figure 26: READ UNIQUE ID (EDh) Operation
Cycle type
I/O[7:0]
Command
Address
EDh
00h
tWB
tR
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
U00
U10
U01
U11
tRR
R/B#
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Feature Operations
The SET FEATURES (EFh) and GET FEATURES (EEh) commands are used to modify the
target's default power-on behavior. These commands use a one-byte feature address to
determine which subfeature parameters will be read or modified. Each feature address
(in the 00h to FFh range) is defined in below. The SET FEATURES (EFh) command
writes subfeature parameters (P1P4) to the specified feature address. The GET FEATURES command reads the subfeature parameters (P1P4) at the specified feature address.
Table 11: Feature Address Definitions
Feature Address
Definition
00h
Reserved
01h
Timing mode
02h7Fh
Reserved
80h
81h
82hFFh
Reserved
90h
Options
1/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Value
Notes
1
P1
Operation
mode option
Normal
Reserved (0)
00h
OTP
operation
Reserved (0)
01h
03h
OTP
protection
Reserved (0)
Reserved (0)
00h
Reserved (0)
00h
Reserved (0)
00h
Reserved (0)
00h
Reserved (0)
00h
P2
Reserved
P3
Reserved
P4
Reserved
Note:
41
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Command
Address
DIN
DIN
DIN
DIN
P1
P2
P3
P4
tADL
I/O[7:0]
EFh
FA
tWB
tFEAT
R/B#
I/Ox
Command
Address
DOUT
DOUT
DOUT
DOUT
EEh
FA
P1
P2
P3
P4
tWB
tFEAT
tRR
R/B#
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Options
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Value
Notes
P1
Timing mode
Mode 0
(default)
Reserved (0)
00h
1, 2
Mode 1
Reserved (0)
01h
Mode 2
Reserved (0)
02h
Mode 3
Reserved (0)
03h
Mode 4
Reserved (0)
04h
Mode 5
Reserved (0)
05h
P2
Reserved (0)
00h
Reserved (0)
00h
Reserved (0)
00h
P3
P4
Notes:
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1. The timing mode feature address is used to change the default timing mode. The timing
mode should be selected to indicate the maximum speed at which the device will receive commands, addresses, and data cycles. The five supported settings for the timing
mode are shown. The default timing mode is mode 0. The device returns to mode 0
when the device is power cycled. Supported timing modes are reported in the parameter page.
2. Supported for both 1.8V and 3.3V.
3. Supported for 3.3V only.
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Options
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Value
Notes
1
P1
I/O drive strength
Full (default)
Reserved (0)
00h
Three-quarters
Reserved (0)
01h
One-half
Reserved (0)
02h
One-quarter
Reserved (0)
03h
P2
Reserved (0)
00h
Reserved (0)
00h
Reserved (0)
00h
P3
P4
Note:
1. The programmable drive strength feature address is used to change the default I/O
drive strength. Drive strength should be selected based on expected loading of the
memory bus. This table shows the four supported output drive strength settings. The
default drive strength is full strength. The device returns to the default drive strength
mode when the device is power cycled. AC timing parameters may need to be relaxed if
I/O drive strength is not set to full.
Options
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Value
Notes
Full (default)
00h
Three-quarters
01h
One-half
02h
One-quarter
03h
P1
R/B# pull-down
strength
P2
Reserved (0)
00h
Reserved (0)
00h
Reserved (0)
00h
P3
P4
Note:
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1. This feature address is used to change the default R/B# pull-down strength. Its strength
should be selected based on the expected loading of R/B#. Full strength is the default,
power-on value.
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Status Operations
Each die (LUN) provides its status independently of other die (LUNs) on the same target
through its 8-bit status register.
After the READ STATUS (70h) or READ STATUS ENHANCED (78h) command is issued,
status register output is enabled. The contents of the status register are returned on I/
O[7:0] for each data output request.
When the asynchronous interface is active and status register output is enabled,
changes in the status register are seen on I/O[7:0] as long as CE# and RE# are LOW; it is
not necessary to toggle RE# to see the status register update.
While monitoring the status register to determine when a data transfer from the Flash
array to the data register (tR) is complete, the host must issue the READ MODE (00h)
command to disable the status register and enable data output (see Read Operations).
The READ STATUS (70h) command returns the status of the most recently selected die
(LUN). To prevent data contention during or following an interleaved die (multi-LUN)
operation, the host must enable only one die (LUN) for status output by using the READ
STATUS ENHANCED (78h) command (see Interleaved Die (Multi-LUN) Operations).
Table 16: Status Register Definition
Program Page
Cache Mode Page Read
Page Read
Cache Mode
SR Bit
Program Page
Write protect
Write protect
Write protect
Write protect
RDY
RDY cache1
RDY
RDY cache1
RDY
0 = Busy
1 = Ready
ARDY
ARDY2
ARDY
ARDY2
ARDY
0 = Busy
1 = Ready
Reserved (0)
Reserved (0)
Reserved (0)
FAILC (N1)
FAILC (N1)
0 = Pass
1 = Fail
FAIL
FAIL (N)
FAIL
0 = Pass
1 = Fail
Notes:
Block Erase
Description
1. Status register bit 6 is 1 when the cache is ready to accept new data. R/B# follows bit 6.
2. Status register bit 5 is 0 during the actual programming operation. If cache mode is
used, this bit will be 1 when all internal operations are complete.
3. A status register bit 0 reports a 1 if a TWO-PLANE PROGRAM PAGE or TWO-PLANE
BLOCK ERASE operation fails on one or both planes. A status register bit 1 reports a 1 if
a TWO-PLANE PROGRAM PAGE CACHE MODE operation fails on one or both planes. Use
READ STATUS ENHANCED (78h) to determine the plane to which the operation failed.
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Command
DOUT
tWHR
I/O[7:0]
70h
SR
Command
Address
Address
Address
DOUT
tWHR
I/Ox
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78h
R1
R2
46
R3
SR
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Cycle type
DOUT
DOUT
Command
Address
Address
Command
tRHW
I/O[7:0]
Dn
Dn + 1
DOUT
DOUT
DOUT
Dk
Dk + 1
Dk + 2
tWHR
05h
C1
C2
E0h
SR[6]
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Cycle
type
I/O[7:0]
DOUT
DOUT
Command
Address
Address
Address
Address
Address
Command
tRHW
Dn
Dn + 1
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DOUT
DOUT
DOUT
Dk
Dk + 1
Dk + 2
tWHR
06h
C1
C2
R1
R2
48
R3
E0h
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Cycle type
DIN
DIN
Address
Address
DIN
DIN
DIN
Dk
Dk + 1
Dk + 2
tADL
I/O[7:0]
Dn
Dn + 1
85h
C1
C2
RDY
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Cycle type
DIN
DIN
Command
Address
Address
Address
Address
Address
Command
DIN
DIN
DIN
Dk
Dk + 1
Dk + 2
tADL
I/O[7:0]
Dn
Dn + 1
85h
C1
C2
R1
R2
R3
10h
RDY
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Read Operations
The READ PAGE (00h-30h) command, when issued by itself, reads one page from the
NAND Flash array to its cache register and enables data output for that cache register.
During data output the following commands can be used to read and modify the data in
the cache registers: RANDOM DATA READ (05h-E0h) and RANDOM DATA INPUT (85h).
Read Cache Operations
To increase data throughput, the READ PAGE CACHE series (31h, 00h-31h) commands
can be used to output data from the cache register while concurrently copying a page
from the NAND Flash array to the data register.
To begin a read page cache sequence, begin by reading a page from the NAND Flash array to its corresponding cache register using the READ PAGE (00h-30h) command.
R/B# goes LOW during tR and the selected die (LUN) is busy (RDY = 0, ARDY = 0). After
tR (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these commands:
READ PAGE CACHE SEQUENTIAL (31h) copies the next sequential page from the
NAND Flash array to the data register
READ PAGE CACHE RANDOM (00h-31h) copies the page specified in this command
from the NAND Flash array to its corresponding data register
After the READ PAGE CACHE series (31h, 00h-31h) command has been issued, R/B#
goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while
the next page begins copying data from the array to the data register. After tRCBSY,
R/B# goes HIGH and the dies (LUNs) status register bits indicate the device is busy
with a cache operation (RDY = 1, ARDY = 0). The cache register becomes available and
the page requested in the READ PAGE CACHE operation is transferred to the data register. At this point, data can be output from the cache register, beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data output by the die (LUN).
After outputting the desired number of bytes from the cache register, either an additional READ PAGE CACHE series (31h, 00h-31h) operation can be started or the READ
PAGE CACHE LAST (3Fh) command can be issued.
If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target,
and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the data register is copied
into the cache register. After tRCBSY, R/B# goes HIGH and RDY = 1 and
ARDY = 1, indicating that the cache register is available and that the die (LUN) is ready.
Data can then be output from the cache register, beginning at column address 0. The
RANDOM DATA READ (05h-E0h) command can be used to change the column address
of the data being output.
For READ PAGE CACHE series (31h, 00h-31h, 3Fh), during the die (LUN) busy time,
tRCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations
(70h, 78h) and RESET (FFh). When RDY = 1 and ARDY = 0, the only valid commands
during READ PAGE CACHE series (31h, 00h-31h) operations are status operations (70h,
78h), READ MODE (00h), READ PAGE CACHE series (31h, 00h-31h), RANDOM DATA
READ (05h-E0h), and RESET (FFh).
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I/O[7:0]
Command
Address
Address
Address
Address
Address
Command
DOUT
DOUT
DOUT
00h
C1
C2
R1
R2
R3
30h
Dn
Dn+1
Dn+2
tWB
tR
tRR
RDY
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Cycle type
I/O[7:0]
Command
Address x5
Command
00h
Page Address M
30h
tWB
Command
31h
tR
RR
tWB
tRCBSY
DOUT
DOUT
DOUT
Command
D0
Dn
31h
tWB
tRR
DOUT
D0
tRCBSY
tRR
RDY
Page M
Page M+1
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Cycle type
I/O[7:0]
Command
Address x5
Command
00h
Page Address M
30h
tWB
tR
Command
Address x5
Command
00h
Page Address N
31h
tWB
RR
tRCBSY
DOUT
DOUT
DOUT
Command
D0
Dn
00h
tRR
RDY
Page M
1
Cycle type
I/O[7:0]
DOUT
Command
Address x5
Command
Dn
00h
Page Address P
31h
tWB
DOUT
D0
tRCBSY
tRR
RDY
Page N
1
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Cycle type
I/O[7:0]
Command
31h
tWB
tRCBSY
DOUT
DOUT
DOUT
Command
D0
Dn
3Fh
tRR
tWB
tRCBSY
DOUT
DOUT
DOUT
D0
Dn
tRR
RDY
Page Address N
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Page N
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WE#
ALE
RE#
Page address M
00h
I/Ox
Col
add 1
Col
add 2
Row
add 1
Column address J
Row
add 2
Page address M
Row
add 3
Col
add 1
00h
Plane 0 address
Col
add 2
Row
add 1
Column address J
Row
add 2
Row
add 3
30h
tR
Plane 1 address
R/B#
1
CLE
WE#
ALE
RE#
I/Ox
DOUT 0
DOUT 1
DOUT
06h
Col
add 1
Col
add 2
Row
add 1
Plane 0 data
Row
add 2
Row
add 3
Plane 1 address
E0h
DOUT 0
DOUT 1
DOUT
Plane 1 data
R/B#
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Program Operations
Program operations are used to move data from the cache or data registers to the NAND
array. During a program operation the contents of the cache and/or data registers are
modified by the internal control logic.
Within a block, pages must be programmed sequentially from the least significant page
address to the most significant page address (0, 1, 2, .., 63). During a program operation, the contents of the cache and/or data registers are modified by the internal control
logic.
Program Operations
The PROGRAM PAGE (80h-10h) command, when not preceded by the PROGRAM PAGE
TWO-PLANE (80h-11h) command, programs one page from the cache register to the
NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should
check the FAIL bit to verify that the operation has completed successfully.
Program Cache Operations
The PROGRAM PAGE CACHE (80h-15h) command can be used to improve program operation system performance. When this command is issued, the die (LUN) goes busy
(RDY = 0, ARDY = 0) while the cache register contents are copied to the data register,
and the die (LUN) is busy with a program cache operation (RDY = 1, ARDY = 0. While
the contents of the data register are moved to the NAND Flash array, the cache register
is available for an additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE
(80h-10h) command.
For PROGRAM PAGE CACHE series (80h-15h) operations, during the die (LUN) busy
times, tCBSY and tLPROG, when RDY = 0 and ARDY = 0, the only valid commands are
status operations (70h, 78h) and reset (FFh). When RDY = 1 and ARDY = 0, the only valid
commands during PROGRAM PAGE CACHE series (80h-15h) operations are status operations (70h, 78h), PROGRAM PAGE CACHE (80h-15h), PROGRAM PAGE (80h-10h),
RANDOM DATA INPUT (85h), PROGRAM FOR INTERNAL DATA INPUT (85h), and RESET (FFh).
Two-Plane Program Operations
The PROGRAM PAGE TWO-PLANE (80h-11h) command can be used to improve program operation system performance by enabling multiple pages to be moved from the
cache registers to different planes of the NAND Flash array. This is done by prepending
one or more PROGRAM PAGE TWO-PLANE (80h-11h) commands in front of the PROGRAM PAGE (80h-10h) command.
Two-Plane Program Cache Operations
The PROGRAM PAGE TWO-PLANE (80h-11h) command can be used to improve program cache operation system performance by enabling multiple pages to be moved
from the cache registers to the data registers and, while the pages are being transferred
from the data registers to different planes of the NAND Flash array, free the cache registers to receive data input from the host. This is done by prepending one or more PROGRAM PAGE TWO-PLANE (80h-11h) commands in front of the PROGRAM PAGE
CACHE (80h-15h) command.
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Cycle type
Command
Address
Address
Address
Address
Address
DIN
DIN
DIN
DIN
Command
D0
D1
Dn
10h
Command
DOUT
70h
Status
tADL
I/O[7:0]
80h
C1
C2
R1
R2
R3
tWB
tPROG
RDY
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Cycle type
Command
Address
Address
Address
Address
Address
DIN
DIN
DIN
DIN
Command
D0
D1
Dn
15h
tADL
I/O[7:0]
80h
C1
C2
R1
R2
R3
tWB
tCBSY
RDY
1
Cycle type
Command
Address
Address
Address
Address
Address
DIN
DIN
DIN
DIN
Command
D0
D1
Dn
15h
tADL
I/O[7:0]
80h
C1
C2
R1
R2
R3
tWB
tCBSY
RDY
Cycle type
Command
Address
Address
Address
Address
Address
DIN
DIN
DIN
DIN
Command
D0
D1
Dn
15h
tADL
I/O[7:0]
80h
C1
C2
R1
R2
R3
tWB
tCBSY
RDY
1
Cycle type
Command
Address
Address
Address
Address
Address
DIN
DIN
DIN
DIN
Command
D0
D1
Dn
10h
tADL
I/O[7:0]
80h
C1
C2
R1
R2
R3
tWB
tLPROG
RDY
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Cycle type
Command
Address
Address
Address
Address
Address
DIN
DIN
DIN
Command
Command
Address
D0
Dn
11h
80h
...
tADL
I/O[7:0]
80h
C1
C2
R1
R2
R3
tWB tDBSY
RDY
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Erase Operations
Erase operations are used to clear the contents of a block in the NAND Flash array to
prepare its pages for program operations.
Erase Operations
The ERASE BLOCK (60h-D0h) command, when not preceded by the ERASE BLOCK
TWO-PLANE (60h-D1h) command, erases one block in the NAND Flash array. When the
die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that
this operation completed successfully.
TWO-PLANE ERASE Operations
The ERASE BLOCK TWO-PLANE (60h-D1h) command can be used to further system
performance of erase operations by allowing more than one block to be erased in the
NAND array. This is done by prepending one or more ERASE BLOCK TWO-PLANE (60hD1h) commands in front of the ERASE BLOCK (60h-D0h) command. See Two-Plane
Operations for details.
I/O[7:0]
Command
Address
Address
Address
Command
60h
R1
R2
R3
D0h
tWB
tBERS
RDY
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I/O[7:0]
Command
Address
Address
Address
Command
60h
R1
R2
R3
D1h
tWB
Command
Address
60h
...
tDBSY
RDY
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Command
Address
Address
Address
Address
Address
Command
DOUT
DOUT
DOUT
00h
C1
C2
R1
R2
R3
35h
Dn
Dn+1
Dn+2
I/O[7:0]
tWB
tR
tRR
RDY
Figure 47: READ FOR INTERNAL DATA MOVE (00h35h) with RANDOM DATA READ (05hE0h)
Cycle type
I/O[7:0]
Command
Address
Address
Address
Address
Address
Command
00h
C1
C2
R1
R2
R3
35h
tWB
tR
DOUT
DOUT
DOUT
D0
Dj + n
tRR
RDY
1
Cycle type
Command
Address
Address
Command
DOUT
DOUT
DOUT
Dk
Dk + 1
Dk + 2
tWHR
I/O[7:0]
05h
C1
C2
E0h
RDY
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Command
Address
Address
Address
Address
Address
Command
85h
C1
C2
R1
R2
R3
10h
I/O[7:0]
tWB
tPROG
RDY
Figure 49: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h)
Cycle type
Command
Address
Address
Address
Address
Address
DIN
DIN
Di
Di + 1
tWHR
I/O[7:0]
85h
C1
C2
R1
R2
R3
RDY
1
Cycle type
Command
Address
Address
DIN
DIN
DIN
Command
Dj
Dj + 1
Dj + 2
10h
tWHR
I/O[7:0]
85h
C1
C2
tWB
tPROG
RDY
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Cycle type
Command
Address
Address
Address
Address
Address
DIN
DIN
DIN
Command
Command
Address
D0
Dn
11h
85h
...
tADL
I/O[7:0]
85h
C1
C2
R1
R2
R3
tWB tDBSY
RDY
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UNLOCK (23h-24h)
By default at power-on, if LOCK is HIGH, all the blocks are locked and protected from
PROGRAM and ERASE operations. The UNLOCK (23h) command is used to unlock a
range of blocks. Unlocked blocks have no protection and can be programmed or erased.
The UNLOCK command uses two registers, a lower boundary block address register and
an upper boundary block address register, and the invert area bit to determine what
range of blocks are unlocked. When the invert area bit = 0, the range of blocks within
the lower and upper boundary address registers are unlocked. When the invert area bit
= 1, the range of blocks outside the boundaries of the lower and upper boundary address registers are unlocked. The lower boundary block address must be less than the
upper boundary block address. The figures below show examples of how the lower and
upper boundary address registers work with the invert area bit.
To unlock a range of blocks, issue the UNLOCK (23h) command followed by the appropriate address cycles that indicate the lower boundary block address. Then issue the
24h command followed by the appropriate address cycles that indicate the upper boundary block address. The least significant page address bit, PA0, should be set to 1 if setting the invert area bit; otherwise, it should be 0. The other page address bits should be
0.
Only one range of blocks can be specified in the lower and upper boundary block address registers. If after unlocking a range of blocks the UNLOCK command is again issued, the new block address range determines which blocks are unlocked. The previous
unlocked block address range is not retained.
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Block 2047
Block 2046
Block 2045
Block 2044
Block 2043
Block 2042
Block 2041
Block 2040
Block. 2039
..
..
..
..
..
..
.
Block 0002
Block 0001
Block 0000
Protected
area
7FCh
7F8h
Unprotected
area
Protected
area
Block 2047
Block 2046
Block 2045
Block 2044
Block 2043
Block 2042
Block 2041
Block 2040
Block. 2039
..
..
..
..
..
..
.
Block 0002
Block 0001
Block 0000
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Unprotected
Area
7FCh
7F8h
Protected
area
Unprotected
area
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I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
First
LOW
BA7
BA6
LOW
LOW
LOW
LOW
LOW
Second
LOW
BA15
BA14
BA13
BA12
BA11
BA10
BA9
BA8
Third
LOW
LOW
LOW
LOW
LOW
LOW
LOW
BA17
BA16
ALE Cycle
Notes:
CE#
WE#
ALE
RE#
I/Ox
23h
Unlock
Block
Block
Block
add 1
add 2
add 3
Lower boundary
24h
Block
Block
Block
add 1
add 2
add 3
Upper boundary
R/B#
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tLBSY. The
The LOCK (2Ah) command is disabled if LOCK is LOW at power-on or if the device is
locked tight.
Figure 54: LOCK Operation
CLE
CE#
WE#
I/Ox
2Ah
LOCK command
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WP#
CLE
CE#
WE#
I/Ox
2Ch
LOCK TIGHT
command
R/B#
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R/B#
I/Ox
PROGRAM or ERASE
CONFIRM
70h
Locked block
60h
READ STATUS
I/O[7:3]
I/O2 (Lock#)
I/O1 (LT#)
I/O0 (LT)
Block is locked
CE#
WE#
tWHR
ALE
RE#
I/Ox
7Ah
BLOCK LOCK
READ STATUS
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Add 1
Add 2
Add 3
Status
Block address
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Power-up
Power-up with
LOCK HIGH
Power-up with
LOCK LOW
(default)
Unlocked range
WP# LOW
>100ns or
LOCK Cmd
Locked range
Locked range
Unlocked range
Unlocked range
UNLOCK Cmd
with invert area
bit = 1
Locked range
Unlocked range
Unlocked range
Unlocked range
Locked-tight range
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CE#
tWC
WE#
tWB
tPROG
ALE
RE#
I/Ox
Col
add 1
80h
OTP DATA INPUT
command
Col
add 2
OTP
page1
OTP address1
00h
00h
DIN
n
DIN
m
1 up to m bytes
serial input
10h
70h
PROGRAM
command
READ STATUS
command
Status
R/B#
x8 device: m = 4320 bytes
x16 device: m = 2160 words
Note:
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tADL
tADL
WE#
tWB
tPROG
ALE
RE#
I/Ox
80h
Col
add1
OTP
Col
add2 page1
00h
00h
SERIAL DATA
INPUT command
DIN
Col
Col
85h
add1 add2
n+1
Serial input RANDOM DATA Column address
INPUT command
DIN
n
DIN
10h
n+1
Serial input
PROGRAM
command
DIN
n
70h
Status
READ STATUS
command
R/B#
Dont Care
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CE#
tWC
WE#
tWB
tPROG
ALE
RE#
I/Ox
Col
00h
80h
OTP DATA
PROTECT command
Col
00h
OTP
page
00h
00h
DIN
OTP address
10h
70h
PROGRAM
command
READ STATUS
command
R/B#
Status
Note:
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CLE
CE#
WE#
ALE
tR
RE#
I/Ox
00h
Col
add 1
Col
add 2
OTP
page1
00h
00h
OTP address
DOUT
n
30h
DOUT
n+1
DOUT
m
Busy
R/B#
Dont Care
Note:
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CE#
WE#
tWB
tAR
tWHR
ALE
tREA
tRC
RE#
tRR
I/Ox
00h
Col
add 1
Col
add 2
Column addressn
R/B#
OTP
page1
00h
00h
DOUT
n
30h
DOUT
n+1
05h
tR
Col
add 1
Col
add 2
E0h
DOUT
m
DOUT
m+1
Column addressm
Busy
Dont Care
Note:
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Two-Plane Operations
Each NAND Flash logical unit (LUN) is divided into multiple physical planes. Each
plane contains a cache register and a data register independent of the other planes. The
planes are addressed via the low-order block address bits. Specific details are provided
in Device and Array Organization.
Two-plane operations make better use of the NAND Flash arrays on these physical
planes by performing concurrent READ, PROGRAM, or ERASE operations on multiple
planes, significantly improving system performance. Two-plane operations must be of
the same type across the planes; for example, it is not possible to perform a PROGRAM
operation on one plane with an ERASE operation on another.
When issuing two-plane program or erase operations, use the READ STATUS (70h)
command and check whether the previous operation(s) failed. If the READ STATUS
(70h) command indicates that an error occurred (FAIL = 1 and/or FAILC = 1), use the
READ STATUS ENHANCED (78h) command to determine which plane operation failed.
Two-Plane Addressing
Two-plane commands require multiple, five-cycle addresses, one address per operational plane. For a given two-plane operation, these addresses are subject to the following requirements:
The LUN address bit(s) must be identical for all of the issued addresses.
The plane select bit, BA[6], must be different for each issued address.
The page address bits, PA[5:0], must be identical for each issued address.
The READ STATUS (70h) command should be used following two-plane program page
and erase block operations on a single die (LUN).
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WE#
ALE
RE#
Page address M
00h
I/Ox
Col
add 1
Col
add 2
Row
add 1
Column address J
Row
add 2
Page address M
Row
add 3
Col
add 1
00h
Plane 0 address
Col
add 2
Row
add 1
Column address J
Row
add 2
Row
add 3
30h
tR
Plane 1 address
R/B#
1
CLE
WE#
ALE
RE#
I/Ox
DOUT 0
DOUT 1
DOUT
06h
Col
add 1
Col
add 2
Row
add 1
Plane 0 data
Row
add 2
Row
add 3
Plane 1 address
E0h
DOUT 0
DOUT 1
DOUT
Plane 1 data
R/B#
Notes:
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RE#
I/Ox
00h
Plane 0 address
Data output
Plane 1 address
05h
Address
(2 cycles)
E0h
Data output
Plane 0 data
Plane 0 data
R/B#
RE#
06h
I/Ox
Data output
Plane 1 address
05h
Address
(2 cycles)
E0h
Data output
Plane 1 data
Plane 1 data
tPROG
R/B#
I/Ox
80h
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input 11h
80h
Address (5 cycles)
Data
input 10h
70h
Status
2nd-plane address
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I/Ox
80h
Address (5 cycles)
Data
85h
input
Data
Address (2 cycles)
input
Different column
address than previous
5 address cycles, for
1st plane only
1st-plane address
11h
80h
Address (5 cycles)
Data
input
2nd-plane address
tPROG
R/B#
85h
I/Ox
Address (2 cycles)
Data
input
10h
Different column
address than previous
5 address cycles, for
2nd plane only
Unlimited number of repetitions
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tCBSY
R/B#
80h
I/Ox
Address/data input
11h
80h
1st plane
Address/data input
15h
2nd plane
tDBSY
tCBSY
R/B#
80h
I/Ox
Address/data input
11h
80h
1st plane
Address/data input
15h
2nd plane
1
2
tDBSY
tLPROG
R/B#
80h
I/Ox
Address/data input
11h
80h
1st plane
Address/data input
10h
2nd plane
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tDBSY
R/B#
00h
I/Ox
85h
2nd-plane source
1
tPROG
R/B#
85h
I/Ox
70h
Status
2nd-plane destination
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RE#
I/Ox
Data output
2nd-plane source
06h
R/B#
RE#
I/Ox
Data output
05h
Data from
2nd-plane source
Data output
2nd-plane
source column address
Optional
tDBSY
tPROG
R/B#
RE#
I/Ox
85h
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85h
70h
Status
2nd-plane destination
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00h
I/Ox
Address (5 cycles)
00h
Address (5 cycles)
1st-plane source
35h
85h
2nd-plane source
Address (5 cycles)
Data
85h
1st-plane destination
Optional
Address (2 cycles)
Data
11h
Unlimited number
of repetitions
tPROG
tDBSY
R/B#
85h
I/Ox
Address (5 cycles)
Data
Optional
2nd-plane destination
85h
Address (2 cycles)
Data
10h
70h
Status
Unlimited number
of repetitions
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tBERS
R/B#
RE#
I/Ox
60h
D1h
60h
1st plane
D0h
70h
Status
or 78h
2nd plane
Dont Care
Optional
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78h
Address (3 cycles)
95
tREA
Status output
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Error Management
Each NAND Flash die (LUN) is specified to have a minimum number of valid blocks
(NVB) of the total available blocks. This means the die (LUNs) could have blocks that
are invalid when shipped from the factory. An invalid block is one that contains at least
one page that has more bad bits than can be corrected by the minimum required ECC.
Additional blocks can develop with use. However, the total number of available blocks
per die (LUN) will not fall below NVB during the endurance life of the product.
Although NAND Flash memory devices could contain bad blocks, they can be used
quite reliably in systems that provide bad block management and error-correction algorithms. This type of software environment ensures data integrity.
Internal circuitry isolates each block from other blocks, so the presence of a bad block
does not affect the operation of the rest of the NAND Flash array.
NAND Flash devices are shipped from the factory erased. The factory identifies invalid
blocks before shipping by attempting to program the bad block mark into every location in the first page of each invalid block. It may not be possible to program every location with the bad block mark. However, the first spare area location in each bad block is
guaranteed to contain the bad block mark. This method is compliant with ONFI Factory
Defect Mapping requirements. See the following table for the first spare area location
and the bad block mark.
System software should check the first spare area location on the first page of each
block prior to performing any PROGRAM or ERASE operations on the NAND Flash device. A bad block table can then be created, enabling system software to map around
these areas. Factory testing is performed under worst-case conditions. Because invalid
blocks could be marginal, it may not be possible to recover this information if the block
is erased.
Over time, some memory locations may fail to program or erase properly. In order to
ensure that data is stored properly over the life of the NAND Flash device, the following
precautions are required:
Always check status after a PROGRAM or ERASE operation
Under typical conditions, use the minimum required ECC (see table below)
Use bad block management and wear-leveling algorithms
The first block (physical block address 00h) for each CE# is guaranteed to be valid
with ECC when shipped from the factory.
Table 19: Error Management Details
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Description
Requirement
2008
2048
Bad-block mark
x8: 00h
x16: 0000h
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Electrical Specifications
Stresses greater than those listed can cause permanent damage to the device. This is
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods can affect reliability.
Table 20: Absolute Maximum Ratings
Voltage on any pin relative to VSS
Parameter/Condition
Voltage input
Symbol
Min
Max
Unit
VIN
0.6
+2.4
0.6
+4.6
0.6
+2.4
0.6
+4.6
TSTG
65
+150
mA
1.8V
3.3V
1.8V
VCC
3.3V
Storage temperature
Short circuit output current, I/Os
Symbol
Min
Typ
Max
Unit
TA
+70
1.8V
VCC
3.3V
Ground supply voltage
VSS
40
+85
1.7
1.8
1.95
2.7
3.3
3.6
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NVB
Device
Min
Max
Unit
Notes
MT29F4G
2008
2048
Blocks
1. Invalid blocks are blocks that contain one or more bad bits. The device may contain bad
blocks upon shipment. Additional bad blocks may develop over time; however, the total
number of available blocks will not drop below NVB during the endurance life of the
device. Do not erase or program blocks marked invalid by the factory.
2. Block 00h (the first block) is guaranteed to be valid with ECC when shipped from the
factory.
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Notes:
Max
Unit
Notes
Input capacitance
CIN
10
pF
1, 2
CIO
10
pF
1, 2
1. These parameters are verified in device characterization and are not 100% tested.
2. Test conditions: TC = 25C; f = 1 MHz; Vin = 0V.
Value
Notes
0.0V to VCC
5ns
VCC/2
Output load
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Conditions
tRC
tRC
Symbol
Min
Typ
Max
Unit
Notes
ICC1
15
30
mA
PROGRAM current
ICC2
15
30
mA
ERASE current
ICC3
15
30
mA
CE# = VIH;
WP# = 0V/VCC
ISB1
mA
ISB2
20
100
IST
10 per die
mA
VIN = 0V to VCC
ILI
10
VOUT = 0V to VCC
ILO
10
I/O[7:0], I/O[15:0],
CE#, CLE, ALE, WE#, RE#,
WP#, R/B#
VIH
0.8 x VCC
VCC + 0.3
VIL
0.3
0.2 x VCC
IOH = 400A
VOH
0.67 x VCC
IOL = 2.1mA
VOL
0.4
VOL = 0.4V
IOL (R/B#)
10
mA
Notes:
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1. Measurement is taken with 1ms averaging intervals and begins after VCC reaches VCC
(MIN).
2. IOL (R/B#) may need to be relaxed if R/B pull-down strength is not set to full.
3. VOH and VOL may need to be relaxed if I/O drive strength is not set to full.
4. Typical and maximum values are for single-plane operation only. If the device supports
dual-plane operation, values are 25mA (TYP) and 35mA (Max).
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Conditions
tRC
tRC
Symbol
Min
Typ
Max
Unit
Notes
ICC1
13
20
mA
1, 2
PROGRAM current
ICC2
10
20
mA
1, 2
ERASE current
ICC3
10
20
mA
1, 2
CE# = VIH;
LOCK = WP# = 0V/VCC
ISB1
mA
ISB2
10
50
IST
10 per die
mA
VIN = 0V to VCC
ILI
10
VOUT = 0V to VCC
ILO
10
I/O[7:0], I/O[15:0],
CE#, CLE, ALE, WE#, RE#,
WP#, R/B#, LOCK
VIH
0.8 x VCC
VCC + 0.3
VIL
0.3
0.2 x VCC
IOH = 100A
VOH
VCC - 0.1
IOL = 100A
VOL
0.1
VOL = 0.2V
IOL (R/B#)
mA
Notes:
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1. Typical and maximum values are for single-plane operation only. Dual-plane operation
values are 20mA (TYP) and 40mA (MAX).
2. Values are for single die operations. Values could be higher for interleaved die operations.
3. Measurement is taken with 1ms averaging intervals and begins after VCC reaches VCC
(MIN).
4. Test conditions for VOH and VOL.
5. DC characteristics may need to be relaxed if R/B# pull-down strength is not set to full.
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Symbol
Min
Max
Unit
Notes
tADL
70
ns
tALH
ns
tALS
10
ns
tCH
ns
tCLH
ns
tCLS
10
ns
tCS
15
ns
tDH
ns
tDS
ns
tWC
20
ns
tWH
ns
tWP
10
ns
tWW
100
ns
Notes:
Symbol
Min
Max
Unit
Notes
tADL
100
ns
tALH
ns
tALS
10
ns
tCH
ns
tCLH
ns
tCLS
10
ns
tCS
25
ns
tDH
ns
tDS
10
ns
tWC
30
ns
tWH
10
ns
tWP
15
ns
tWW
100
ns
Notes:
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2010 Micron Technology, Inc. All rights reserved.
Symbol
Min
Max
Unit
tAR
10
ns
tCEA
30
ns
tCHZ
50
ns
tCLR
10
ns
tCOH
15
ns
tIR
ns
tRC
30
ns
tREA
25
ns
tREH
10
ns
tRHOH
15
ns
tRHW
100
ns
tRHZ
65
ns
tRP
15
ns
tRR
20
ns
tRST
5/10/500
tWB
100
ns
tWHR
80
ns
PDF: 09005aef840a5fc9
m70m_4gb_nand.pdf Rev. L 2/12 EN
Notes
1. AC characteristics may need to be relaxed if I/O drive strength is not set to full.
2. Transition is measured 200mV from steady-state voltage with load. This parameter is
sampled and not 100% tested.
3. The first time the RESET (FFh) command is issued while the device is idle, the device will
be busy for a maximum of 1ms. Thereafter, the device is busy for a maximum of 5s.
4. Do not issue a new command during tWB, even if R/B# is ready.
103
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2010 Micron Technology, Inc. All rights reserved.
Symbol
Min
tAR
Max
Unit
tCEA
10
ns
25
ns
tCHZ
30
ns
tCLR
10
ns
tCOH
15
ns
tIR
ns
tRC
20
ns
tREA
16
ns
tREH
ns
tRHOH
15
ns
tRHW
100
ns
tRHZ
Notes
100
ns
tRLOH
ns
tRP
10
ns
tRR
20
ns
tRST
5/10/500
tWB
100
ns
tWHR
60
ns
PDF: 09005aef840a5fc9
m70m_4gb_nand.pdf Rev. L 2/12 EN
1. AC characteristics may need to be relaxed if I/O drive strength is not set to full.
2. Transition is measured 200mV from steady-state voltage with load. This parameter is
sampled and not 100% tested.
3. The first time the RESET (FFh) command is issued while the device is idle, the device will
go busy for a maximum of 1ms. Thereafter, the device goes busy for a maximum of 5s.
4. Do not issue a new command during tWB, even if R/B# is ready.
104
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2010 Micron Technology, Inc. All rights reserved.
Symbol
Typ
Max
Unit
Notes
NOP
cycles
tBERS
10
ms
tCBSY
600
tDBSY
0.5
tRCBSY
25
tFEAT
tLPROG
tOBSY
30
tLBSY
tPROG
200
600
tPOR
ms
tR
25
PDF: 09005aef840a5fc9
m70m_4gb_nand.pdf Rev. L 2/12 EN
1.
2.
3.
4.
105
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2010 Micron Technology, Inc. All rights reserved.
CLE
CE#
tWB
WE#
tRST
R/B#
I/O[7:0]
FFh
RESET
command
CE#
tCLS
tCLH
tCS
tWP
tCH
WE#
tCEA
tWHR
tRP
tCOH
tCHZ
RE#
tRHZ
tDS
I/O[7:0]
tDH
tIR
tREA
tRHOH
Status
output
70h
Dont Care
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m70m_4gb_nand.pdf Rev. L 2/12 EN
106
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2010 Micron Technology, Inc. All rights reserved.
tCS
CE#
tCLS
tCLH
CLE
tWC
tWP
tWP
tWH
tCH
WE#
tALH
tALS
tALH
tAR
tCHZ
tCEA
tCOH
ALE
RE#
tRHZ
tDS
I/O[7:0]
tDH
tWHR
Row add 1
78h
Row add 2
tREA
tRHOH
Status output
Row add 3
Dont Care
CLE
WE#
tWB
ALE
tRC
RE#
tRR
I/O[7:0]
ECh
R/B#
PDF: 09005aef840a5fc9
m70m_4gb_nand.pdf Rev. L 2/12 EN
00h
tR
tRP
P00
107
P10
P2550
P01
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2010 Micron Technology, Inc. All rights reserved.
CLE
tCLR
CE#
tWC
WE#
tWB
tAR
ALE
tR
tRC
tRHZ
RE#
tRR
I/Ox
00h
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Row
add 3
tRP
DOUT
N
30h
DOUT
N+1
DOUT
M
Busy
RDY
Dont Care
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m70m_4gb_nand.pdf Rev. L 2/12 EN
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CLE
CE#
RE#
ALE
tR
RDY
WE#
I/Ox
00h
Address (5 cycles)
30h
Data output
tCEA
CE#
tREA
tCOH
RE#
Dont Care
Out
I/Ox
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m70m_4gb_nand.pdf Rev. L 2/12 EN
tCHZ
109
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CLE
tCLR
CE#
WE#
tRHW
tWHR
ALE
tRC
tREA
RE#
I/Ox
DOUT
N-1
DOUT
N
05h
Col
add 1
Col
add 2
E0h
DOUT
M
DOUT
M+1
Column address M
RDY
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m70m_4gb_nand.pdf Rev. L 2/12 EN
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CLE
tCLS
tCLS
tCLH
tCS
tCH
tCS
tCLH
tCH
CE#
tWC
WE#
tCEA
tRHW
ALE
tRC
RE#
tDH
tDS
tR
tWB
I/Ox
Col
add 1
00h
Col
add 2
Row
add 1
Column address
00h
Row
add 2
Row
add 3
tRR
30h
DOUT
0
31h
Page address
M
tWB
tREA
tDS
DOUT
1
DOUT
tDH
31h
Page address
M
tRCBSY
RDY
Column address 0
1
CLE
tCLS
tCLH
tCS
tCH
CE#
WE#
tRHW
tRHW
tCEA
ALE
tRC
tRC
RE#
tWB
tREA
tDS
tRR
tDH
I/Ox
DOUT
0
DOUT
1
DOUT
Page address
M
tREA
DOUT
0
31h
tRCBSY
DOUT
1
DOUT
Page address
M+1
DOUT
0
3Fh
tRCBSY
DOUT
1
DOUT
Page address
M+2
RDY
Column address 0
Column address 0
Column address 0
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m70m_4gb_nand.pdf Rev. L 2/12 EN
Dont Care
111
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CLE
tCLS
tCLH
tCH
tCS
CE#
tWC
WE#
ALE
RE#
tDH
tWB
tDS
I/Ox
Col
add 1
00h
Row
add 1
Col
add 2
Column address
00h
Row
add 2
Row
add 3
tR
30h
Col
add 1
00h
Page address
M
Row
add 1
Col
add 2
Column address
00h
Row
add 2
Page address
N
RDY
1
CLE
tCLS
tCLH
tCS
tCH
CE#
WE#
tCEA
ALE
tRC
tWB
RE#
tDS
tDH
I/Ox
tRHW
Col
add 1
Row
add 1
Col
add 2
Column address
00h
RDY
Row
add 2
Row
add 3
Page address
N
tRR
tREA
DOUT
0
31h
DOUT
1
Page address
M
tRCBSY
Column address 0
PDF: 09005aef840a5fc9
m70m_4gb_nand.pdf Rev. L 2/12 EN
DOUT
DOUT
0
3Fh
tRCBSY
DOUT
1
DOUT
Page address
N
Column address 0
Dont Care
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CLE
CE#
WE#
tAR
ALE
RE#
tWHR
I/Ox
90h
tREA
Byte 1
Byte 0
00h or 20h
Byte 2
Byte 3
Byte 4
Address, 1 cycle
CLE
CE#
tWC
tADL
WE#
tWB
tPROG
tWHR
ALE
RE#
I/Ox
80h
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Row
add 3
DIN
N
DIN
M
10h
70h
Status
1 up to m byte
serial Input
RDY
Dont Care
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m70m_4gb_nand.pdf Rev. L 2/12 EN
113
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2010 Micron Technology, Inc. All rights reserved.
CLE
CE#
WE#
ALE
I/Ox
Address (5 cycles)
80h
Data
Data
input
input
10h
tCH
tCS
CE#
tWP
WE#
Dont Care
CLE
CE#
tWC
tADL
tADL
WE#
tWB
tPROG
tWHR
ALE
RE#
I/Ox
80h
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Row
add 3
DIN
M
DIN
N
Serial input
85h
Col
add 1
Col
add 2
DIN
P
DIN
Q
Serial input
10h
70h
Status
READ STATUS
command
RDY
Dont Care
PDF: 09005aef840a5fc9
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114
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CLE
CE#
tADL
tWC
WE#
tWB tCBSY
tWB tLPROG
tWHR
ALE
RE#
I/Ox
80h
DIN
DIN
N
M
Serial input
15h
80h
Col
Col Row Row Row
add 1 add 2 add 1 add 2 add 3
DIN
N
DIN
M
10h
70h
Status
RDY
Last page - 1
Last page
Dont Care
CLE
CE#
tADL
tADL
tWC
WE#
tWHR
tWHR
ALE
RE#
I/Ox
80h
DIN
N
DIN
M
15h
70h
Status
80h
DIN
N
DIN
M
15h
70h
Status
70h
Status
Serial input
Last page 1
Last page
Poll status until:
I/O6 = 1, Ready
Dont Care
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CLE
CE#
tADL
tWC
WE#
tWB tPROG
tWB
tWHR
ALE
RE#
I/Ox
tR
00h
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Row
add 3
35h
(or 30h)
85h
Col
Row Row Row
Col
add 1 add 2 add 1 add 2 add 3
Data
1
Data
N
10h
Status
70h
READ STATUS
Busy command
Busy
RDY
Data Input
Optional
Dont Care
CLE
CE#
WC
WE#
WB
WHR
ALE
RE#
BERS
I/O[7:0]
60h
Row
add 1
Row
add 2
Row
add 3
D0h
70h
Row address
RDY
Status
READ STATUS
command
Busy
I/O0 = 0, Pass
I/O0 = 1, Fail
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116
Dont Care
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2010 Micron Technology, Inc. All rights reserved.
Revision History
Rev. L, Production 2/12
Updated ISB2 spec in 3.3V DC Characteristics and Operating Conditions table
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