VHDL Cheat-Sheet

Copyright: 2009 Bryan Mealy

Concurrent Statements

Sequential Statements

Concurrent Signal Assignment

Signal Assignment

(dataflow model)

target <= expression;

target <= expression;

A <= B AND C;
DAT <= (D AND E) OR (F AND G);

A <= B AND C;
DAT <= (D AND E) OR (F AND G);

Conditional Signal Assignment

if (condition) then
{ sequence of statements }
elsif (condition) then
{ sequence of statements }
else --(the else is optional)
{ sequence of statements }
end if;

target <= expressn when condition else

expressn when condition else
expressn;

F3 <= 1 when (L=0 AND M=0)

1 when (L=1 AND M=1)
0;

(dataflow model)

with chooser_expression select

target <= expression when choices,
expression when choices;

11,
10,
01,
00,
others;

Process
(behavioral model)

opt_label: process(sensitivity_list)
begin
{sequential_statements}
end process opt_label;
proc1: process(A,B,C)
begin
if (A = 1 and B = 0) then
F_OUT <= 1;
elsif (B = 1 and C = 1) then
F_OUT <= 1;
else
F_OUT <= 0;
end if;
end process proc1;

if
(SEL =
elsif (SEL =
elsif (SEL =
elsif (SEL =
else F_CTRL
end if;

else
else

Selective Signal Assignment

with SEL select

MX_OUT <= D3 when
D2 when
D1 when
D0 when
0 when

if statements

(dataflow model)

111) then
110) then
101) then
000) then
<= 0;

F_CTRL
F_CTRL
F_CTRL
F_CTRL

<=
<=
<=
<=

case statements
case (expression) is
when choices =>
{sequential statements}
when choices =>
{sequential statements}
when others => -- (optional)
{sequential statements}
end case;
case ABC is
when 100 =>
when 011 =>
when 111 =>
when others =>
end case;

F_OUT
F_OUT
F_OUT
F_OUT

<=
<=
<=
<=

1;
1;
1;
0;

D(7);
D(6);
D(1);
D(0);

Description
Typical logic
circuit

CKT Diagram

VHDL Model
entity my_ckt is
Port ( A,B,C,D : in std_logic;
F : out std_logic);
end my_ckt;
architecture ckt1 of my_ckt is
begin
F <= (A AND B) OR (C AND (NOT D));
end ckt1;

4:1 Multiplexor

architecture ckt2 of my_ckt is

begin
F <= 1 when (A = 1 AND B = 1)
1 when (C = 1 AND D = 0)
0;
end ckt2;
entity MUX_4T1 is
Port ( SEL : in std_logic_vector(1
D_IN : in std_logic_vector(3
F : out std_logic);
end MUX_4T1;
architecture my_mux of MUX_4T1 is
begin
F <= D_IN(0) when (SEL = "00")
D_IN(1) when (SEL = "01")
D_IN(2) when (SEL = "10")
D_IN(3) when (SEL = "11")
'0';
end my_mux;

2:4 Decoder

downto 0);
downto 0);

else
else
else
else

entity DECODER is
Port ( SEL : in std_logic_vector(1 downto 0);
F : out std_logic_vector(3 downto 0));
end DECODER;
architecture my_dec
begin
with SEL select
F <= "0001" when
"0010" when
"0100" when
"1000" when
"0000" when
end my_dec;

8-bit register
with load enable

else
else

of DECODER is

"00",
"01",
"10",
"11",
others;

entity REG is
port ( LD,CLK : in std_logic;
D_IN : in std_logic_vector (7 downto 0);
D_OUT : out std_logic_vector (7 downto 0));
end REG;
architecture my_reg of REG is
begin
process (CLK,LD)
begin
if (LD = '1' and rising_edge(CLK)) then
D_OUT <= D_IN;
end if;
end process;
end my_reg;

8-bit up/down
counter with
asynchronous
reset

entity COUNT_8B is
port ( RESET,CLK,LD,UP : in std_logic;
DIN : in std_logic_vector (7 downto 0);
COUNT : out std_logic_vector (7 downto 0));
end COUNT_8B;
architecture my_count of COUNT_8B is
signal t_cnt : std_logic_vector(7
begin
process (CLK, RESET)
begin
if (RESET = '1') then
t_cnt <= (others => 0); -elsif (rising_edge(CLK)) then
if (LD = '1') then
t_cnt
else
if (UP = '1') then t_cnt
else
t_cnt
end if;
end if;
end if;
end process;
COUNT <= t_cnt;
end my_count;

downto 0);

clear
<= DIN;

-- load

<= t_cnt + 1; -- incr

<= t_cnt - 1; -- decr