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64K SRAM
Echo Processor
DataSheet
Version: 1.0
Jun/2002
http://www.topro.com.tw
HQ:
5F, No.10, Prosperity Road 1, Science-Based Industrial Park, Hsinchu 300, Taiwan, R.O.C
300 10 5
TPE:
5 F, No.27, Min Chuan W. Rd. Taipei 104, Taiwan, R.O.C
104 27 5
SHENZHEN:
Room 802, Tower A, World Trade Plaza, Fahong Rd., Fatian, Shenzhen, China
9 A 802 (518033)
Page 1 of 1
TOPRO CONFIDNETIAL
2003/7/28 Print
TP5208
64K SRAM
Echo Processor
Description
The TP5208 is a developed for producing echo effects added to voice signals picked up by
microphone for karaoke applications. The IC has the largest memory among the digital delay
series. As its design is aimed at high performance, it is best suited to provide radio cassette tape
recorders and miniature unit audio system with quality echo function.
Being pin compatible with the Mitsubishi M65831AP/FP, M65830CP/FP, and M65843AP/FP,
the TP5208 is suitable for upgrading the series.
Features
Built-in input/output filters, A-D and D-A converters and memory realize a delay system
with only a single chip
Capable of composing low-noise and lowdistortion delay system at low cost by ADM
system (No= -88dB typ, THD=0.17% typ)
Control mode selections available from 2 kinds: easy mode using parallel data and
microcomputer mode using serial data
Sleep mode can be selected to stop IC functions
Built-in automatic reset circuit
Page 2 of 2
TOPRO CONFIDNETIAL
2003/7/28 Print
TP5208
64K SRAM
Echo Processor
Pin Configuration
VDD
24
VCC
XIN
23
LPF1 IN
XOUT
22
LPF1 OUT
D1/REQ
21
OP1 OUT
D2/SCK
20
OP1 IN
D3/DATA
19
REF
D4/IDSW
18
CC1
TEST
17
CC2
EASY/U-COM
16
OP2 IN
SLEEP
10
15
OP2 OUT
D-GND
11
14
LPF2 IN
A-GND
12
13
LPF2 OUT
24 PINS DIP/SOP
Page 3 of 3
TOPRO CONFIDNETIAL
2003/7/28 Print
TP5208
64K SRAM
Echo Processor
Pin Description
No.
Symbol
1. VDD
2. XIN
3. XOUT
Name
Digital VDD
Oscillator input
Oscillator input
4.
D1/REQ
Delay1/Request
5.
D2/SCK
Delay2/Shift clock
6.
D3/DATA
Delay3/Serial data
7.
D4/IDSW
Delay4/ID switch
8.
TEST
Test
9.
EASY/U-COM
EASY/U-COM
10. SLEEP
Sleep
11. DGND
Digital GND
12. AGND
13. LPF2 OUT
14. LPF2 IN
15. OP2 OUT
16. OP2 IN
17. CC2
18. CC1
19. REF
20. OP1 IN
21. OP1 OUT
22. LPF1 OUT
23. LPF1 IN
24. VCC
Analog GND
Low pass filter2 output
Low pass filter2 input
OP-AMP2 output
OP-AMP2 input
Current control 2
Current control 1
Reference
OP-AMP1 input
OP-AMP1 output
Low pass filter1 output
Low pass filter1 input
Analog Vcc
Page 4 of 4
I /O
Function
Supply voltage
I
O Connects to 2MHz ceramic filter
Easy mode: inputs D1 data
I
U-COM mode: inputs request data
Easy mode: inputs D2 data
I
U-COM mode: inputs shift clock
Easy mode : inputs D3 data
I
U-COM mode: inputs shift data
Easy mode : inputs D4 data
I
U-COM mode: controls ID code
I L= normal mode
H= Easy mode
I
L= U-COM mode
H= sleep mode
I
L= normal mode
Connects to analog GND at one point
Connects to analog GND
O
Forms low pass filter with external C, R
I
O
Forms integrator with external C.R
I
= 1/2 VCC
I
Forms integrator with external C, R
O
O
Forms low pass filter with external C, R
I
Supply voltage
TOPRO CONFIDNETIAL
2003/7/28 Print
TP5208
64K SRAM
Echo Processor
Operation
1) EASY Mode (EASY / U-COM =H)
D4
D3
D2
D1
fs
Td
666
12.3
666
24.6
666
36.9
666
49.2
666
61.4
666
73.7
666
86.0
666
98.3
333
110.6
333
122.9
333
135.2
333
147.5
333
159.7
333
172.0
333
184.3
333
196.6
Page 5 of 5
TOPRO CONFIDNETIAL
2003/7/28 Print
TP5208
64K SRAM
Echo Processor
2) U-COM Mode (EASY / U-COM =L)
H
Delay Time
H
= SLEEP Mode
= MUTE
ID Code
This Timing chart shows that delay time is set by serial data from U-COM.
DATA signal is latched at the falling edge of SCK signal, the last ten data
are set at the rising edge of REQ signal when ID codes are satisfied.
ID1, ID3: L
ID2
:H
ID4
Page 6 of 6
: equal to IDSW
TOPRO CONFIDNETIAL
2003/7/28 Print
TP5208
64K SRAM
Echo Processor
Page 7 of 7
TOPRO CONFIDNETIAL
2003/7/28 Print
TP5208
64K SRAM
Echo Processor
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TOPRO CONFIDNETIAL
2003/7/28 Print
TP5208
64K SRAM
Echo Processor
Page 9 of 9
TOPRO CONFIDNETIAL
2003/7/28 Print
TP5208
64K SRAM
Echo Processor
Page 10 of 10
TOPRO CONFIDNETIAL
2003/7/28 Print
TP5208
64K SRAM
Echo Processor
REQ, SCK, DATA Input Timing
Symbol
Parameter
min
Page 11 of 11
t1
ds
t2
t3
Range
typ
Units
max
250
ns
50
100
t1/2
ns
100
t1/2
ns
t4
100
ns
t5
250
ns
TOPRO CONFIDNETIAL
2003/7/28 Print
TP5208
64K SRAM
Echo Processor
3) MUTING
(a) EASY mode
Automatic mute upon changing delay time, cancelling SLEEP mode
and power-on.
(b) U-COM mode
MUTE= H: mute
MUTE= L: automatic mute
Automatic Mute:
Delay Signal Before Change Mode
Page 12 of 12
TOPRO CONFIDNETIAL
2003/7/28 Print
TP5208
64K SRAM
Echo Processor
Power On
4) SLEEP Mode
SLEEP data is
H: clock and RAM stop to reduce circuit current (SLEEP mode)
L: normal operation
5) System Reset
Automatically reset power-on. The reset time is about 120msec.
Delay time is set at 147.5msec.
Page 13 of 13
TOPRO CONFIDNETIAL
2003/7/28 Print
TP5208
64K SRAM
Echo Processor
Absolute Maximum Ratings (Ta=25, unless otherwise noted)
Symbol
Parameter
Ratings
Units
Vcc
Supply Voltage
6.5
Icc
Supply Current
100
mA
Pd
Power Dissipation
1.7
Topr
Operating Temperature
-20~75
Tstg
Storage Temperature
-25~125
Page 14 of 14
Parameters
Min
Range
Typ
Units
Max
VCC
Supply Voltage
4.5
5.5
VDD
Supply Voltage
4.5
5.5
VCC-VDD
Difference Voltage
-0.3
0.3
fck
Clock Frequency
MHz
VIH
0.7VDD
VIL
TOPRO CONFIDNETIAL
V
0.3VDD
2003/7/28 Print
TP5208
64K SRAM
Echo Processor
Electrical Characteristics
(Vcc=5.0Vfin=1KHzVi=100mVrmsfck=2MHzTa=25, unless otherwise noted)
Symbol
parameter
Test Conditions
Icc
Circuit Current
Gv
Vomax
THD
Typ
Max
Units
No Signal
36
50
mA
Voltage gain
RL=47K
-0.5
2.5
dB
Maximum Output
Voltage
THD=10%
30KHz
L.P.F.
Output Distortion
Min
1.0
fs=666KHz
fs=333Khz
Upon Changing Delay Time
TMUTE
Mute Time
No
1.6
Vrms
0.17
0.8
0.4
1.2
508
528
548
ms
508
528
548
ms
-88
-80
dBV
DIN-AUDIO(fs=333KHz)
D.C. Characteristics
Symbol
Vcc
Supply Voltage
Icc
Supply Current
VIH
VIL
Page 15 of 15
Range
Parameters
TOPRO CONFIDNETIAL
Units
Min
Typ
Max
4.5
5.5
60
80
mA
0.7VDD
V
0.3VDD
2003/7/28 Print
TP5208
64K SRAM
Echo Processor
Application Circuit
IN
20k
1u
22nF
0.01u
0.047u
CC2
TEST
EASY/u_com OP2_in
OP1_out
2M
Hz
100p
100p
2.7k
OUT
13
LPF2_out
CC1
D4
14
1u
AGND
REF
LPF1_out
D3
15
OP1_in
16
D2
17
D1
18
XOUT
19
LPF1_in
20
XIN
21
Vcc
22
VDD
23
10k
2.2nF
620
0.33u
0.33u
DGND
47u
2.2nF
LPF2_in
0.047u
0.1u
100u
10k
620
24
3k
OP2_out
22nF
0.01u
30k
10k
10k
SLEEP
1u
10
11
12
SETING DELAY
TIME
EASY Mode
20k
IN
1u
0.1u
10k
47u
10k
2.2nF
620
0.33u
0.33u
1u
2.7k
OUT
2.2nF
LPF2_out
13
AGND
14
LPF2_in
15
DGND
EASY/u_com OP2_in
CC2
CC1
REF
OP1_out
LPF1_out
TEST
16
IDSW
17
DATA
18
SCK
19
REQ
20
XOUT
21
XIN
22
VDD
LPF1_in
23
0.047u
0.047u
OP2_out
620
Vcc
100u
0.01u
22nF
10k
10k
24
3k
SLEEP
22nF
0.01u
30k
OP1_in
1u
10
11
12
2M
Hz
100p
100p
u-COM
U-COM Mode
Page 16 of 16
TOPRO CONFIDNETIAL
2003/7/28 Print
TP5208
64K SRAM
Echo Processor
IC Package Information
TP5208P(24-DIP)
Page 17 of 17
TOPRO CONFIDNETIAL
2003/7/28 Print