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VLSI INTERVIEW QUESTIONS

1.

Why does the present VLSI circuits use MOSFETs instead of BJTs explain?

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10.

What are the various regions of operation of MOSFET? How are those regions used? Explain?

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13.

Explain cross-talk. How can it be divided?

What is threshold voltage Explain?


What does it mean term the channel is pinched off?
Explain the three regions of operation of a MOSFET. and Give Difference?
What is channel length modulation Explain?
Explain depletion region. Briefly?
What is body effect . Explain?
Give various factors on which threshold voltage depends.on ?
Explain:
a.) Stuck-at-faults
b.) ATPG
Explain charge sharing between bus and memory element. ?
Situation - Two inverters are connected in series. The widths of pmos and nmos transistors of the second inverter are 100 and 50
respectively. If the fan-out is assumed to be 3, what would be the widths of the transistors in the first inverter?

14.

Explain:
a.) Clock Race
b.) Single Phase Clocking
c.) Double Phase Clocking

15.

Explain the following effects and how would you eliminate them.
a.) Hot electron effect.
b.) Latchup problem

16.

Explain the following:


a.) Channel length modulation
b.) Repeaters in VLSI design
c.) Tunneling problem

17.

Explain:
a.) Mobility of electrons
b.) Mobility of holes
c.) Stage Ratio

18.

How does temperature affect the following?


a.) Threshold Voltage
b.) Mobility

19.

Write short notes on following:


a.) PALs
b.) PLAs
c.) FPGAs
d.) ASICs
e.) PLDs

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21.

How would you make a XOP gate using NAND gates?

22.

. Explain the following:


a.) Leakage current
b.) Domino Logic

23.

Differentiate between:
a.) Testing and Verification
b.) Latch and Flip Flop
c.) Depletion mode devices and Enhancement mode devices

24.

Explain elextron migration. What would you do if you want to eliminate it?

List the critical parameter of following:


a.) Latch
b.) Flip-flop

25.

Explain:
a.) Elmore delay algorithm
b.) False and multi cycle paths
c.) Metastability

26.

Create the following:


a.) An OR gate using NAND gate.
b.) NAND gate using a 2:1 multiplexer.
c.) NOR gate using a 2:1 multiplexer.

27.

What are the advantages and disadvantages of Bi-CMOS process?

28.

What do you mean by negative biased instability? How can you avoid it?

29.

What factors would you consider while choosing a technology library for a design?

30.

22. Explain clock skew. How will you avoid it?

31.

Situation:
a.) You want to equate rise and fall times in a inverter. How would you do that?
b.) A resistor is added in series with the drain in a mos transistor. What would happen?
c.) Suppose Vds is increased over saturation. What would happen?

32.

What will be the effect of increase in the number of contacts and vias in the interconnect layers?

33.

25. Explain
a.) Body bias
b.) Charge sharing on a bus

34.

What are the various types of scaling?

35.

List the various regions of operation in a mos transistor.?

36.

In the I-V characteristics curve, what does flat or constant saturation curve signify?

37.

Can both pmos and nmos transistors pass good 1 and good 0? Explain?

38.

Why is only nmos used in pass transistor logic?

39.

. You want to reduce charge sharing in dynamic logic. What are the different methologies you can use?

40.

Explain setup and hold time violations? How can they be eliminated?

41.

What is the effect of increasing thickness and increasing length on the resistance of a metal layer?

42.

Explain the working of a bacis sram and dram?

43.

How does Vdd effect delay?

44.

You want to change the voltage for less delay. What limitation you might face? How would you achieve this?

45.

37. What is the role of a sense amplifier in SRAM?

46.

You are given NAND gates and NOR gates, which of them would you take? Why?

47.

39. Explain Noise margin in an inverter. How would you overcome it?

48.

40. What is the effect of delay, rise and fall times with increase in load capacitance?

49.

41. Which is more time consuming? Why?


a.) Read Operations
b.) Write Operations

50.

Why is size of pmos transistor chosen to be close to three times of an nmos transistor?

51.

43. Why should there be less number of CMOS transistors in a series?

52.

a.) What are the substrates of pmos and nmos transistors connected to?

53.

b.) What would happen if the connections are interchanged with each other?

54.

45. While trying to drive a huge load, driver circuits are designed with number of stages with a gradual increase in sizes. Why is it done?
Why can't you use just one big driver gate?

55.

What is latch up?

56.

Why is NAND gate preferred over NOR gate for fabrication?

57.

What is Noise Margin? Explain the procedure to determine Noise Margin

58.

Explain sizing of the inverter?

59.

Let A and B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later
than signal B. To optimize delay of the two series NMOS inputs A and B which one would
you place near to the output?

60.

What happens to delay if you increase load capacitance?

61.

What happens to delay if we include a resistance at the output of a CMOS circuit?

62.

For CMOS logic, give the various techniques you know to minimize power consumption?

63.

What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a
Bus?

64.

Why do we gradually increase the size of inverters in buffer design? Why not give the
output of a circuit to one large inverter?

65.

Give the expression for CMOS switching power dissipation?

66.

What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you
avoid Latch Up?

67.

How does Resistance of the metal lines vary with increasing thickness and increasing
length?

68.

What are the limitations in increasing the power supply to reduce delay?

69.

When are DFT and Formal verification used?

70.

What is Synthesis?

71.

What is DFT ?

72.

What is LVs and why do we do that. What is the difference between LVS and DRC?

73.

What is the purpose of DRC?

74.

Suggest some ways to increase clock frequency?

75.

What are different types of timing verifications?

76.

What are dcm's?why they are used?

77.

Difference between FPGA and CPLD?

78.

What are different types of FPGA programming modes?what are you currently using ?
how to change from one to another?

79. What is minimum and maximum frequency of dcm in spartan-3 series fpga?
80.

What is FPGA ?

81.

What is metastability? When/why it will occur?Different ways to avoid this?

82.

A good question on Layouts. Give 5 important Design techniques you would follow when
doing a Layout for Digital Circuits?

83.

All of us know how an inverter works. What happens when the PMOS and NMOS are
interchanged with one another in an inverter?

84.

Why PMOS and NMOS are sized equally in a Transmission Gates?

85.

In CMOS technology, in digital design, why do we design the size of pmos to be higher
than the nmos.What determines the size of pmos wrt nmos. Though this is a simple
question try to list all the reasons possible?

86.

Why do we gradually increase the size of inverters in buffer design when trying to drive a
high capacitive load? Why not give the output of a circuit to one large inverter?

87.

Which transistor has higher gain. BJT or MOS and why?

88.

What is the fundamental difference between a MOSFET and BJT ?

89.

Why is the substrate in NMOS connected to Ground and in PMOS to VDD?

90.

What is the fundamental difference between a MOSFET


and BJT ?

91.

Explain zener breakdown and avalanche breakdown?

92.

What is the basic difference between Analog and


Digital Design?

93.

What is ring oscillator? And derive the freq of


operation?

94.

What are RTL, Gate, Metal and FIB fixes? What is a


"sewing kits"?

95.

what is slice,clb,lut?

96.

Can a clb configured as ram?

97.

What is FPGA you are currently using and some of main


reasons for choosing it?

98.

Draw a rough diagram of how clock is routed through


out FPGA?

99.

Why is map-timing option used?

100.

What are different types of timing verifications?

What is frequency of operation and equivalent gate


count of u r project?

101.

How many global buffers are there in your current


fpga,what is their significance?

102.

103.

Compare PLL & DLL ?

Given two ASICs. one has setup violation and the


other has hold violation. how can they be made to work
together without modifying the design?

104.

105.

Suggest some ways to increase clock frequency?

What is the significance of contamination delay in


sequential circuit timing?

106.

107.

Can you draw general structure of fpga?

100.Can you explain what struck at zero means?


101.Can you list out some of synthesizable and non
synthesizable constructs?
102.Tell me some of features of FPGA you are currently
using?
103. Suppose for a piece of code equivalent gate count is
600 and for another code equivalent gate count is 50,000
will the size of bitmap change?in other words will size of
bitmap change it gate count change?
104. Tell me some of constraints you used and their purpose
during your design?
105. What logic is inferred when there are multiple assign
statements targeting the same wire?
106. What do conditional assignments get inferred into?
107. What value is inferred when multiple procedural assignments
made to the same reg variable in an always block?
108. What are standard Cell's?
109. What is Different Logic family ?
110. What is Different Types of IC packaging ?
111. What is Stuck-at fault ?
112. What is Substrate coupling ?
113. What Physical verification ?
114. What are different ways to synchronize between two
clock domains?
115. What is glitch? What causes it (explain with waveform)?
How to overcome it?

116. What is difference between latch and flipflop?


117. Given only two xor gates one must function as buffer
and another as inverter?
118. Build a 4:1 mux using only 2:1 mux?
119. Difference between heap and stack?
120. Difference between mealy and moore state machine?
121. How to find out longest path?
122. Difference between onehot and binary encoding?
123 Given the following FIFO and rules, how deep does the
FIFO need to be to prevent underflow or overflow?
RULES:
1) frequency(clk_A) = frequency(clk_B) / 4
2) period(en_B) = period(clk_A) * 100
3) duty_cycle(en_B) = 25%

124. What will happen if contents of register are shifter left,


right?
125. Implement an AND gate using mux?
126. Tell some of applications of buffer?
127 What is significance of ras and cas in SDRAM?
128. How to achieve 180 degree exact phase shift?
129 Draw the state diagram to output a "1" for one cycle if
the sequence "0110" shows up (the leading 0s cannot be
used in more than one sequence)?
130. How to calculate maximum operating frequency?
131. what are the differences between SIMULATION and SYNTHESIS?

132 Can u tell me the differences between latches & flipflops?


133. What is slack?
134. Equivalence between VHDL and C?
135. RTL and Behavioral?
136. xplain the flow of physical design and inputs and outputs for each step in flow.

Physical Design Flow?


137. How chance of metastable state failure can be reduced?
138. What are the advantages of using synchronous reset ?
139. What are the disadvantages of using synchronous reset ?
140. What are the advantages of using asynchronous reset ?
141. What are the disadvantages of using asynchronous reset ?
142. Is verilog/VHDL is a concurrent or sequential language?
143. What are the 3 fundamental operating conditions that determine the delay characteristics of gate? How
operating conditions affect gate delay?
144. Is verilog/VHDL is a concurrent or sequential language?
145. In a system with insufficient hold time, will slowing down the clock frequency help?
146 Explain various adders and difference between them?
147 How can you construct both PMOS and NMOS on a single substrate?
148 What happens when the gate oxide is very thin?
What is SPICE?
What are the differences between IRSIM and SPICE?
What are the differences between netlist of HSPICE and Spectre?
Implement F = AB+C using CMOS gates?
What is hot electron effect?
Define threshold voltage?
List out the factors affecting power consumption on a chip?
What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?
What is clock feed through?
Implement an Inverter using a single transistor?
What is Fowler-Nordheim Tunneling?
Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?
Draw the Differential Sense Amplifier and explain its working. How to size this circuit?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
Draw the SRAM Write Circuitry
How did you arrive at sizes of transistor in SRAM?
How does the size of PMOS pull up transistors for bit and bitbar lines affect SRAMs performance?
What is the critical path in a SRAM?
Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
Give a big picture of the entire SRAM layout showing placements of SRAM cells, row decoders, column decoders, read
circuit, write circuit and buffers.
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
What is the difference between using direct instantiations and component ones except that you need to declare the
component?
2. What is the use of BLOCKS?

3. What is the use of PROCEDURES?


4. What is the usage of using more then one architecture in an entity?
5. What is a D-latch? Write the VHDL Code for it?
6. Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?
7. Differences between Signals and Variables in VHDL? If the same code is written

using Signals and Variables what does it

synthesize to?
8. Differences between functions and Procedures in VHDL?
9. Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?

1. Give two ways of converting a two input NAND gate to an inverter


2. Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any
sequential ckt)
3. What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock
frequency of a circuit?
4. Give a circuit to divide frequency of clock cycle by two
5. Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock)
6. Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the
combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)
7. The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this?
8. What are the different Adder circuits you studied?
9. Give the truth table for a Half Adder. Give a gate level implementation of the same.
10. Draw a Transmission Gate-based D-Latch.
11. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output)
12. How do you detect if two 8-bit signals are same?
13. How do you detect a sequence of "1101" arriving serially from a signal line?
14. Design any FSM in VHDL or Verilog

Verilog

What is the difference between $display and $monitor and $write and $strobe?

What is the difference between code-compiled simulator and normal simulator?

What is the difference between wire and reg?

What is the difference between blocking and non-blocking assignments?

What is the significance Timescale directivbe?

What is the difference between bit wise, unary and logical operators?

What is the difference between task and function?

What is the difference between casex, casez and case statements?

Which one preferred-casex or casez?

For what is defparam used?

What is the difference between = = and = = = ?

What is a compiler directive like include and ifdef?

Write a verilog code to swap contents of two registers with and without a temporary register?

What is the difference between inter statement and intra statement delay?

What is delta simulation time?

What is difference between Verilog full case and parallel case?

What you mean by inferring latches?

How to avoid latches in your design?

Why latches are not preferred in synthesized design?

How blocking and non blocking statements get executed?

Which will be updated first: is it variable or signal?

What is sensitivity list?

If you miss sensitivity list what happens?

In a pure combinational circuit is it necessary to mention all the inputs in

sensitivity disk? If yes, why? If not,

why?

In a pure sequential circuit is it necessary to mention all the inputs in sensitivity disk? If yes, why? If not, why?

What is general structure of Verilog code you follow?

What are the difference between Verilog and VHDL?

What are system tasks?

List some of system tasks and what are their purposes?

What are the enhancements in Verilog 2001?

Write a Verilog code for synchronous and asynchronous reset?

What is pli? why is it used?

What is file I/O?

What is difference between freeze deposit and force?

Will case always infer priority register? If yes how? Give an example.

What are inertial and transport delays ?

What does `timescale 1 ns/ 1 ps signify in a verilog code?

How to generate sine wav using verilog coding style?

How do you implement the bi-directional ports in Verilog HDL?

How to write FSM is verilog?

What is verilog case (1)?

What are Different types of Verilog simulators available?

What is Constrained-Random Verification ?

How can you model a SRAM at RTL Level?

What are High-Vt and Low-Vt cells?


Give 5 important Design techniques you would follow when doing a Layout for Digital Circuits?
Why now a days we use copper (Cu) and not Al for metal layers.?