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A Low Power and High Sensing Margin Non-Volatile Full

Adder Using Racetrack Memory


ABSTRACT:
The continuing miniaturization of complementary metal oxide semiconductor
(CMOS) technology has brought in two critical issuesthe high power and long
global interconnection delay. Magnetic tunnel junction (MTJ) nanopillar with the
advantages of non-volatility, fast switching speed, and high density promises new
designs and architectures to significantly alleviate the power and delay issues. This
paper presents a new design of the key component in processorsmulti-bit full
adder, whose input and output data are stored in perpendicular magnetic anisotropy
(PMA) domain wall (DW) racetrack memory (RTM). The MTJ sharing technique
with demultiplexing approach is used in the proposed non-volatile full adder
(NVFA) to greatly reduce the area and power, and improve the speed and sensing
margin as well. The proposed NVFA scheme can also apply to the other types of
non-volatile memory (NVM). Compared to the state-of-art magnetic full adder
(MFA), our proposed NVFA has reduced the power and area by 5.9 times and 50%,
respectively. It also accelerates the speed by 10% and increases the sensing margin
by more than 66%.

EXISTING SYSTEM:
COMPLEMENTARY metal oxide semiconductor (CMOS) technology has been
scaled down continuously for more than four decades [1][4] for higher integration
and better performance. The semiconductor industry has showcased a tremendous
growth in the number of transistors per integrated circuit for several decades, as
predicted by Moores law [5]. However, the leakage power dissipation is rapidly
becoming a substantial contributor in memories or state retention in duty cycled
systems due to scaling, which poses significant challenge to achieve the goal of
low power [6], [7]. In addition, the scaling has led to the growth of the parasitic
resistance and capacitance in global interconnections of advanced very large scale
integration (VLSI) systems, thus greatly increases both dynamic power and delay
[8], [9]. Therefore, the reduction of power consumption and interconnection delay
are the two major targets for the next generation VLSI systems. Technological
advancements are the major propellant for architectural innovations [10]. The
recent resistive non-volatile memory (NVM) technologies provide a new solution
to address the high power and long interconnection delay is- sues by integrating the
memories on top of the logic circuits. The NVM could be used to directly store the
computing results, and be recalled for other operations. It not only shortens the
length between logic and memory, but also reduces the number of transistors to
achieve a higher density.

PROPOSED SYSTEM:
This paper presents a new logic-in-memory architecture based NVFA circuit
using racetrack memory (RTM). RTM is one of the most promising resistive
NVMs, with the advantages of high density, high speed, and low power [16]. The
NVFA could be designed as the standard cell to maintain the compatibility with
digital design flow in order to reduce the design cycle. Logic operations of the
NVFA are processed directly with the magnetic data stored in ferromagnetic strips.
The CARRY and SUM results are written to the output ferromagnetic strips for the
next operations. Long latency and high dynamic power due to data moving can be
greatly economized. Moreover, as only one strip is used for each input or output
signal, thus the data write and propagation energy is significantly reduced.
Demultiplexing approach is used to share the same input MTJs for both SUM and
CARRY operations. The proposed NVFA scheme also suits for the other types of
NVMs, with slightly changing of the write circuit. Compared to the conventional
RTM based NVFA, our proposed RTM based NVFA has reduced the power and
area by 5.9 times and 50%, respectively. It also improves the speed, and sensing
margin by 10% and more than 66%, respectively.

SOFTWARE IMPLEMENTATION:
Modelsim 6.0
Xilinx 14.2

HARDWARE IMPLEMENTATION:
SPARTAN-III, SPARTAN-VI

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