Digital Electronics - Lab Manual'121

EXP.
NO: 1
DATE :
STUDY OF LOGIC GATES
AIM:
To study about logic gates and verify their truth tables.
APPARATUS REQUIRED:
SL No.
COMPONENT
SPECIFICATION
QTY
1.
AND GATE
IC 7408
2.
OR GATE
IC 7432
3.
NOT GATE
IC 7404
4.
NAND GATE 2 I/P
IC 7400
5.
NOR GATE
IC 7402
6.
X-OR GATE
IC 7486
7.
NAND GATE 3 I/P
IC 7410
8.
IC TRAINER KIT
9.
PATCH CORD
14
THEORY:
Circuit that takes the logical decision and the process are called logic gates. Each gate has
one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal
gates. Basic gates form these gates.
AND GATE:
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs
is low.
OR GATE:
The OR gate performs a logical addition commonly known as OR function. The
output is high when any one of the inputs is high. The output is low level when both the inputs
are low.
NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low. The
output is low when the input is high.
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are
low and any one of the input is low .The output is low level when both inputs are high.
NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low.
The output is low when one or both inputs are high.
X-OR GATE:
The output is high when any one of the inputs is high. The output is low when both the
inputs are low and both the inputs are high.
AND GATE:
SYMBOL:
PIN DIAGRAM:
2
Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32
OR GATE:
NOT GATE:
SYMBOL:
PIN DIAGRAM:
3
X-OR GATE :
SYMBOL :
PIN DIAGRAM :
2-INPUT NAND GATE:

SYMBOL:
PIN DIAGRAM:
4
3-INPUT NAND GATE :
NOR GATE:
5
PROCEDURE:
6
a. Give connections as per the circuit diagram

b. Inputs are given to the circuit making high 1 i.e. +5 V or + Vcc supply to the
14th pin and for low 0 i.e. GND to the 7th pin of the gate IC
c. Depending upon the truth table, if the LED glow it represent 1 and else it
represents 0
d. Verify the truth table as given
e. Repeat the procedure steps for different gates.
RESULT:
Thus the truth tables for logic gates are verified using IC trainer kit.
EXP. NO: 2
7
DESIGN AND IMPLEMENTATION HALF ADDER AND
DATE:
FULL ADDER.
AIM:
To construct half and full adder circuits and verify the truth table
APPARATUS REQUIRED:
S.NO
1
2
3
4
Particular Name
Digital IC trainer kit
IC7432
IC7408, IC7486
Connecting Wires
SPECIFICATION
---QUAD
QUAD
QUANTITY
1
1
1 each
CIRCUIT DIAGRAM:
HALF ADDER:
IC 7486
3
SUM
S = A (+)B
IC 7408
1
3
CARRY
Cr = A . B
8
TRUTH TABLE
A
0
0
1
1
0
1
0
1
SUM
( S)
0
1
1
0
K-Map for SUM:
SUM = AB + AB
CARRY
( Cr )
0
0
0
1
K-Map for CARRY:
CARRY = AB
9
10
K-Map for SUM:
SUM = ABC + ABC + ABC + ABC
CARRY = AB + BC + AC
TRUTH TABLE
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
S
0
1
1
0
1
0
0
1
Cr
0
0
0
1
0
1
1
1
11
PROCEDURE:
1. Give connections as per the circuit diagram
2. Inputs are given to the circuit making high 1 i.e. +5 V or
+ Vcc supply to the 14th pin and for low 0 i.e. GND to the 7th
pin of the gate IC
3. Depending upon the truth table, if the LED glow it represent 1 and else it represents 0
4. Verify the truth table as given for half adder
5. Repeat the procedure steps for full adder circuit
RESULT:
The half and full adder circuits are constructed and verified.
12
EXP. NO: 3
DATE:
DESIGN AND IMPLEMENTATION OF SUBTRACTORS

USING LOGIC GATES
AIM:
To construct half and full subtractor circuits and verify the truth table
APPARATUS REQUIRED:
S.NO
1
2
3
4
5
6
Particular Name
IC7404
IC7432
IC7408
IC7486
Connecting Wires
SPECIFICATION
----
QUANTITY
1
1 each
1 each
1 each
1 each
CIRCUIT DIAGRAM:
13
TRUTH TABLE:
Half Subtractor
X
0
0
1
1
Y
0
1
0
1
Diff
0
1
1
0
Borr
0
1
0
0
FULL SUBTRACTOR:
14
FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:
TRUTH TABLE:
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Diff
0
1
1
0
1
0
0
1
Borro
0
1
1
1
0
0
0
1
15
PROCEDURE:
2. Inputs are given to the circuit making high 1 i.e. +5 V or + Vcc supply to the 14th
pin and for low 0 i.e. GND to the 7th pin of the gate IC
3. Depending upon the truth table, if the LED glow it represent 1 and else it represents
0
4. Verify the truth table as given for half subtractor
5. Repeat the procedure steps for full subtractor circuits
RESULT:
The half and full subtractor circuits are constructed and truth table was verified
16
EXP. NO: 4
DATE:
AIM:
BINARY TO GRAY - CODE CONVERTER
To Construct and Verify the Truth Table of Binary to Gray Code Converter.
APPARATUS REQUIRED:
S.NO
1
2
3
Particular Name
IC 7486
Connecting Wires
SPECIFICATION
QUANTITY
---QUAD
QUAD
1
3
1
THEORY:
The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion
circuit must be inserted between the two systems if each uses different codes for
same information. Thus, code converter is a circuit that makes the two systems
compatible even though each uses different binary code.
The bit combination assigned to binary code to gray code. Since each code
uses four bits to represent a decimal digit. There are four inputs and four outputs.
Gray code is a non-weighted code.
LOGIC DIAGRAM:
17
K-Map for G3:
G3 = B3
K-Map for G2:
18
K-Map for G1:
K-Map for G0:
TRUTH TABLE:
19
INPUTS(Binary Code)
B3
B2
B1
B0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
OUTPUTS (Gray Code)

G3
G2
G1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
1
0
1
1
0
1
0
0
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
0
1
1
0
1
1
0
0
1
0
0
G0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
20
PROCEDURE:
2. Inputs are given to the circuit making high 1 i.e. +5 V or + Vcc supply to the 14th pin
and for low 0 i.e. GND to the 7th pin of gate IC
3. Verify the truth table
RESULT:
The Binary to Gray code converter circuit was constructed and truth table is verified.
EXP. NO: 5
DATE:
GRAY TO BINARY - CODE CONVERTER
21
AIM:
To construct and verify the truth table of Gray to Binary code converter
S.N
O
1
2
3
Particular Name
IC 7486
Connecting Wires
SPECIFICATION
---QUAD
QUAD
QUANTITY
1
3
1
APPARATUS REQUIRED:
PROCEDURE:
3. Verify the truth table as given for the entire code converter
22
LOGIC DIAGRAM:
TRUTH TABLE:
G3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
INPUTS(Gray Code)
G2 G1
G0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OUTPUTS(Binary Code)
B3
B2
B1
B0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
23
RESULT:
The code converter circuit was constructed and truth table is verified.
24
EXP. NO: 6
DATE:
AIM:
BCD TO EXCESS 3 - CODE CONVERTER
To construct and verify the truth table of BCD to Excess-3 code converter circuit.
APPARATUS REQUIRED:
S.NO
Particular Name
SPECIFICATION
QUANTITY
1.
2.
IC7486
QUAD
3.
IC 7404
QUAD
4.
IC 7408
QUAD
5.
IC 7432
QUAD
6.
Connecting Wires
PROCEDURE:
3. Verify the truth table as given for the entire code converter
25
CIRCUIT DIAGRAM:
TRUTH TABLE:
INPUTS(BCD Code)
OUTPUTS(Binary Code)
B3
B2
B1
B0
E3
E2
E1
E0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
1
1
1
0
0
1
0
1
0
0
0
1
1
0
0
0
1
0
1
1
0
1
0
1
0
0
0
1
1
1
1
0
1
1
1
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
1
0
1
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
26
RESULT:
27
The code converter circuit was constructed and truth table is verified
EXPT. NO. :7
DATE:
DESIGN OF 4-BIT ADDER AND SUBTRACTOR
AIM:
To design and implement 4-bit adder and subtractor using IC 7483.
APPARATUS REQUIRED:
Sl.No.
COMPONENT
SPECIFICATION
QTY.
1.
IC
IC 7483
2.
EX-OR GATE
IC 7486
3.
NOT GATE
IC 7404
3.
IC TRAINER KIT
4.
PATCH CORDS
40
THEORY:
4 BIT BINARY ADDERS:
A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output carry from
each full adder connected to the input carry of next full adder in chain.
The augends bits of A and the addend bits of B are designated by subscript numbers
from right to left, with subscript 0 denoting the least significant bits. The carries are connected in
chain through the full adder. The input carry to the adder is C 0 and it ripples through the full
adder to the output carry C4.
28
4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed between each
data input B and the corresponding input of full adder. The input carry C0 must be equal to 1
when performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the circuit is adder
circuit. When M=1, it becomes subtractor.
PIN DIAGRAM FOR IC 7483:
29
TRUTH TABLE:
4-BIT BINARY ADDER
30
Input Data A
Input Data B
Addition
Subtraction
A4 A3 A2 A1 B4 B3 B2 B1
S4 S3 S2 S1
D4 D3 D2 D1
31
4-BIT BINARY SUBTRACTOR
32
4-BIT BINARY ADDER/SUBTRACTOR

33
PROCEDURE:
34
(i)
Connections were given as per circuit diagram.
(ii)
Logical inputs were given as per truth table
(iii)
Observe the logical output and verify with the truth tables.
RESULT:
The 4-bit adder and subtractor using IC 7483 were constructed and its truth
table was verified.
EXP. NO: 8
MULTIPLEXER
35
DATE:
AIM:
To construct and verify the truth table of multiplexer and circuits.
APPARATUS REQUIRED:
S.N
O
1
Particular Name
SPECIFICATION
QUANTITY
----
IC7404
----
IC7432
IC7411
Connecting Wires
MULTIPLEXER
CIRCUIT DIAGRAM:
36
TRUTH TABLE:
Inputs
Control input
Outputs (D0,D1,D2,D3)
D0
D1
D2
D3
D0
D1
D2
D3
PROCEDURE:
37

2. Inputs are given to the circuit making high 1, i.e. +5 V or + Vcc supply to the 16th pin
and for low 0 i.e. GND to the 8th pin of the gate IC
3. Verify the truth table for the multiplexer as given
RESULT:
The Multiplexer circuit is constructed and truth table is verified.
EXP. NO: 9
DATE:
DEMULTIPLEXER
38
AIM:
To construct and verify the truth table of demultiplexer circuits
APPARATUS REQUIRED:
S.NO
Particular Name
1
2
IC7404, IC7432 IC7411
3
Connecting Wires
THEORY: DEMULTIPLEXER:
SPECIFICATION
-------
QUANTITY
1
1 each
2
The function of Demultiplexer is in contrast to multiplexer function. It takes

information from one line and distributes it to a given number of output lines. For
this reason, the demultiplexer is also known as a data distributor. Decoder can also
be used as demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND
gates. The data select lines enable only one gate at a time and the data on the data
input line will pass through the selected gate to the associated data output line.
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:
FUNCTION TABLE:
S1
0
0
S0
0
1
INPUTS Y
D0 D0 S1 S0
D1 D1 S1 S0
39
1
1
0
1
D2 D2 S1 S0
D3 D3 S1 S0
Y = D0 S1 S0 + D1 S1 S0 + D2 S1 S0 + D3 S1 S0
DE MULTIPLEXER LOGIC DIAGRAM
40
41
TRUTH TABLE:
INPUTS
CONTROL INPUTS
D
1
1
1
1
0
X
0
0
1
1
X
Y
0
1
0
1
X
OUTPUTS
D0
1
0
0
0
0
D1
0
1
0
0
0
D2
0
0
1
0
0
D3
0
0
0
1
0
TRUTH TABLE:
S1
0
0
0
0
1
1
1
1
INPUT
S0
0
0
1
1
0
0
1
1
I/P
0
1
0
1
0
1
0
1
D0
0
1
0
0
0
0
0
0
OUTPUT
D1
D2
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
D3
0
0
0
0
0
0
0
1
42
PROCEDURE:
2. Inputs are given to the circuit making high 1, i.e. +5 V or + Vcc supply to the
3. Verify the truth table for the de multiplexer as given
RESULT:
The De Multiplexer circuit is constructed and truth table is verified.
43
EXP. NO: 10
DATE:
DESIGN AND IMPLEMENTATION OF MAGNITUDE

COMPARATOR
AIM:
To design and implement
(i)
2 bit magnitude comparator using basic gates.
(ii)
8 bit magnitude comparator using IC 7485.
APPARATUS REQUIRED:
Sl.No.
1.
2.
3.
4.
5.
6.
7.
COMPONENT
AND GATE
X-OR GATE
OR GATE
NOT GATE
4-BIT MAGNITUDE
COMPARATOR
IC TRAINER KIT
PATCH CORDS
SPECIFICATION
IC 7408
IC 7486
IC 7432
IC 7404
2
1
1
1
QTY.
IC 7485
1
30
THEORY:
The comparison of two numbers is an operator that determine one number is greater than,
less than (or) equal to the other number. A magnitude comparator is a combinational circuit that
compares two numbers A and B and determine their relative magnitude. The outcome of the
comparator is specified by three binary variables that indicate whether A>B, A=B (or) A<B.
A = A3 A2 A1 A0
B = B 3 B2 B1 B0
44
The equality of the two numbers and B is displayed in a combinational circuit designated by the
symbol (A=B).
This indicates A greater than B, then inspect the relative magnitude of pairs of significant digits
starting from most significant position. A is 0 and that of B is 0.
We have A<B, the sequential comparison can be expanded as
A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01
A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0
The same circuit can be used to compare the relative magnitude of two BCD digits.
Where, A = B is expanded as,
A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)
x3
x2
x1
x0
45
2 BIT MAGNITUDE COMPARATOR
K MAP
46
47
TRUTH TABLE
INPUTS
OUTPUTS
DECIMAL
BINARY
A
A
0
0
0
0
1
1
1
1
2
2
2
2
3
B
0
1
2
3
0
1
2
3
0
1
2
3
0
A0
0
0
0
0
0
0
0
0
1
1
1
1
1
A<B
B
A1
0
0
0
0
1
1
1
1
0
0
0
0
1
B0
0
0
1
1
0
0
1
1
0
0
1
1
0
A=B
A>B
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
B1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
0
1
1
0
0
0
1
0
48
3
3
3
1
2
3
1
1
1
A1 A0 B1 B0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
A> B
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0
0
1
1
1
0
1
0
0
0
0
0
1
A=B
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
1
0
A<B
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
49
8 BIT MAGNITUDE COMPARATOR
TRUTH TABLE:
A>B
A=B
A<B
0000
0000
0000
0000
0001
0001
0000
0000
0000
0000
0001
0001
50
PROCEDURE:
2. Inputs are given to the circuit making high 1 i.e. +5 V or + Vcc supply to the 14 th pin
3. Depending upon the values of A and B, the corresponding LEDs glow which indicates
the comparator Output
51
RESULT:
Thus the comparator circuits were constructed and the truth table was verified.
EXP. NO: 11
DATE:
ENCODER
AIM :
To construct and verify the truth table of encoder circuit
APPARATUS REQUIRED:
S.N
O
1
2
3
Particular Name
IC7432
Connecting Wires
SPECIFICATION
---QUAD
QUANTITY
1
3
ENCODER:
52
An encoder is a digital circuit that perform inverse operation of a decoder. An encoder

has 2n input lines and n output lines. In encoder the output lines generates the binary code
corresponding to the input value. In octal to binary encoder it has eight inputs, one for each octal
digit and three output that generate the corresponding binary code.
In encoder it is assumed that only one input has a value of one at any given time
otherwise the circuit is meaningless. It has an ambiguila that when all inputs are zero the outputs
are zero. The zero outputs can also be generated when D0 = 1.
CIRCUIT DIAGRAM:
53
TRUTH TABLE:
Y1
1
0
0
0
0
0
0
Y2
0
1
0
0
0
0
0
Y3
0
0
1
0
0
0
0
INPUT
Y4
Y5
0
0
0
0
0
0
1
0
0
1
0
0
0
0
Y6
0
0
0
0
0
1
0
Y7
0
0
0
0
0
0
1
A
0
0
0
1
1
1
1
OUTPUT
B
0
1
1
0
0
1
1
C
1
0
1
0
1
0
1
54
55
TRUTH TABLE:
INPUTS
OUTPUTS
D1
0
D2
0
D3
0
D4
0
D5
0
D6
0
D7
0
X
0
Y
0
Z
0
56
PROCEDURE :
2.
Inputs are given to the circuit making high 1 i.e. +5 V or + Vcc supply to the 14th pin
and for low 0 i.e. GND to the 7th
3. pin of the gate IC

4. Verify the truth table as given for the encoder
RESULT:
The Encoder circuit is constructed and truth table is verified.
57
EXP. NO: 12
DATE:
DECODER
AIM:
To construct and verify the truth table of decoder circuit
APPARATUS REQUIRED:
S.NO
1
2
3
4
Particular Name
IC 7411
IC 7404
Connecting Wires
SPECIFICATION
QUANTITY
---QUAD
QUAD
1
3
1
THEORY:
DECODER:
A decoder is a multiple input multiple output logic circuit which converts

coded input into coded output where input and output codes are different. The
input code generally has fewer bits than the output code. Each input code word
produces a different output code word i.e there is one to one mapping can be
expressed in truth table. In the block diagram of decoder circuit the encoded
information is present as n input producing 2n possible outputs. 2n output values are
from 0 through out 2n 1.
PIN DIAGRAM:
58
14
13
+ Vcc
12
11
10
IC 7411
GND
TRUTH TABLE:
INPUTS
X
Y
0
0
OUTPUTS
D3
D4
D5
0
0
0
Z
0
D0
1
D1
0
D2
0
D6 D7
0
0
CIRCUIT DIAGRAM:
59
60
TRUTH TABLE:
E
1
0
0
0
0
INPUT
A
0
0
0
1
1
B
0
0
1
0
1
D0
1
0
1
1
1
OUTPUT
D1
D2
1
1
1
1
0
1
1
0
1
1
D3
1
1
1
1
0
PROCEDURE:
61

2. Inputs are given to the circuit making high 1 i.e. +5 V or + Vcc supply to the
3. Verify the truth table as given for the decoder circuit
RESULT:
The decoder circuit is constructed and truth table is verified.
EXP. NO:13
DATE:
16 BIT ODD/EVEN PARITY CHECKER/GENERATOR
AIM:
62
To design and implement 16 bit odd/even parity checker generator using IC

74180.
APPARATUS REQUIRED:
Sl. No.
1.
1.
2.
3.
COMPONENT
NOT GATE
IC TRAINER KIT
PATCH CORDS
SPECIFICATION
IC 7404
IC 74180
-
QTY.
1
2
1
30
THEORY:
A parity bit is used for detecting errors during transmission of binary

information. A parity bit is an extra bit included with a binary message to make the
number is either even or odd. The message including the parity bit is transmitted
and then checked at the receiver ends for errors.
An error is detected if the checked parity bit doesnt correspond to the one
transmitted. The circuit that generates the parity bit in the transmitter is called a
parity generator and the circuit that checks the parity in the receiver is called a
parity checker.
In even parity, the added parity bit will make the total number is even
amount. In odd parity, the added parity bit will make the total number is odd
amount. The parity checker circuit checks for possible errors in the transmission.
If the information is passed in even parity, then the bits required must have
an even number of 1s. An error occur during transmission, if the received bits
have an odd number of 1s indicating that one bit has changed in value during
transmission.
63
FUNCTION TABLE:
INPUTS
Number of High Data
Inputs (I0 I7)
EVEN
ODD
EVEN
ODD
X
X
PE
PO
1
1
0
0
1
0
0
0
1
1
1
0
OUTPUTS
E
O
1
0
0
1
0
1
0
1
1
0
0
1
LOGIC DIAGRAM:
16 BIT ODD/EVEN PARITY CHECKER
64
TRUTH TABLE:
I7 I6 I5 I4 I3 I2 I1 I0
I7I6I5I4I3I211 I0
Active
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
0 0 0 0 0 1 1 0
0 0 0 0 0 1 1 0
0 0 0 0 0 1 1 0
0 0 0 0 0 1 1 0
16 BIT ODD/EVEN PARITY GENERATORS
65
TRUTH TABLE:
I7 I6 I5 I4 I3 I2 I1 I0
I7 I6 I5 I4 I3 I2 I1 I0 Active
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0
PROCEDURE:
66
(i)
Connections are given as per circuit diagram.
(ii)
Logical inputs are given as per circuit diagram.
(iii)
Observe the output and verify the truth table.
RESULT:
The 16 bit odd/even parity checker generator using IC 74180 was constructed and
its truth table was verified
EXP. NO:14
DATE:
DESIGN AND IMPLEMENTATION OF SHIFT

REGISTER
AIM:
67
To design and implement

(i)
(ii)
(iii)
(iv)
Serial in serial out

Serial in parallel out
Parallel in serial out
Parallel in parallel out
APPARATUS REQUIRED:
Sl.No.
1.
2.
3.
4.
COMPONENT
D FLIP FLOP
OR GATE
IC TRAINER KIT
PATCH CORDS
SPECIFICATION
IC 7474
IC 7432
-
QTY.
2
1
1
35
THEORY:
A register is capable of shifting its binary information in one or both directions is known
as shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with
output of one flip flop connected to input of next flip flop. All flip flops receive common clock
pulses which causes the shift in the output of the flip flop. The simplest possible shift register is
one that uses only flip flop. The output of a given flip flop is connected to the input of next flip
flop of the register. Each clock pulse shifts the content of register one bit position to right.
PIN DIAGRAM:
68
LOGIC DIAGRAM:
SERIAL IN SERIAL OUT:
TRUTH TABLE:
69
CLK
Serial in
Serial out
LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:
TRUTH TABLE:
CLK
1
2
3
4
DATA
1
0
0
1
QA
1
0
0
1
OUTPUT
QB
QC
0
0
1
0
0
1
0
0
QD
0
0
1
1
LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:
70
TRUTH TABLE:
CLK
0
1
2
3
Q3
1
0
0
0
Q2
0
0
0
0
Q1
0
0
0
0
Q0
1
0
0
0
O/P
1
0
0
1
LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:
71
TRUTH TABLE:
CLK
1
2
DA
1
1
DATA INPUT
DB
DC
0
0
0
1
DD
QA
1
0
1
1
OUTPUT
QB
QC
0
0
0
1
QD
1
0
PROCEDURE:
(i)
Connections are given as per circuit diagram.
(ii)
Logical inputs are given as per circuit diagram.
(iii)
Observe the output and verify the truth table.

72
RESULT:
The shift register circuits were constructed and its truth table was verified.
EXP. NO: 15
DATE:
3 BIT ODD/EVEN PARITY GENERATOR
AIM:
To construct and verify the truth table of parity generator circuits
73
APPARATUS REQUIRED:
S.NO
1
2
3
Particular Name
IC 7486, IC 7404
Connecting Wires
SPECIFICATION
---QUAD
QUANTITY
1
1 each
PROCEDURE:
2. Inputs are given to the circuit making high 1 i.e. +5 V or + Vcc supply to the 14 th pin
3. Depending upon the truth table, if the LED glow it represents 1 and else it represents 0
4. Verify the truth table as given
74
TRUTH TABLE
X
0
0
0
0
1
1
1
1
3- bit Message
Y
Z
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Parity bit
Generated (P)
1
0
0
1
0
1
1
0
75
RESULT:
The 3 bit even parity generator circuit is constructed and its truth
table was verified.
76

Digital Electronics - Lab Manual'121

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EXP.

STUDY OF LOGIC GATES

NAND GATE 2 I/P

NAND GATE 3 I/P

2-INPUT NAND GATE:

3-INPUT NAND GATE :

a. Give connections as per the circuit diagram

DESIGN AND IMPLEMENTATION HALF ADDER AND

K-Map for SUM:

K-Map for CARRY:

K-Map for SUM:

SUM = ABC + ABC + ABC + ABC

DESIGN AND IMPLEMENTATION OF SUBTRACTORS

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

BINARY TO GRAY - CODE CONVERTER

K-Map for G3:

K-Map for G1:

K-Map for G0:

OUTPUTS (Gray Code)

GRAY TO BINARY - CODE CONVERTER

BCD TO EXCESS 3 - CODE CONVERTER

Digital IC trainer kit

Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32

DESIGN OF 4-BIT ADDER AND SUBTRACTOR

4 BIT BINARY SUBTRACTOR:

PIN DIAGRAM FOR IC 7483:

4-BIT BINARY SUBTRACTOR

4-BIT BINARY ADDER/SUBTRACTOR

Connections were given as per circuit diagram.

Logical inputs were given as per truth table

Digital IC trainer kit

1. Give connections as per the circuit diagram

The function of Demultiplexer is in contrast to multiplexer function. It takes

Vels University/ Dept of ECE/ Digital Electronics Lab/11 PBEC32

DESIGN AND IMPLEMENTATION OF MAGNITUDE

2 bit magnitude comparator using basic gates.

8 bit magnitude comparator using IC 7485.

2 BIT MAGNITUDE COMPARATOR

8 BIT MAGNITUDE COMPARATOR

An encoder is a digital circuit that perform inverse operation of a decoder. An encoder

3. pin of the gate IC

A decoder is a multiple input multiple output logic circuit which converts

1. Give connections as per the circuit diagram

16 BIT ODD/EVEN PARITY CHECKER/GENERATOR

To design and implement 16 bit odd/even parity checker generator using IC

A parity bit is used for detecting errors during transmission of binary

16 BIT ODD/EVEN PARITY GENERATORS

Connections are given as per circuit diagram.

Logical inputs are given as per circuit diagram.

Observe the output and verify the truth table.

DESIGN AND IMPLEMENTATION OF SHIFT

To design and implement

Serial in serial out

Connections are given as per circuit diagram.

Logical inputs are given as per circuit diagram.

Observe the output and verify the truth table.

3 BIT ODD/EVEN PARITY GENERATOR

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