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Benefits
Features
High precision
Easy to use
AS5048A/AS5048B 1
Benefits
Features
3.3V / 5V compliant
Package: 14-pin TSSOP (5 x 6.4mm)
Applications
The applications of AS5048 include:
Robotic joint position detection
Industrial motor position control
Medical robots and fitness equipment
Block Diagram
The functional blocks of this device for reference are
shown below:
Figure 2:
AS5048A Block Diagram
VDD5V
SCK
VDD3V
Register
Setting
LDO
MISO
SPI
MOSI
OTP
CSn
AFE
14-bit A/D
14-bit A/D
ATAN
(CORDIC)
PWM
PWM
AS5048A
AGC
GND
AS5048A/AS5048B 2
General Description
Figure 3:
AS5048B Block Diagram
VDD5V
SCL
VDD3V
Register
Setting
LDO
SDA
I2C
A1
OTP
A2
AFE
14-bit A/D
A/D
14-bit
ATAN
(CORDIC)
PWM
PWM
AS5048B
AGC
GND
AS5048A/AS5048B 3
Pin Assignment
Pin Assignment
Figure 4:
TSSOP14 Pin Configuration
14
PWM
SDA
14
PWM
CLK
13
GND
SCL
13
GND
MISO
12
VDD3V
A2
12
VDD3V
MOSI
11
VDD5V
A1
11
VDD5V
TEST
10
TEST
TEST
10
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST
AS5048B
AS5048A
CSn
Figure 5:
TSSOP14 Pin Description for AS5048A
Pin
AS5048A
Pin Type
CSn
CLK
MISO
MOSI
TEST
TEST
TEST
TEST
TEST
10
TEST
11
VDD5V
12
VDD3V
13
GND
14
PWM
Analog I/O
AS5048A/AS5048B 4
Description
SPI chip select - active low
SPI clock input
Supply pad
Pi n A s s i g n m e n t
Figure 6:
TSSOP14 Pin Description for AS5048B
Pin
AS5048B
Type
SDA
SCL
A2
A1
TEST
TEST
TEST
TEST
TEST
10
TEST
11
VDD5V
12
VDD3V
13
GND
14
PWM
Description
Data pin IC interface
IC clock input
Analog I/O
Supply pad
AS5048A/AS5048B 5
Figure 7:
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Note
Electrical Parameters
VDD5V
-0.3
VDD3V
-0.3
-0.3
0.3
VDD+0.3
100
mA
Norm: Jedec 78
kV
GND
VIN
ISCR
-100
Electroststic Discharge
ESD
Electrostatic discharge
2
Power Dissipation
PT
150
mW
Storage temperature
TBODY
Humidity non-condensing
MSL
AS5048A/AS5048B 6
-55
150
5
3
260
85
Electrical Characteristics
Electrical Characteristics
Operating Conditions
Figure 8:
Operating Conditions
Symbol
VDD5V
Parameter
Positive supply voltage
VDD3V
VDDCORE
TAMB
Ambient temperature
ISUP
Supply Current
Min
Max
Unit
Note
4.5
5.5
3.6
3.6
-40
150
15
mA
Symbol
Parameter
Min
Max
Unit
CMOS Digital Input with Schmitt Trigger: CSn, CLK, MOSI and SCL, A1, A2
VIH
VIL
lLEAK
0.7 * VDDCORE
V
0.3 * VDDCORE
VOL
CL
IOUT
VDDCORE - 0.5
V
GND+0.4
Capacitive load
50
pF
Output current
mA
AS5048A/AS5048B 7
Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Bz
30
50
70
mT
fsample
10.2
11.25
12.4
kHz
RES
Output Resolution
14
Noise
tprop
90.7
fPWM
PWM frequency
0.907
INLOPT
@25C
INL
OPT+TEMP
INL
DIS+TEMP
tstartup
0.06
Deg
100
110.2
1.102
kHz
Non-linearity, optimum
placement of the magnet
0.8
Deg
Non-linearity optimum
placement of the magnet
over the full Temperature
Range
Deg
1.2
Deg
10
ms
Non-linearity @
displacement of magnet
and temperature -40C to
150C
Startup Time
AS5048A/AS5048B 8
Bit
Fu n c t i o n a l D e s c r i p t i o n
Functional Description
AS5048A/AS5048B 9
Operation
Operation
Supply Voltage Configuration
The AS5048 operates at 5V 10%, using an internal
Low-Dropout (LDO) voltage regulator. In addition a 3.3V
operation is possible. The VDD3V output is intended for
internal use only. It must not be loaded with an external load.
Figure 11:
Connections for 5V and 3.3V Supply Voltages
3.3V Operation
5V Operation
10F
VDD3V
VDD3V
100nF
10F
100nF
LDO
LDO
VDD5V
VDD5V
Internal
VDD3.3V
Internal
VDD3.3V
4.5 - 5.5V
3.0 - 3.6V
GND
GND
SPI Interface
The 16 bit SPI Interface enables read / write access to the
register blocks and is compatible to a standard micro controller
interface. The SPI is active as soon as CSn is pulled low. The
AS5048A then reads the digital value on the MOSI (master out
slave in) input with every falling edge of CLK and writes on its
MISO (master in slave out) output with the rising edge. After 16
clock cycles CSn has to be set back to a high status in order to
reset some parts of the interface core.
AS5048A/AS5048B 10
Operation
Figure 12:
SPI Connection AS5048A with C
CLK
SPI_CLK
CSn
SPI_SSN
MOSI
MOSI
Interface Core
RXSR
Master Device
RXSPI
TXSPI
(Tester)
TXSR
MISO
MISO
AS5048A
TCOM
MSB
MOSI
MISO
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
Command 1
Command 2
Command 3
Command N
NOP
Response 1
Response 2
Response N-1
LSB
Transmission 1
MSB
LSB
Transmission 2
MSB
LSB
Transmission 3
MSB
LSB
Transmission N
AS5048A/AS5048B 11
Operation
SPI Timing
Figure 14:
SPI Timing Diagram
tCSn
CSn
(Input)
tL
tclk
tclkL
tclkH
tH
CLK
(Input)
tMISO
tOZ
MISO
(Output)
data[15]
data[14]
data[0]
tOZ
tMOSI
MOSI
(Input)
data[15]
data[14]
data[0]
Figure 15:
SPI Timing Characteristics
Parameter
tL
Description
Min
Max
Unit
350
ns
TCLK
100
ns
tCLKL
50
ns
tCLKH
50
ns
Time between last falling edge of CLK and rising edge of CSn
50
ns
TCSnH
350
ns
tMOSI
20
ns
tMISO
tH
AS5048A/AS5048B 12
20
ns
Operation
4 wire mode
MOSI
MOSI
MISO
MISO
SCK
SCK
SS/
SS/
MOSI
AS5048A
0xFFFF
Read angle 1
MISO
0xFFFF
Read angle 2
0xFFFF
Read angle 3
0xFFFF
Read angle 4
Angle 1
Angle 2
Angle 3
SS/
MISO
MOSI
MISO
MISO
SCK
SCK
SS/
SS/
AS5048A
Angle 1
Angle 2
Angle 3
SS/
Single Slave Mode: This figure shows the SPI connection to the host C using Single Slave Mode.
MOSI
MOSI
MISO
MISO
SCK
SCK
SS1/
SS/
MOSI
AS5048A
1
MISO
SW Reset
0xFFFF
Read angle 1
0xFFFF
Read angle 2
Angle 1
0xFFFF
Read angle 3
Angle 2
Angle 3
SS2/
SS1/
SS3/
MOSI
MISO
SCK
SS2/
SS3/
AS5048A
2
SS/
MOSI
MISO
SCK
AS5048A
3
SS/
Multiple Slave, n+3 Wire (Separate ChipSelect): This figure shows the SPI connection to the host C using 3
Wire mode.
ams Datasheet: 2014-Jun-05 [v1-06]
AS5048A/AS5048B 13
Operation
MOSI
MOSI
MOSI
MISO
MISO
SCK
SCK
SS/
SS/
AS5048A
1
SW Reset
SW Reset
SW Reset
0xFFFF
Read Angle 3
0xFFFF
Read angle 2
0xFFFF
Read Angle 1
MISO
SS/
MOSI
MISO
SCK
MOSI
AS5048A
2
MISO
SS/
0xFFFF
Read angle 3
0xFFFF
Read angle 2
0xFFFF
Read angle 1
Angle 3
Angle 2
Angle 1
SS/
MOSI
MISO
SCK
AS5048A
3
SS/
Daisy Chain, 4 Wire: This figure shows the SPI connection to the host C using Daisy Chain, 4 wire mode.
Command Package
Bit
MSB
14
PAR
RWn
13
12
11
10
LSB
Address<13:0>
Bit Definition & Description
PAR
RWn
Address
AS5048A/AS5048B 14
Operation
Read Package
Bit
MSB
14
PAR
EF
13
12
11
10
LSB
Data<13:0>
Bit Definition & Description
PAR
EF
Data
Data Package
Bit
MSB
14
PAR
13
12
11
10
LSB
Data <13:0>
Bit Definition & Description
PAR
R
Data
AS5048A/AS5048B 15
Register Description
Register Description
Figure 22:
SPI Register Map
Address
hex
Name
Access
Type
Bit
Symbol
Default
Description
NOP
NOP
Not used
n.a.
No operation dummy
information
0
13
:
x0001
Clear Error
Flag
R
2
Parity Error
Command Invalid
Framing Error
13
:
Not used
7
6
Verify
5
x0003
Programming
Control
R/W
Not used
4
3
Burn
Programming control
register.
Programming must be
enabled before burning
the fuse(s). After
programming is a
verification mandatory.
See programming
procedure.
Reserved
1
0
AS5048A/AS5048B 16
Programming
Enable
Register Description
Address
hex
Name
Access
Type
Bit
Symbol
Default
Description
OTP Register
Zero Position
Hi
R/W
+
Program
Not used
8
7
Not used
13
:
x0017
OTP Register
Zero Position
Low 6 LSBs
R/W
+
Program
6
5
Readout Registers
13
Not used
n.a.
11
Comp High
10
Comp Low
COF
OCF
AGC value<7>
AGC value<0>
13
Magnitude<13>
Magnitude<0>
13
Angle <13>
Angle<0>
12
Diagnostics flags
x3FFD
x3FFE
x3FFF
Diagnostics +
Automatic
Gain Control
(AGC)
Magnitude
Angle
Magnitude information
after ATAN calculation
AS5048A/AS5048B 17
LSB
MOSI
MISO
MSB
LSB
READ
Next command
Response -1
Response on
READ command
MSB
LSB
MSB
Transmission N
LSB
Transmission N+1
WRITE Command
A single WRITE command takes two transmission cycles. With a
NOP command after the WRITE command you can verify the
sent data with three transmission cycles because the data will
be send back during the following command.
Figure 24:
WRITE Command
TCOM
MSB
LSB
MOSI
MISO
MSB
LSB
MSB
LSB
WRITE
command
DATA
NOP
Response-1
Old register
content
New register
content
MSB
LSB
Transmission N
AS5048A/AS5048B 18
MSB
LSB
Transmission N+1
MSB
LSB
Transmission N+2
TCOM
MSB
LSB
MSB
LSB
MOSI
CLEAR ERROR
FLAG
Next command
Next command
MISO
Response-1
EF
Error register
Content + EF
New register
EF cleared
MSB
LSB
MSB
Transmission N
MSB
LSB
LSB
Transmission N+2
Transmission N+1
MSB
14
13
12
11
10
LSB
PAR
AS5048A/AS5048B 19
NOP Command
The NOP command represents a dummy write to the AS5048.
Figure 27:
NOP Command
TCOM
MSB
LSB
MOSI
MISO
MSB
LSB
MSB
LSB
NOP
NOP
Next command
Response-1
0x0000
0x0000
MSB
LSB
MSB
Transmission N
LSB
MSB
Transmission N+1
LSB
Transmission N+2
NOP Command
Bit
MSB
14
13
12
11
10
LSB
AS5048A/AS5048B 20
IC Inter face
IC Interface
Supported modes:
Random/Sequential Read
Byte/Page Write
Standard: 0 to 100kHz clock frequency (slave mode)
Fast Mode: 0 to 400kHz clock frequency (slave mode)
High Speed: 0 to 3.4MHz clock frequency (slave mode)
The SDA signal is bidirectional and is used to read and write the
serial data. The SCL signal is the clock generated by the host
MCU, to synchronize the SDA data in read and write mode. The
maximum IC clock frequency is 3.4MHz, data are triggered on
the rising edge of SCL.
IC Electrical Specification
Figure 29:
IC Electrical Specification
FS-mode+
Symbol
Parameter
Condition
HS-mode
CB=100pF
HS-mode
CB=400pF
Min
Max
Min
Max
Min
Max
-0.5
0.3VDDC
-0.5
0.3VDDC
Unit
VIL
LOW-Level Input
Voltage
-0.5
0.3VDDC
VIH
HIGH-Level Input
Voltage
0.7VDD
VDDCORE
+ 0.5
0.7VDD
CORE
VDDCORE
+ 0.5
0.7VDD
CORE
CORE
VDDCORE
+ 0.5
Vhys
Hysteresis of Schmitt
Trigger Inputs
VDDCORE< 2V
0.1VDD
--
0.1VDD
--
0.1VDD
--
VOL
LOW-Level Output
Voltage (open-drain
or open-collector) at
3mA Sink Current
VDDCORE< 2V
--
0.2VDDC
--
0.2VDDC
--
0.2VDDC
IOL
LOW-Level Output
Current
VOL = 0.4V
20
--
--
--
--
mA
ICS
Pull-up current of
SCLH current source
--
--
12
12
mA
tSP
--
50 (1)
--
10
--
10
ns
CORE
ORE
ORE
CORE
ORE
ORE
CORE
ORE
ORE
AS5048A/AS5048B 21
IC Inter face
HS-mode
CB=100pF
FS-mode+
Symbol
Parameter
Condition
Input
Voltage
between
HS-mode
CB=400pF
Unit
Min
Max
Min
Max
Min
Max
-10
+10 (2)
--
10
--
10
Ii
CB
--
550
--
100
--
400
pF
CI/O
I/O Capacitance
(SDA,SCL)
--
10
--
10
--
10
pF
IC Timing
Figure 30:
IC Timing
FS-mode+
Symbol
Parameter
Condition
HS-mode
CB=100pF
HS-mode
CB=400pF (5)
Unit
Min
Max
Min
Max
Min
Max
--
1000
--
3400
--
1700
kHz
fSCLK
SCL clock
Frequency
tBUF
500
--
500
--
500
--
ns
tHD;STA
Hold Time;
(Repeated) START
Condition (1)
260
--
160
--
160
--
ns
tLOW
500
--
160
--
320
--
ns
tHIGH
260
--
60
--
120
--
ns
tSU;STA
260
--
160
--
160
--
ns
tHD;DAT
450
70
150
ns
tSU;DAT
50
--
10
--
10
--
ns
20+0.1Cb
120
--
--
--
--
ns
tR
AS5048A/AS5048B 22
IC Inter face
FS-mode+
Symbol
tF
Parameter
Condition
HS-mode
CB=100pF
HS-mode
CB=400pF (5)
Unit
Min
Max
Min
Max
Min
Max
20+0.1Cb
120 (4)
--
--
--
--
ns
trCL
Ext. pull-up
source of
3mA
--
--
10
40
20
80
ns
trCL1
--
--
10
80
20
160
ns
tfCL
Ext. pull-up
source of
3mA
--
--
10
40
20
80
ns
trDA
--
--
10
80
20
160
ns
tfDA
--
--
10
80
20
160
ns
tSU;STO
260
--
160
--
160
--
ns
VnL
Noise margin at
LOW level
0.1VDDp
--
0.1VDDp
--
0.1VDDp
--
VnH
Noise margin at
HIGH level
0.2VDDp
--
0.2VDDp
--
0.2VDDp
--
AS5048A/AS5048B 23
IC Inter face
Register Table
The following registers / functions are accessible over the serial
IC interface.
Figure 31:
Register Map IC
Address
hex
Name
Access
Type
Bit
Symbol
Default
Description
Programming control
register. Programming
must be enabled before
burning the fuse(s). After
programming is an
verification mandatory.
See programming
procedure.
Control OTP
7
Not used
Verify
5
Not used
4
x03
Programming
Control
R/W
Burn
2
Reserved
1
0
Programming
Enable
Not used
n.a.
IC address<4>
internally
inverted
IC address<0>
Not used
n.a.
5
x15
x16
IC slave
address
OTP Register
Zero Position
Hi
R/W
R/W
+
Program
7
6
x17
OTP Register
Zero Position
Low 6 LSBs
AS5048A/AS5048B 24
R/W
+
Program
IC Inter face
Address
hex
Name
Access
Type
Bit
Symbol
Default
Description
Readout Registers
xFA
Automatic
Gain
Control
AGC value<7>
AGC value<0>
Not used
n.a.
Comp High
Comp Low
COF
OCF
Magnitude<13>
Magnitude<6>
Not used
n.a.
Magnitude<5>
Magnitude<0>
Angle<13>
Angle<6>
Not used
n.a.
Angle<5>
Angle<0>
7
:
4
xFB
Diagnostics
xFC
7
Magnitude
6
xFD
xFE
7
Angle
6
xFF
Diagnostic flags
Magnitude information
afer ATAN calculation
AS5048A/AS5048B 25
IC Inter face
IC Slave address
Stop
Slave Address
A A
2 1
X X X X X X X X
Slave Address
Register Address
X X X X X X X X
Data Byte (n)
LSB
Start
1 0 0 0 0
ACK
random write
X X X X X X X X
HW
Pins
R/W
ACK
OTP cotent
(Default)
A A
2 1
LSB
Register Address
LSB
Slave Address
1 0 0 0 0
X X X X X X X X
R/W
ACK
A A
2 1
ACK
Stop
Start
1 0 0 0 0
HW
Pins
ACK
Start
random read
HW
Pins
R/W
ACK
OTP cotent
(Default)
ACK
Figure 32:
Slave Address Construction
AS5048A/AS5048B 26
PWM Interface
PWM = high
Error_n:
4 clocks
PWM = not(system_error)
Data:
4095 clocks
Exit:
8 clocks
PWM = low
In case of an error the data section is set to zero.
Figure 33:
PWM Format
Init
Error_n
Data
4095 clocks
Zero degree
16 clocks
Exit
8 clocks
Figure 34:
PWM Period and resolution
Parameter
Symbol
Value
Unit
PWM Frequency
F_PWM
KHz
T_PWM
4119
bit
AS5048A/AS5048B 27
Application Information
Application Information
Programming of the AS5048
Programming of the Zero Position: The absolute angle
position can be permanent programmed over the interface.
This could be useful for random placement of the magnet on
the rotation axis. A readout at the mechanical zero position can
be performed and written back into the IC. With permanent
programming the position is non-reversible stored in the IC.
This programming can be performed only once.
To simplify the calculation of the zero position it is only needed
to write the value in the IC which was read out before from the
angle register.
Programming Sequence with Verification: To program the
zero position is needed to perform following sequence:
1. Write 0 into OTP zero position register to clear
2. Read angle information
3. Write previous read angle position into OTP zero
position register
Now the zero position is set.
If you want to burn it to the OTP register send:
4. Set the Programming Enable bit in the OTP control
register
5. Set the Burn bit to start the automatic programming
procedure
6. Read angle information (equals to 0)
7. Set the Verify bit to load the OTP data again into the
internal registers
8. Read angle information (equals to 0)
The programming can either be performed in 5V operation
using the internal LDO, or in 3V operation but using a minimum
supply voltage of 3.3V. In case of 3V operation, also a 10F
capacitor is required on the VDD3 pin.
Programming the IC Slave address: For informations of
programming the IC Slave address please refer to our
application note covering this topic.
AS5048A/AS5048B 28
Application Information
AS5048A/AS5048B 29
Application Information
S
Magnet axis
R1
Magnet axis
Vertical field
component
R1 concentric circle;
radius 1.1mm
Vertical field
component
Bv
(3070mT)
AS5048A/AS5048B 30
360
Application Information
3.2 mm
2.5 mm
Defined
center
Rd
2.5 mm
Magnet Placement
The magnets center axis should be aligned within a
displacement radius R d of 0.25 mm (larger magnets allow more
displacement e.g. 0.5 mm) from the defined center of the IC.
The magnet may be placed below or above the device. The
distance should be chosen such that the magnetic field on the
die surface is within the specified limits The typical distance z
between the magnet and the package surface is 0.5mm to
2.5mm, provided the use of the recommended magnet material
and dimensions (6mm x 3mm). Larger distances are possible, as
long as the required magnetic field strength stays within the
defined limits.
However, a magnetic field outside the specified range may still
produce usable results, but the out-of-range condition will be
indicated by indication flags.
Figure 37:
Vertical Placement of the Magnet
N
Package surface
Die surface
0.22990.100
0.23410.100
0.77010.150
AS5048A/AS5048B 31
Figure 38:
Package Markings for AS5048A & AS5048B
Figure 39:
Package Code YYWWMZZ
YY
Last two digits of the year
AS5048A/AS5048B 32
WW
Manufacturing week
M
Plant identifier
ZZ
Letters for free traceability
Pa c k a g e D r a w i n g s & M a r k i n g s
Figure 40:
14-Lead Thin Shrink Small Outline Package TSSOP-14
Symbol
Min
Nom
Max
Symbol
Min
Nom
Max
1.20
0.09
A1
0.05
0.15
R1
0.09
A2
0.80
1.00
1.05
0.20
0.19
0.30
0.09
0.20
12 REF
4.90
5.00
5.10
12 REF
6.40 BSC
aaa
0.10
E1
4.30
4.40
4.50
bbb
0.10
0.65 BSC
ccc
0.05
0.45
0.60
0.75
ddd
0.20
L1
1.00 REF
14
AS5048A/AS5048B 33
Figure 41:
Ordering Information
Ordering Code
Description
Delivery Form
Package
AS5048A-HTSP
TSSOP 14
AS5048B-HTSP
TSSOP 14
AS5048A/AS5048B 34
AS5048A/AS5048B 35
AS5048A/AS5048B 36
Document Status
Document Status
Document Status
Product Preview
Preliminary Datasheet
Datasheet
Datasheet (discontinued)
Product Status
Definition
Pre-Development
Pre-Production
Production
Discontinued
AS5048A/AS5048B 37
Revision Information
Revision Information
Page(1)
24
AS5048A/AS5048B 38
Content Guide
Content Guide
1
1
2
2
General Description
Key Benefits & Features
Applications
Block Diagram
4
6
Pin Assignment
Absolute Maximum Ratings
7
7
7
8
Electrical Characteristics
Operating Conditions
DC/AC Characteristics for Digital Inputs and Outputs
Electrical System Specifications
Functional Description
10
10
10
10
12
13
13
13
14
14
15
15
Operation
Supply Voltage Configuration
SPI Interface
SPI Interface Signals (4-Wire Mode, Wire_mode = 1)
SPI Timing
SPI Connection to the Host C
Single Slave Mode
3 Wire Mode (read only)
Daisy Chain, 4 Wire
SPI Communication Command Package
Read Package (Value Read from AS5048A)
Write Data Package (Value Written to AS5048A)
16
Register Description
18
18
18
19
20
21
21
22
24
26
IC Interface
IC Electrical Specification
IC Timing
Register Table
IC Slave address
27
PWM Interface
AS5048A/AS5048B 39
Content Guide
AS5048A/AS5048B 40
28
28
29
30
31
31
Application Information
Programming of the AS5048
Diagnostic Functions of the AS5048
Choosing the Proper Magnet
Physical Placement of the Magnet
Magnet Placement
32
34
35
36
37
38