1

Name - Ajai Krishna

Velayutham
SID -

010026328

San Jose State University

CMPE 200
Assignment -1
1.
a) To calculate which processor has highest performance in instructions
per second For P1 4 GHz / 2.5 CPI = 1.6 x 109 instructions per second.
For P2 3.4 GHz / 2.0 CPI = 1.7 x 109 instructions per second.
For P3 2.4 GHz / 1.2 CPI = 2 x 109 instructions per second.
It is evident from the above that P3 executes more instructions than
other processors, hence it has the highest performance.
b)
To find number and clock cycles and instructions executed by
each processor for
executing a program which has taken 10 seconds
to complete.
P1 takes 1.6 x 109 instructions per second , for 10 seconds 1.6 x
109 x 10
i.e. 16 x 109 instructions/second.
Clock cycles taken 16 x 2.5 x 109 = 40 x 109 clock cycles.
Similarly, P2 1.7 x 109 instructions/second, for 10seconds 17 x
109 instructions/second.
Clock cycles taken 17 x 2.0 x 109 = 34 x 109 clock cycles.
P3 2.0 x 109 instructions/second, for 10seconds 20 x 109
instructions/second.
Clock cycles taken 20 x 1.2 x 109 = 24 x 109 clock cycles.
c) Given execution time is reduced by 30% (i.e. 0.7 x execution time).
And this leads to 20% increase in CPI (i.e. 1.2 x CPI).
Execution time is determined by

Execution time = CPI * Clock cycles * Number of Instructions

1
2
Keeping the number of instructions constant as per the problem
scenario
0.7 x Execution time = 1.2 x CPI * Clock cycles * number of
instructions.
To maintain the balance of the equation
New clock cycles is = 0.7 / 1.2 of old clock cycles = 0.5833 x old clock
cycles
Hence, New Clock rate = 1/
0.5833 = 1.71428 x old clock rate.
2. Code C=D+B
B=A-C
a) For Accumulator Based
Load D
Add B
Store C
Load A
Sub C
Store B
Code Size = # instructions x size of each instruction
=6*(1+3)
= 24 bytes.
Data Memory Traffic = # data addresses to memory * data address
size +
# data received from memory * data size.
= (6 * 4) + (6 * 4) = 48 bytes.
Instruction Traffic = # instruction address to memory * address size +
# instruction received from memory *
instruction size.
= (6 * 4) + (6 * 4) = 48 bytes.

2
3
b) For Stack Based
Push D
Push B
Add
Pop C
Push A
Push C
Sub
Pop B
Code Size = # instructions x size of each instruction
= 6 * ( 1 + 3 ) + 2 = 26 bytes.
Data Memory Traffic = # data addresses to memory * data address
size +
# data received from memory * data size.
= (6 * 4) + (6 * 4) = 48 bytes.
Instruction Traffic = # instruction address to memory * address size +
# instruction received from memory *
instruction size.
= (4 * 8) + [(6 * 4) +2] = 58 bytes.
c) For Memory Memory
ADD C, D, B
SUB B, A, C
Code Size = # instructions x size of each instruction
= 2 * (3 + 3 + 1) = 20 bytes.
Data Memory Traffic = # data addresses to memory * data address
size +
# data received from memory * data size.
= (6 * 4) + (6 * 4) = 48 bytes.
Instruction Traffic = # instruction address to memory * address size +

# instruction received from memory *

instruction size.
= (2 * 4) + (6 * (3 + 3+ 1)) = 28 bytes.
4
d) For Register based
Load R1,D
Load R2,B
Add R3,R1,R2
Store R3,C
Code Size = # instructions x size of each instruction
= (5 * 5) + (4 * 2) = 33 bytes.
Data Memory Traffic = # data addresses to memory * data address
size +
# data received from memory * data size.
= (5 * 4) + (5 * 4) = 40 bytes.
Instruction Traffic = # instruction address to memory * address size +
# instruction received from memory *
instruction size.
= (7 * 4) + [(5 * 5) + (4 * 2)] = 61 bytes.

*****
Ajai Krishna Velayutham
010026328