This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2015.2448518, IEEE Transactions on Industrial Electronics

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

A Low THD Class-D Audio Amplifier with

Dual-Level Dual-Phase Carrier Pulse-Width
Modulation
Shang-Hsien Yang, Yuan-Han Yang, Ke-Horng Chen, Senior Member, IEEE, Ying-Hsi Lin,
Tsung-Yen Tsai, Jian-Ru Lin, and Chao-Cheng Lee

Chen Chao-Cheng Lee

Abstractin this paper, a class-D audio amplifier which

combines the advantages of the phase shifted carrier (PSC) PWM
and the multiple level carrier (MLC) PWM is proposed with a
dual-level dual-phase carrier (DLDPC) PWM. The proposed
closed-loop amplifier includes a 2nd order integrator and a
DLDPC triangular wave generator. Two sets of 180 out-of-phase
triangular waves are used as carriers, and each set has its
respectful offset voltage level with non-overlapping amplitude. By
performing the double Fourier analysis, it can be found that the
linearity can be enhanced and the distortion can be reduced with
the proposed modulation. Experimental results shows that the
proposed fully differential DLDPC PWM class-D audio amplifier
features a total harmonic distortion (THD) lower than 0.01% with
an output voltage swing of +/ 5V.
Index TermsClass-D, dual-level dual-phase carrier, DLDPC
PWM, PSCPWM, MLCPWM, THD, IMD.

I. INTRODUCTION
UDIO amplifier design has recently been the focus of
research interest with the increasing popularity of portable
consumer electronics. High quality audio amplifiers should
exhibit high power efficiency, while maintaining satisfying
high fidelity to the human ear at the same time. Class-A, B, and
AB audio amplifiers topologies provide the best linearity;
however, due to poor power efficiency, their applications are
limited to low power ear jack amplifiers [1]. Class-D amplifiers,
on the other hand, provide high power efficiency [2] over a
wide modulation index range. Thereby, power consumption
and heat dissipation can be reduced simultaneously even with
high crest factor for audio [3] and RF applications [4] alike.
Due to the switching nature of class-D amplifiers, the output
signal will be affected by additional total harmonic distortion
(THD) components and linearity will be degraded [5]. Hence,
in order to improve the audio quality of the class-D audio
amplifiers, THD components must be minimized.

Manuscript received February 13, 2015; revised April 12, 2015; accepted
May 7, 2015.
Copyright 2015 IEEE. Personal use of this material is permitted.
However, permission to use this material for any other purposes must be
obtained from the IEEE by sending a request to pubs-permissions@ieee.org
Ke-Horng Chen is with the Department of Electrical Engineering, National
Chiao Tung University, Hsinchu, Taiwan, (phone: +886-3-5712121-54390;
fax: +886-3-5715998; e-mail: khchen@cn.nctu.edu.tw). S.-H. Yang and Y.-H.
Yang are with the Institute of Electrical and Computer Engineering, National
Chiao Tung University. Ying-Hsi Lin, Tsung-Yen Tsai, Jian-Ru Lin, and
Chao-Cheng Lee are with Realtek Semiconductor Corp., Hsinchu 300, Taiwan.

Input
Audio
Signal
Vin

Integrator
Output VI

Integrator
Triangular
Waveform VC

PWM
Signal bpwm
PWM

Power
Stage
Switching Audio
Signal

Filter
Filtered Audio
Signal

Fig. 1. The block diagram of a closed-loop class-D audio amplifier.

A typical closed-loop class-D audio amplifier is shown in

Fig. 1. It is a switch-mode amplifier with a power stage that
produces a switching audio signal. Within a given period of
time, the integral of this switching audio signal should be
identical to the integral of the input audio signal, Vin. To
achieve this operation, an integrator is used to regulate the
voltage feedback from the power stage with Vin, and is
responsible for suppressing non-idealities occurring in the loop.
In certain design, current feedback is also used to stabilize the
loop [6] and reduce nonlinearity [7]. Noise injected from the
power supply can also be removed from the loop to yield a high
power supply rejection ratio (PSRR). For analog PWM, the
integrator output VI is modulated with a triangular waveform
which serves as a carrier VC, where as a digital PWM utilize a
pulse former in the digital domain to determine the duty of the
switching signal [8], [9]. This operation is a sampling process
of VI, which results in a square waveform PWM signal bpwm(t).
The duty cycle of bpwm(t) corresponds to the magnitude of VI.
As shown in Fig. 2, the switching of bpwm(t) and the power stage
occur when VC intersects VI. Since electromagnetic noise is
generated due to the switching nature of the amplifier [10], the
cascaded output filter is required to remove the generated high
frequency components and obtain the filtered audio signal [11],
[12]. Notably, due to the nature of modulation, the PWM output
signal will be influenced by harmonics and inter-modulation
(IMD). Consequently, the THD and IMD performance of a
class-D audio amplifier is deteriorated [13].
Fortunately, by using different types of triangular waves as
carriers, the influences to the aforementioned non-idealities can
be reduced. This can be achieved by adding multiple triangular
wave phases and different DC levels to modify the modulation
characteristics. By analyzing their influences using the double
Fourier series method, it can be discovered that phase shifted
carrier pulse-width modulation (PSCPWM) [14]-[18] and

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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Triangular waveform VC

The first term represents the audio component in terms of I,

where M is the modulation index. The second term represents
the carrier components in terms of c, where m and n are the
coefficients for I and c. The third term represents the IMD
components generated by I and c. From (1), it is apparent
that reduction of carrier harmonic and IMD is possible by
reducing the coefficients of the second and third terms. This can
be achieved by PSCPWM and MLCPWM techniques used in
DC/AC inverters, which utilize different modulation schemes
[13]-[25] are described as follows.

Integrator output VI

PWM signal bpwm

Fig. 2. A PWM signal obtained by modulating the integrator output with

single phase single level triangular wave.

multi-level carrier pulse-width modulation (MLCPWM)

[19]-[25] with multiple numbers of phases and levels of
triangular wave combination can lead to better THD and IMD
performance. Since both PSCPWM and MLCPWM are
designed for DC/AC inverters, the implementation of these
topologies are not directly optimized for class-D audio
amplifier applications. These issues will be further described in
Section II. According to these results, the class-D audio
amplifier compatible dual-level dual-phase carrier (DLDPC)
PWM control is proposed to include both the advantages of
PSCPWM and MLCPWM to improve the THD. The PWM
spectral characteristics of the DLDPC PWM signal exhibits
similar components with those of PSCPWM and MLCPWM,
but the power stage is re-designed to accommodate the control
signal generated by the DLDPC PWM logic circuit. A test chip
was fabricated in a standard 0.5m CMOS process, and is
presented to verify the proposed DLDPC class-D audio
amplifier.
II. COMPARISON OF PWM, PSCPWM, AND MLCPWM
In a class-D audio amplifier, operation and output waveform
of the power stage are directly controlled by bpwm(t). Hence,
Fourier analysis can be applied to bpwm(t) to characterize its
frequency components and determine its THD and IMD
performance. Unfortunately, since the switching point in the
PWM waveform is determined by the trigonometric equation
involving both I and C (the angular frequencies of VI and VC,
respectively), the Fourier analysis has to be performed over the
interval according to the number of fundamental cycles [26].
Thus, the resulting numerical solution will quickly become
intractable. In order to overcome the aforementioned problem,
the double Fourier series method can be applied instead. The
derivation on the spectral components of bpwm(t) with double
Fourier series can be found in [26]-[32], and its result can be
expressed as (1).
bpwm (t ) M cos(I t I )
2 mM
J0

m
2
m 1
m
sin
cos m c t c
2

A. Phase shifted carrier pulse-width modulation (PSCPWM)

The PSCPWM scheme modulates VI with multiple triangular
waves as carriers [13]-[18]. Each triangular wave has a 360/N
phase shift compared to the adjacent triangular waves, where N
is the number of phases in the modulator of the PSCPWM
controller. The power stage as shown in Fig. 3(a) is composed
of N switching legs, each with its output impedance, Z.
Basically, all the output impedances have identical values, and
all the currents sum up at the load impedance, Zload.
In a closed-loop implementation, the regulator is used to
sense and regulate Vout from the feedback path with Vin.
Signals bpwm <1:N> are generated to control their respective
switches SW <1:N>. To visualize this operation, Fig. 3(b) is
drawn with bpwm <1:N> plotted with N carriers and VI. A
N-phase PSCPWM results in N+1 PWM decision levels, and
the effective discrete voltage levels at the output is increased by
a factor of N compared to its conventional PWM counterpart.
This type of implementation reduces the amplitudes of high
frequency components, where the total number of m in (1) is
reduced from 1, 2, 3 ...+ to N, 2N, 3N, ...+ [29], [32]. Hence,
the harmonic components of the carrier and IMD are reduced
by a factor of N, enhancing the fidelity of the amplifier
significantly. The double Fourier series can be applied [18], [29]
to express the spectral components of bpwm(t) as (2).
bpwm (t ) M cos I t I
mM
J0

2
2
m
m N ,2 N ,...

m
sin
2

cos m c t c

mM
Jn

2
(m n)
sin
2

m
2

m N ,2 N ,.. n 1
cos m c t c n I t I

(2)

(1)

2
mM (m n)

Jn
sin
2

m 1 n 1 m 2

cos m c t c n I t I

Unfortunately, the power stage required by the PSCPWM

scheme has to be implemented by N impedances through the
use of costly inductors. Furthermore, since the time constant of
each inductor and the speaker resistance creates a pole in the
frequency domain, the discrepancy of inductance values in each
inductor would result in different phase shift to each switching
leg, increasing harmonics. Hence, this modulation scheme is
not preferred.

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SW [N]

SW [2]

SW [1:N] PWM Signal

N
bpwm [1:N]
Driver

Regulator
Output VI

PSCPWM

Regulator

Reference
Signal Vin

SW <1>

SW </2> SW <NEG> SW <POS> SW </2+1>

SW <1:>
SW <POS/NEG>
Decoder
& Driver

SW <>

Vout
Feedback Path

Regulator

MLCPWM

PWM Signal N
bpwm <1:N>

Regulator Output VI
MLCPWM Carriers
VC <1:N>

(a)

Zload
Reference
Signal Vin

(a)

MLCPWM carriers:
VC <1>
VC <2>

VC <N>

Regulator output VI

PSCPWM carriers:
VC <1>
VC <2>
VC <N>
Regulator output VI


PWM signal bpwm <1>

PWM signal bpwm <1>

PWM signal bpwm <2>

PWM signal bpwm <N>

+V

DPOS <1:(/2-1)>

PSCPWM
Carriers VC [1:N]

DNEG <1:(/2-1)>

VDCN

(b)
Fig. 3. (a) A DC/AC inverter with the PSCPWM technique. (b) PWM
waveforms of the PSCPWM.

B. Multi-level carrier pulse-width modulation (MLCPWM)

As shown in Fig. 4(a), the MLCPWM [19]-[25] modulates
the integrator signal VI with N carrier levels, resulting in
N-levels of supply voltages at the power stage. N stacked VDC
voltage sources are used to generate different voltage levels to
drive Zload. PWM bpwm <1:N> signals are shown in Fig. 4(b).
Unlike the PSCPWM PWM, only the PWM signal with an
associated triangular wave that intersects with VI is switching,
while other PWM signal may remain static for an indefinite
period of time. The MLCPWM decoder and the driver are used
to convert bpwm <1:N> to the switch control signal, SW <1:>.
The MLCPWM approach has two major issues. The forward
conduction voltages of the diodes DPOS and DNEG in the
conduction path of the power stage cause additional distortion
to class-D audio amplifier applications. Furthermore, as the
number of N becomes increases, it is difficult to maintain low
conduction loss while more transistors are stacked.
The voltage level is equivalent to VDC multiplied by N-1,
resulting in a similar effect on the high frequency components
of bpwm, analogous to the PSCPWM technique. Hence, the
sideband and intermodulation harmonics are divided by N-1,
where the total number of m in (1) is reduced from 1, 2, 3 ...+
to N-1, 2N-1, 3N-1 ...+, resulting in a spectral characteristic
described by (3) [19], [27], and [30].

PWM signal bpwm <2>

PWM signal bpwm <N>

SW [1]

Zload

SW [N]

VDCN-1

VDC2

Feedback Path

SW [1]

VDC1

VDD

-V

Vout

SW [2]

(b)
Fig. 4. (a) A DC/AC inverter and (b) PWM waveforms of the MLCPWM
technique.

bpwm (t ) M cos I t I
mM
J0

2
2
m
m N 1,2 N 1,...

m
sin
2

cos m c t c

mM
Jn

2 sin (m n)
2

m
2
m N 1,2 N 1,.. n 1

(3)

cos m c t c n I t I

The MLCPWM approach has two major issues. The forward

conduction voltages of the diodes DPOS and DNEG in the
conduction path of the power stage cause additional distortion
to class-D audio amplifier applications. Furthermore, as the
number of N becomes increases, it is difficult to maintain low
conduction loss while more transistors are stacked.
Having addressed the advantages and disadvantages of both
the PSCPWM and MLCPWM techniques, it is clear that neither
approach is ideal for class-D audio amplifier applications if

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DLDPC carriers:
VC <1>
VC <2>

VC <3>

VC <4>

Switch signal SW
Integrator PWM signal
output VI bpwm <1:N1+N2>

VI

DLDPC
PWM

PWM signal bpwm <1>

PWM signal bpwm <2>

Reference
Signal Vin

PWM signal bpwm <3>

PWM signal bpwm <4>

Order
Integrator

used directly, yet each approach has its potential of reducing

harmonic components. Therefore, the dual-level dual-phase
carrier (DLDPC) PWM control is proposed to combine the
benefits of both the PSCPWM and MLCPWM techniques, in
order to achieve low harmonics.

VB2

bpwm (t ) M cos(I t I )

VOP

m( N 2 1) M
Jn

2
2
m( N 2 1)
m N1 ,2 N1 ,... n 1

cos[m( N 2 1)(c t c ) n(I t I )]

M5

VON

VIP

VIN

M7

M2
M4

M1
M3

M12 M16
M6

M8

(a)
VDD

VDD

M
VB1 B11
MB13 VB1

VB2

VOP

MB12

MB14 VB2

VDD

VCMFB

m( N 2 1)
sin
cos m(c t c )
2

MB6

MB2

M15 M11

M20

M17

m( N 2 1) M
J0

2
m( N 2 1)
m N1 ,2 N1 ,...

MB10 M14

MB5

The proposed DLDPC PWM control requires two sets of

non-overlapping triangular waves which are separately biased
at its corresponding offset voltage levels with non-overlapping
amplitudes. Each set of triangular waves is composed of two
180 out-of-phase triangular waves as shown in Fig. 5.
To obtain its spectral characteristics, the double Fourier
series is applied again to a PWM carrier with multiple phases
and DC offset voltage levels. By defining N1 as the number of
triangular wave phases, and N2 1 as the number of triangular
wave DC offset voltage levels, bpwm can be expressed as (4).

VC <1:N1+N2>

Fig. 6. Class-D audio amplifier with the proposed DLDPC PWM.

VDD
MB4
MB3
MB1
MB8
MB7
VCMFB
VB1
VCMFB
M13 MB9

III. DESIGN OF A CLASS-D AUDIO AMPLIFIER WITH THE

PROPOSED DLDPC PWM

Power
Stage

DLDPC
DLDPC
Triangular Wave
Carriers
Generator

2nd

Fig. 5. Waveforms of the proposed DLDPC PWM control technique.

N1+N2

M19

M21

M23

M22

M24

VON

(b)
(c)
Fig. 7. (a) A fully differential Class-AB operational amplifier, (b) CMFB,
and (c) bias circuit (start-up circuit not shown).

(4)

m( N 2 1) n
sin

The circuit realization of DLDPC PWM requires four

comparators for single-ended implementation, and eight
comparators for fully-differential implementation to compare
the integrator output with their respective triangular wave. As
shown in Fig. 6, the proposed closed-loop class-D audio
amplifier utilizes a generic 2nd order integrator to achieve high
signal to noise ratio (SNR). The fully differential class-AB
operational amplifier [33] is shown in Fig. 7(a), along with
common-mode feedback (CMFB) to stabilize DC operating
points, and bias circuit in Fig. 7(b) and (c), respectively. In Fig.

6, a four-phase triangular wave generator is used to emulate the

DLDPC triangular waves. The power stage is controlled by the
DLDPC PWM with an 8-bit output, bPWM <1:8>. The detailed
descriptions of the DLDPC triangular wave generator and the
DLDPC PWM are described in the following sub sections.
A. DLDPC triangular wave generator
According to Fig. 5, level high and level low triangular
waves must be biased at an appropriate voltage level, and must
not be overlapped. Failure in preventing the triangular waves
from overlapping will cause the integrator output to be sampled
twice, and the power stage will be erroneously triggered, which
results in double-sampling and undesired switching loss at the
power stage. On the contrary, if the non-overlapping gap is too
large, a dead-band will be generated. Both phenomena causes
severe degradation to THD performance. Moreover, since the
triangular waves are not controlled by the closed-loop, the 2nd
order integrator will not be able to suppress the distortions

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VDD

CLK

Master
MI1 Integrator

0.5C

1V

Q1

VDD

SR1_

MI2

Q1

ENC <1>

VC' <1>

VDD
R

VDD

Q2

SR2

4V

ENC <1:4>
VDD

DQ

CNT <1>
CNT <2>

DQ

CNT <1:2>

DQ

C
C

ENC <3>

ENC <4>

VC' <1:4>

VC' <3>

VDD

DQ

VC' <4>

4-bit Integrator

Encoder

Ripple Counter

VC' <2>

ENC <2>

Delayed Q

MI3

Fig. 8. Implementation and waveforms of the proposed DLDPC generator.

VDD
MB15
MB16

VB2
MC9
ENC
<n+2>

ENC
<n>

MS3

MS2

VIN2

MC3

VIP

MC13

MC14

MC15

MC1
MC6

MC5

MC11

MC12

MS1

VIN1

MC2

MC10

MC17
VCMP

MC16
MC18

MC7
MC8

Fig. 9. Voltage comparator with built-in analog multiplexer for PWM.

Fig. 10. THD performance with respect to triangular wave non-idealities.

caused by the dead-band. A deteriorated THD performance

negates the purpose of using DLDPC PWM.
To ameliorate this issue, a four-phase triangular wave
generator is used. This circuit includes a master integrator, a
ripple counter, an encoder, and a 4-bit integrator. The master
integrator is implemented to serve as an oscillator which
generates a pulse signal, Q1. Since the master integrator circuit
has identical behavior with the 4-bit integrators, the pulse
signal Q1 can adapt to the characteristics of the 4-bit integrators.
The operation of this master integrator can be described as
follows: Assume the integrator is initially charging and its
voltage begins to build up at its output. When 4V is reached, the
Q2 of the SR2 latch is triggered to logic high, M I1 is switched
off, and the voltage of the integrator will remain still. When the
external CLK signal set SR1 to logic high, MI3 is switched on
and the voltage of the integrator begins to decrease. When 1V is
reached, the Q of both SR latches becomes logic low, M I1 and
MI2 begin to conduct and the voltage of the integrator begins to
increase. These operations repeat indefinitely. Since the
capacitor of the master integrator is only half the capacitance
compared to the capacitors of the 4-bit integrator, the
oscillation frequency of Q1 is doubled in comparison with the
output of the 4-bit integrator, VC'. An encoder is used to
generate the 4-bit phase control signal ENC <1:4> from the

2-bit counter signal CNT <1:2>. Four DFFs are used to

synchronize each individual bit of ENC <1:4> to mitigate the
effect of any propagation delay generated by the encoder. Two
identical differential integrators are used to integrate
ENC <1:4> into the four phase triangular waves, VC <1:4>. The
CMFB circuits of the fully differential OP-AMPs will also help
to stabilize the DC level of the output triangular waveforms.
Due to the large value of capacitors used, the layout is widely
spread across the chip. In the event of device mismatch and
offset, the triangular waves may saturate near 1V or 4V by
several millivolts, and THD performance will be deteriorated at
the peak output power of 1.56W. However, since the THD
performance is already poor due to the influence of clipping at
the peak power output and other non-idealities, the
deterioration contributed by the triangular waves is negligible.
For this reason, the analysis is performed with the assumption
that the output power is not saturated.
The VC' waveforms generated by the four phase triangular
generator are not directly compatible with the DLDPC
modulation. In order to realize an operation equivalent to the
waveforms in Fig. 5, the voltage comparator used for PWM
operation has to be re-designed. As shown in Fig. 9, an analog
multiplexer is incorporated into the input stage of the

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comparator, and transistors MC2 and MC3 are connected to 180
out-of-phase triangular waves. The multiplexer transistors M S2
and MS3 are controlled by 180 out-of-phase digital signals
ENC <n> and ENC <n+2>. For the comparator responsible for
generating bpwm <1>, the multiplexer is controlled by ENC <1>
and ENC <3> to sense VC <1> and VC <3>. The comparator
responsible for generating bpwm <2> is controlled by ENC <2>
and ENC <4> to sense VC <2> and VC <4>, the comparator
responsible for generating bpwm <3> is controlled by ENC <3>
and ENC <1> to sense VC <3> and VC <1>, and the comparator
responsible for generating bpwm <4> is controlled by ENC <4>
and ENC <2> to sense VC <2> and VC <4>. The second and
third stage of the comparator consist of transistors MC9 to MC18,
which form a fully differential pair with latched load followed
by a differential to single-ended differential pair. An output
inverter is used to deliver the binary signal to the power stage.
In order to evaluate the impact on the accuracies of DLDPC
triangular wave generator, FFT is applied to bPWM with
MATLAB. The THD of the class-D audio amplifier is
evaluated over a wide range of non-idealities including the
triangular wave phase shift and offset of DC levels in Fig. 10.
To ameliorate this issue, a four-phase triangular wave
generator is used. This circuit includes a master integrator, a
ripple counter, an encoder, and a 4-bit integrator. The master
integrator is implemented to serve as an oscillator which
generates a pulse signal, Q1. Since the master integrator circuit
has identical behavior with the 4-bit integrators, the pulse
signal Q1 can adapt to the characteristics of the 4-bit integrators.
The operation of this master integrator can be described as
follows: Assume the integrator is initially charging and its
voltage begins to build up at its output. When 4V is reached, the
Q2 of the SR2 latch is triggered to logic high, M I1 is switched
off, and the voltage of the integrator will remain still. When the
external CLK signal set SR1 to logic high, MI3 is switched on
and the voltage of the integrator begins to decrease. When 1V is
reached, the Q of both SR latches becomes logic low, MI1 and
MI2 begin to conduct and the voltage of the integrator begins to
increase. These operations repeat indefinitely. Since the
capacitor of the master integrator is only half the capacitance
compared to the capacitors of the 4-bit integrator, the
oscillation frequency of Q1 is doubled in comparison with the
output of the 4-bit integrator, VC'. An encoder is used to
generate the 4-bit phase control signal ENC <1:4> from the
2-bit counter signal CNT <1:2>. Four DFFs are used to
synchronize each individual bit of ENC <1:4> to mitigate the
effect of any propagation delay generated by the encoder. Two
identical differential integrators are used to integrate ENC
<1:4> into the four phase triangular waves, VC <1:4>. The
CMFB circuits of the fully differential OP-AMPs will also help
to stabilize the DC level of the output triangular waveforms.
Due to the large amount of capacitors used, the layout is widely
spread across the chip. In the event of device mismatch and
offset, the triangular waves may saturate near 1V or 4V by
several millivolts, and THD performance will be deteriorated at
the peak output power of 1.56W. However, since THD
performance is already poor due to the heavy influence of other
non-idealities, such as clipping at the peak power output. For
this reason, the analysis is performed with the assumption that
the output power is not saturated.

6
The four phase triangular waves VC' are not directly usable.
To realize an equivalent operation as shown in Fig. 5, the
voltage comparator used for PWM operation has to be
re-designed. As shown in Fig. 9, an analog multiplexer is
incorporated into the input stage of the comparator, and
transistors MC2 and MC3 are connected to 180 out-of-phase
triangular waves. The multiplexer transistors MS2 and MS3 are
controlled by 180 out-of-phase digital signals ENC <n> and
ENC <n+2>. For the comparator responsible of generating bpwm
<1>, the multiplexer is controlled by ENC <1> and ENC <3> to
sense VC <1> and VC <3>. The comparator responsible of
generating bpwm <2> is controlled by ENC <2> and ENC <4> to
sense VC <2> and VC <4>, the comparator responsible of
generating bpwm <3> is controlled by ENC <3> and ENC <1> to
sense VC <3> and VC <1>, and the comparator responsible of
generating bpwm <4> is controlled by ENC <4> and ENC <2> to
sense VC <2> and VC <4>. The second and third stage of the
comparator consist of transistors MC9 to MC18, which form a
fully differential pair with latched load followed by a
differential to single-ended differential pair. An output inverter
is used to deliver the binary signal to the power stage. In order
to evaluate the impact on the accuracies of DLDPC triangular
wave generator, FFT is applied to bPWM with MATLAB. The
THD of the class-D audio amplifier is evaluated over a wide
range of non-idealities including of triangular wave phase shift
and offset of DC levels in Fig. 10.
B. DLDPC power stage and signal flow
The proposed sequenced gate drive circuit, as shown in
Fig. 11, is used to switch gradually. Delay elements are inserted
between the gate drive of staggered-size power transistors.
When the SR latches are triggered to logic high, the ON signal
propagates from the smallest to the largest transistor. If the
values stored in the SR latches are reset to logic low, the OFF
signal propagates from the largest to the smallest transistors.
The geometric progression on the aspect ratio of the power
transistors is set to 4 to optimize between transition time and
shoot-through current. This approach can avoid THD and EMI
caused by dead-time, and allows a higher switching frequency
of 700-kHz. When the switching frequency is higher, smaller
passive components can be used to implement the filter and to
reduce the overall size of the system at a cost of efficiency.
The power stage and signal flow of the DLDPC circuit is
shown in Fig. 12. The DLDPC generator creates VC' <1:4> and
ENC <1:4> to modulate the output of the integrator VI with the
comparators to generate PWM signals bPWM <1:8>. These
PWM signals are decoded and buffered by drivers to create SW
<1:8>. The power stage is composed of two sets of power
transistors to drive the bridge tied load (BTL). Each set contains
two N-type and P-type MOSFETs, which are used to produce
differential output levels from 0, VDD, VDD, VDD at SPKP
and SPKN to drive the BTL differentially. When all power
MOSFETs are turned off, small power MOSFETs are used to
short SPKN and SPKP, resulting in a voltage near VDD. The
ability to bias the BTL at a voltage of VDD and VDD lowers
switching loss when driving a signal at lower amplitude. This is
evident by inspecting (5) derived from [34].

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2015.2448518, IEEE Transactions on Industrial Electronics

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

TABLE I: COMPARISON TABLE

[2]

[26]

[27]

[28]/[29]

[30]

[31]

[32]

[33]

[34]

[35]

[36]

VDD (V)

This
work
0.5
CMOS
5

0.18
CMOS
2.7

0.5
CMOS
2.7

0.14
CMOS
5

0.5
CMOS
2.7

0.13
CMOS
2.5-6.6

0.25
CMOS
2.5-5.5

0.14
CMOS
5.3

0.5
CMOS
2.5

0.18
CMOS
3

0.13
CMOS
1.2

0.6
DMOS
12/20

Process (m)

THD (%)

0.01

0.018

0.0012

0.01

0.02

0.025

0.00122

0.015

0.3

0.022

0.008

0.00384

SNR (dB)
PSRR (dB)
@217-Hz
Efficiency (%)

95

92

94

92

94

104

103

100

80

80

87.2

100

88

88

70

80

77/81

93

96

85

65

85

85.5

89

92

89/90

91

93

81

92

77

73

88

Load ()
Max. POUT (W)
@THD+N=1%
fSW (KHz)

32

160

6/4

1.46

1.15

1.4

0.25

2.5

3.1

2.3

8/12

700

320

500

350

450

446

1000

>200

400

1.01

1.49/1.31

2.19

1.44

6.6

0.59

1.6

1.15

20.3

Die size(mm )

Delay
R

Q
Delay

Delay

Delay

Gate
Drive SW

Delay

Delay

Fig. 13. Chip micrograph.

S

1024

multiple-output (SIMO) converter and post regulators are used

to provide the voltages required, and has an efficiency of
75-87% from 0.2-1.46W, about 5% less compared to a standard
boost converter. An oscilloscope is used to measure the
modulated bPWM <1:4> signals for SPKP, which are buffered
internally by I/O devices and shown in Fig. 14. Since an
oscilloscope has only 4 channels, bPWM <5:8> are omitted. bPWM
<5:8> are used for SPKN, and is in general identical to bPWM
<1:4>, only 180 out of phase. The switching audio signals at
SPKP and SPKN are plotted along with the filtered audio
signals at 1-kHz in Fig. 15. Each side can switch from a range
of 0V to 5V (GND to VDD), which results in a differential
output of 5V.

Power
Stage

Delay

Decoder & Drivers

SW <5:8>
SW <1:4>

Vin <->

VDD

Comparators
bPWM <1:8>

Vin <+>

Integrator
VI <-> VI <+>

DLDPC Gen.
VC' <1:4> ENC <1:4>

Fig. 11. Sequenced gate drive with staggered power transistors.

VDD

Power
Stage
4

SPKP
VDD GND
VDD VDD

BTL
SPKN
4

VDD GND

Power
Stage

Fig. 12. DLDPC power stage and control signal flow.

PSW ,loss

1
Vcross I max trise t fall f SW

(5)

Vcross is the voltage across the transistor when it is off, Imax is

the conduction current through the transistor when it is on, and
trise/tfall is the time required to switch on/off the transistor. When
the class-D audio amplifier delivers only VDD and VDD to the
load, the loss calculated in (5) is divided by a factor of 4. In other
words, switching loss is reduced.
IV. MEASUREMENT RESULTS
The test chip shown in Fig. 13 is fabricated using a 0.5-m
CMOS process, with an area of around 2mm2. CLK is provided
externally at 2.8-MHz to generate VC. A single-inductor

The output spectrum is measured in Fig. 16, at 1-kHz input

signal and an output of 1W. As shown in Fig. 17, PSRR is
measured from 10-Hz to 10-kHz, and especially at 217-Hz with
a value of -88dB for a 200mV perturbation at VDD. The
efficiency and THD+N is plotted against output power in Fig.
18. The output power of the proposed class-D audio amplifier
must be larger than 0.39W for the DLDPC modulation to show
advantages. If the output power is smaller than 0.39W, the
power transistors connected to VDD and GND will not conduct.
This situation will limit power efficiency at light load, and
efficiency approaches 80% at a 0.6W output. Finally, a
comparison is made in Table I to compare the proposed
DLDPC class-D audio amplifier with prior arts.
V. CONCLUSIONS
In this paper, the PSCPWM and MLCPWM techniques
which were used in DC to AC inverter applications were
compared and discussed, which leads to the proposed DLDPC

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

8
-10
-20
-30

bPWM<1>

dB

-40
bPWM<2>

-50
-60
-70

bPWM<3>

-80
-90

bPWM<4>

10

100

Freq.(Hz)

1000

10000

10

SPKP (filtered)

THD+N(%)

Fig. 14. Measured bPWM <1:4> signals.

0.1

SPKN (filtered)
SPKP (switching)

0.01
SPKN (switching)

0.2

0.4

0.6

0.8

1.2

1.4

90
80
70
60
50
40
30
20
10
0
1.6

Efficiency(%)

Fig. 17. PSRR vs. frequency.

Fig. 18. Measured THD+N and power efficiency.

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PWM control. The proposed 2nd order closed-loop class-D

audio amplifier with the DLDPC PWM is capable of achieving
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http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2015.2448518, IEEE Transactions on Industrial Electronics

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

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Shang-Hsien Yang received the B.S. and M.S.
degrees in electrical engineering from National Sun
Yat-Sen University, Kaohsiung, Taiwan, in 2009 and
2011, respectively. He is currently working toward
the Ph.D. degree at the Institute of Electrical and
Computer Engineering, National Chiao Tung
University, Hsinchu, Taiwan.
From 2008 to 2011, he was with the VLSI Design
Laboratory, National Sun Yat-Sen University. He
joined the Ministry of Foreign Affairs, Taipei,
Taiwan, in 2011, where he served his national services. He is presently a
member of the Mixed Signal and Power Management IC Laboratory at
National Chiao Tung University. His current research interest includes
switching amplifiers and envelope tracking supply modulators for radio
frequency power amplifiers used in 4G LTE applications.
Yuan-Han Yang received the B.S. degree in
electrical engineering from National Cheng Kung
University, Tainan, Taiwan, in 1997, and the M.S.
degree in electrical and computer engineering from
National Chiao-Tung University, Hsinchu, Taiwan,
in 2013.
Since graduation, he joined Macronix Electronics,
Hsinchu, Taiwan, where he worked in the
Mix-Signal Department, and his research areas were
in the field of audio and power electronic
applications, including delta-sigma modulators and class D audio amplifier
circuits. Since 2011, he joined Samsung Electronics in Hsinchu, Taiwan. He
is currently the manager of TDC department, and his research areas are in the
field of display solution.
Ke-Horng Chen (M04SM09) received the B.S.,
M.S., and Ph.D. degrees in electrical engineering
from National Taiwan University, Taipei, Taiwan, in
1994, 1996, and 2003, respectively.
He is currently a Director and Professor of the
Institute of Electrical Control Engineering, National
Chiao Tung University, Hsinchu, Taiwan, where he
organized a Mixed-Signal and Power Management
IC Laboratory. He is the author or coauthor of more
than 200 papers published in journals and conferences, and also holds several
patents. His current research interests include power management ICs,
display algorithm and driver designs of liquid crystal display (LCD) TV,
Wireless Power Transfer, Energy Harvesting circuit designs.
Dr. Chen has served as an Associate Editor of the IEEE TRANSACTIONS
ON POWER ELECTRONICS, IEEE TRANSACTIONS ON CIRCUITS
AND SYSTEMSPART I: REGULAR PAPERS, and IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMSPART II: EXPRESS
BRIEFS. He serves as the CAS Taipei Sction Chair from 2015. He is the
Technical Program Committee Member, European Solid-State Circuits
Conference (ESSCIRC) (2014 - present). He is on the IEEE Circuits and
Systems (CAS) VLSI Systems and Applications Technical Committee, and
the IEEE CAS Power and Energy Circuits and Systems Technical
Committee.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Ying-Hsi Lin received the B.S. degree from
National Chiao-Tung University, Hsinchu, Taiwan,
in 1993, and the M.S. degree in electrical
engineering from National Taiwan University in
1995. He joined the Computer and Communication
Research Lab at ITRI as a researcher in 1995, and
became project leader of CMOS RF and high speed
mixed-signal circuits design in 1998. Since joining
ITRI CCL, he has been working on CMOS radio
frequency integrated circuits and mixed-signal
circuits IC design for computer and communication
application. In October 1999, He joined Realtek Semiconductor Corp., as an
RF manager. In 2010, he became the Vice President of Realtek and led the
Research and Design Center. He holds more than 30 patents in the area of
mixed-signal and RF IC design.
Tsung-Yen Tsai was born in Pingtung, Taiwan. He
received the B.S. from the Department of Electrical
Engineering, National Sun Yat-Sen University,
Kaohsiung, Taiwan, in 2004 and the M.S. degree in
Communication Engineering from National Chiao
Tung University, Hsinchu, Taiwan in 2006.
He joined Realtek Semiconductor Corporation in
July 2006 as an analog circuit designer. He is
currently responsible for several projects included
GPS, Bluetooth, WLAN802.11abg, 802.11n and
802.11ac. His research includes current DAC and switching regulators for
SoC.
Shian-Ru Lin was born in Nantou, Taiwan,
R.O.C., in 1978. He received the B.S. degree in
electronic engineering from National Taiwan
University of Science and Technology, Taipei,
Taiwan, in 2000, and the M.S. degrees in electronic
engineering from National Taiwan University,
Taipei, in 2003.
In 2003, he joined R&D Center of Realtek
Semiconductor Corp., Hsinchu, Taiwan, where he is
currently a Director. His research interests include
analog
and
mixed-mode
circuit
design,
high-speed/resolution data converters, timing recovery for communications,
high efficiency line driver, and power management IC.
Chao-Cheng Lee received the B.S. degree in
electrical engineering from National Chiao-Tung
University, Hsinchu, Taiwan, in 1988, and the M.S.
degree in physics from National Taiwan University,
Taipei, Taiwan, in 1990. He joined Realtek
Semiconductor, Hsinchu, Taiwan, in 1992 and is
currently the Senior Vice President of Engineering.
His research interests includes phase-locked loops,
filters, high-speed OP, and mismatch calibration. He
has more than 30 U.S. patents granted or pending.

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