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fully edited. Content may change prior to final publication. Citation information: DOI

10.1109/TIA.2015.2472360, IEEE Transactions on Industry Applications

Inverter for PV/Fuel Cell Applications

K Radha Sree, Student Member, IEEE and Akshay K Rathore, Senior Member, IEEE, Elena Breaz,

Member, IEEE, and Fei Gao, Senior Member, IEEE

voltage doubler based non-isolated inverter for a solar

photovoltaic, battery or fuel cell application is proposed in this

paper. Impulse commutation enables device voltage clamping

with zero current commutation of the semiconductor devices. It

eliminates the traditional problem of turn-off voltage spike

across the devices in current-fed converters. Unlike resonant

converters, resonance pulse appears for a very short interval

leading to zero current turn-off of devices. It therefore, limits

peak and circulating currents through the components. Voltage

doubler is selected to achieve 2x gain. Variable frequency

modulation ensures output voltage regulation with input and

load variations. Steady-state operation and analysis of front-end

converter is explained. A 500 W prototype has been designed and

developed to demonstrate the performance and verify the

proposed operation, analysis, and claims.

Index Terms Current-fed converter, Impulse commutation,

Soft-switching, Non-isolated, High gain.

I. INTRODUCTION

penetration of alternative energy sources owing to

increased environmental concerns. The concept of microgrid

is now celebrated with the penetration of non-conventional

energy sources such as solar photovoltaic (PV), fuel cells, etc.

Located close to the consumers and with a potential to

improve reliability, security and quality of electrical power,

microgrids sound promising for both islanded and grid

connected modes of operation [1]-[3]. The architecture of a

simple microgrid is shown in Fig. 1. Energy storage systems

offer stability against fluctuations associated with the

alternative energy sources and grid. Power converters are

mandatory to interface alternative energy sources and storage

to the dc bus or the grid [4], to match the nature of two ports

as well as accommodate the variability and intermittency [5].

Inverters are essential to convert the variable dc from the

non-conventional energy sources and storage to facilitate gridinterface as well as to feed local ac loads [6]. The inverter

should assure lower input current ripple for precise maximum

Computer Engineering, National University of Singapore, Singapore. Email:

eleakr@nus.edu.sg, radha_k@u.nus.edu. PH: +65 6516 6471, Fax: +65-6779

1103. E. Breaz and F. Gao are with University of Technology of BelfortMontbelliard, France. Email: elena.breaz@utbm.fr, fei.gao@utbm.fr.

current ripple also offers effective fuel utilization in fuel cells

etc. and enhanced battery performance. Configurations such

as the centralized inverter, string inverter, and moduleintegrated converters (MIC) are widely adopted. A detailed

review of the various MIC topologies available in literature is

highlighted in [7]. A transformerless inverter topology for

solar PV modules is proposed in [8]. It eliminates the shoot

through problem, reduces the ground currents, and

demonstrates high efficiency. Centralized inverters are

preferred when several cells are stacked to develop higher

voltage. It, therefore, does not require voltage boost and is

simpler in design and shows better efficiency. At low source

voltage, high voltage gain (up to 10-20x) is required for

mentioned applications and two-stage inverter is usually

implemented. In two stage inverters, the size of the dc link

capacitor responsible for power decoupling depreciates [9].

High-frequency (HF) transformer is usually required in case

of voltage-fed topologies. Dual-stage inverter topologies also

favor decoupled control where MPPT is realized by the dc/dc

converter and the inverter stage is responsible for the current

injection [10]. A novel dual-stage time-sharing dual mode

single-phase sine wave PWM inverter is proposed in [11]. It

minimizes the conduction and switching losses relative to a

regular hard switching boost converter based inverter

topology. Parallel resonant inverter with a dc-link switch for

soft-switching with hysteresis control is proposed in [12].

Current-fed voltage doubler can offer 10x voltage gain [13]

being transformerless and similarly a non-isolated current-fed

voltage quadrupler can offer 20x voltage gain. Current-fed

converters get inherently qualified for such applications as

they offer low input ripple [14]-[17] reducing the input filter

requirements and high voltage gain being transformerless.

Half-bridge topology comprising of dual boost converter [14],

[16] offers higher voltage gain compared to full-bridge

topology. Traditionally, dissipative snubber or active-clamp

circuit [17] is required to snub the device turn-off voltage

across the spike in current-fed converters. Dissipative

snubbers degrade the converter efficiency while the activeclamp requires floating switches and a large HF capacitor [18,

19]. Besides, a current-fed three-phase converter utilizing the

transformer leakage inductance and auxiliary capacitor to

achieve ZCS is proposed in [20]. A ZVS and ZCS operated

current-fed CL-resonant dc/dc converter is proposed in [21].

0093-9994 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See

http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI

10.1109/TIA.2015.2472360, IEEE Transactions on Industry Applications

2

A current-fed bidirectional full-bridge converter based

inverter is proposed in [22]. The proposed converter achieves

zero current switching (ZCS) of the primary switches and zero

voltage switching (ZVS) of the secondary devices with natural

device voltage clamping. Such bidirectional converter is best

suited for interfacing batteries with dc micro-grid, fuel cell

vehicles, or interfacing two dc buses in dc micro-grid.

This paper presents a unidirectional dual-stage impulse

commutated current-fed non-isolated voltage doubler based

inverter for low voltage dc sources including solar PV and

fuel cells as shown in Fig. 2. Impulse commutation achieves

the same merits without compromising on efficiency and

without increasing the component count.

Traditionally, impulse commutation has been adopted in

inverter circuits [23]-[24]. Its implementation for the proposed

topology offers zero-current commutation of the switches and

eliminates the turn-off spike and the associated losses. The

commutation strategy also enables natural voltage clamping

(NVC) across devices. Just an additional HF small parallel

capacitor [25]-[27] provides the above-mentioned benefits.

Although variable frequency modulation controls the load

voltage and power, the control circuit is simple because the

frequency variations are immune to the load variations.

The objectives of this paper are to explain the steady-state

analysis, operation, and design of the converter along with

experimental demonstration of the inverter performance.

II. STEADY-STATE OPERATION AND ANALYSIS OF IMPULSE

COMMUTATED CURRENT-FED VOLTAGE DOUBLER

To understand the steady-state operation and analysis of the

front-end impulse commutated current-fed voltage doubler

shown in Fig. 2, the following assumptions are made: (1)

Input boost inductors are sufficiently large to carry constant

current through them and (2) all semiconductor devices are

ideal and lossless. Components Ls and Cp constitute the

resonant tank that is responsible for impulse commutation.

The duty cycle D is fixed at a value above 0.5 while

variable frequency modulation controls the power transferred

and load voltage. The equivalent circuits illustrating the

operating modes and the steady-state operating waveforms are

shown in Fig. 3 and 4, respectively.

Switch S1 is conducting carrying a constant current Iin while

-Iin/2 flows through the series inductor. The parallel capacitor

voltage is clamped at Vdc/2. Switch S2 is blocking the

voltage Vdc/2. Rectifier diode Dr2 is conducting to transfer

power from source to the load.

Final values: iLs (t1) = -Iin/2, iS1 (t1) = Iin, vCp (t1) = vAB = -Vdc/2.

B. Interval 2 (Fig. 3(b): t1 < t < t2)

At t = t1, switch S2 is turned-on and the device capacitance

discharges in a very short interval of time.

C. Interval 3 (Fig. 3(c): t2 < t < t3)

Now, both the switches S1 and S2 are conducting and Dr2 is

still forward biased. The current in the incoming switch S2

starts increasing while the current in S1 starts falling. Positive

voltage Vdc/2 appears across the series inductor and iLs starts

increasing. The current expressions areV t t 2 I in

(1)

iLs (t ) dc

2 Ls

2

I

V t t2

(2)

iS1 t in iLs t I in dc

2

2 Ls

I in

V t t 2

(3)

iLs t dc

2

2 Ls

At the end of the interval, iLs reaches zero and the diode Dr2

gets reverse biased. Final values: iLs (t3) = 0, iS1 (t3) = iS2 (t3) =

Iin/2, vAB (t3) = 0. The duration of this interval can be given as

L I

(4)

T32 t 3 t 2 s in

V dc

iS 2 t

Capacitors C1 and C2 constituting the voltage doubler feed

the load. The resonance between Ls and Cp commences. The

energy stored in the tank increases. The switch currents iS1 and

iS2 start decreasing and increasing, respectively in a resonant

fashion. The resonant frequency and the characteristic

impedance at resonance can be given as

(5)

f r 1 2 Ls C p

Z r Ls C p

(6)

V

iLs t dc sin 2f r t t3

2Z r

(7)

iS1 t

I in Vdc

sin 2f r t t3

2 2Z r

0093-9994 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See

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(8)

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI

10.1109/TIA.2015.2472360, IEEE Transactions on Industry Applications

3

I in Vdc

(9)

sin 2f r t t3

2 2Z r

The voltage appearing across Cp is

V

(10)

vCp t dc cos2f r t t3

2

Final values: iLs (t4) = Iin/2, iS1 (t4) = 0, iS2 (t4) = Iin. The

duration of this interval can be given as

iS 2 t

T43 t 4 t 3

I Z

1

sin 1 in r

2f r

Vdc

T76 t 7 t 6

Ls

max

2Z r

70

VC1 VC 2

VCp

Vdc

Vdc

(19)

(20)

V dc

V in

1 f

n

4 4

n

2

1 x 1 sin 1 x 1 1 x

2

x

load resistance RFL and the characteristic impedance Zr, the

normalized frequency fn is the ratio of switching frequency fs

to the resonant frequency fr and x is given as M/rn. For the

given specifications and for a chosen Zr, the voltage gain

expression can be approximated as

to Vdc/2 and the rectifier diode Dr1 gets forward biased and

thus power gets transferred from source to load. Final values:

iS1 (t7) = 0 and iS2 (t7) = Iin, iLs (t7) = Iin/2, vCp (t7) = Vdc/2 and

vAB (t7) = Vdc/2. The duration of this interval can be given as

(b)

(18)

The DC gain of the converter, which is a function of the

normalized load rn and the normalized frequency fn is given as

(21)

During this interval, constant current Iin/2 from the boost

inductor flows through the series inductor and this charges the

parallel capacitor Cp. The voltage across the series inductor is

zero. Also, the input current flows through the switch S2. The

expressions governing this interval can be given as

V

I

(14)

v t dc cos 2f T in t t

2C p

doubler is explained with a design example. The

specifications of the converter are tabulated in Table I.

V

(17)

VS 1 VS 2 dc

r 42

During this short interval, the device capacitance CS1 gets

charged and the voltage across it builds up from 0 to Vdc/2.

(11)

Resonance ends at the end of this interval and iLs decreases to

Iin/2. Final values: iLs (t5) = Iin/2, iS1 (t5) = 0, iS2 (t5) = Iin. The

duration T53 is given as

2f rT43

(13)

T53 t 5t3

2f r

Cp

(15)

I in

symmetrical devices conducting during the other half cycle.

Intervals 1 to 7 cover half of the switching period. Therefore,

T

(16)

T t t s

Due to resonance, current iLs rises above Iin/2. This

additional current flows through the body-diode of S1 leading

to ZCS turn-off of switch S1. At t = tx, the current iLs reaches

its peak value Ip while the voltage across Cp reaches zero. The

necessary condition for ZCS is formulated as

V

I

(12)

I i t

dc in

p

(a)

(c)

(e)

(f)

Fig. 3. Equivalent circuits depicting the different intervals of operation of the front-end converter.

(d)

(g)

0093-9994 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See

http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI

10.1109/TIA.2015.2472360, IEEE Transactions on Industry Applications

4

A. Duty ratio

Variable frequency modulation controls the power

transferred from source to load at fixed value of duty cycle D.

To ensure ZCS with variation in input voltage, it is mandatory

to select D such that

(23)

Dmin D Dmax

Where, Dmin and Dmax can be given as

Dmin 0.5

I Z

Ls I in f s

f

n sin 1 in r

Vdc

2

Vdc

Dmax 0.5

I Z f

Ls I in f s

f

n sin 1 in r n

Vdc

2

Vdc 2

(24)

(25)

B. Current stress

The rms current through the switches is given by

12

1

1

x

(26)

I S 1, rms I S 2, rms I in f n

sin 1 x

2

4

6

be 7.36 A and 8.4 A for Vin = 48 and 42 V under full load

conditions. The average current through the rectifier diodes

can be given as

V

(27)

I Dr1, avg I Dr 2, avg dc

RL

The average current through the rectifier diodes is equal to the

load current.

TABLE I SPECIFICATIONS OF THE PROPOSED TOPOLOGY

Parameters

Values

Input voltage Vin

42 V 48 V

DC link voltage Vdc

200 V

RMS value of the output voltage Vo

110 V

Peak output power Po

500 W

Switching frequency range of the converter fs

50 kHz 150 kHz

Switching frequency of the inverter

50 kHz

Frequency of the output waveform

50 Hz

Vdc

1

Vin 0.251 f n

(22)

load can be computed from (22). For this specific design

example this range is between 50 kHz 150 kHz for

variations in Vin from 48 V down to 42 V.

C. ZCS Condition

Energy stored in capacitor Cp is responsible for achieving

and perpetuating ZCS with input voltage and load variations.

Its imperative to maintain stored energy in Cp at a higher

value as this circulating energy makes body-diode conduction

resulting in ZCS under all operating conditions. At the same

time, the maximum circulating energy that can be allowed for

ZCS operation has to be limited to minimize the associated

conduction losses. This goal is met by meticulously choosing

Zr that limits the peak current through the components. The

limitation on Zr can be given as

V

R

(28)

Z r in ,min FL

Vdc

where Vin,min is the minimum input voltage. With increase in

the range of input voltage variations, the chosen value of Zr

should be as small as possible to perpetuate ZCS operation

whilst this leads to increase in the circulating energy. But as

this energy circulates for considerably a short duration, it

doesnt substantially reduce the converter efficiency unlike

resonant converters.

D. Parameters of the resonant tank

Resonant tank parameters can be computed using (5) and (6)

once fs for the maximum gain condition is fixed. The

resonant frequency can be computed using (22). In this

design example, Zr =7.5 was selected to limit peak current

through the switches during overlap to 13.30 A using (12)

and to maintain ZCS between 48 V to 42 V. The computed

L and C values are 1.19 H and 21.2 nF, respectively.

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10.1109/TIA.2015.2472360, IEEE Transactions on Industry Applications

TABLE II PARAMETERS OF THE LABORATORY PROTOTYPE

Components

Parameters

MPP powder Core CS468125; 51 turns; 476

Boost Inductors L1~ L2

H;

Converter switches S1~S2

IPP110N20N3; 200V; 88A; Rds,on = 10.7m

Series inductor Ls

TDK RM14 PC40Z core, Ls = 1.19H

Parallel capacitor Cp

21.2nF, 1000V ceramic capacitor

4.7mF, 50V electrolytic & 2.2F, 400V HF

Input capacitor Cin

film capacitor

100 F, 400V electrolytic capacitor & 2.2F,

Output capacitors C1, C2

400V HF film capacitor

Rectifier diodes Dr1, Dr2

STTH30R04; 400; 30 A; VF = 0.97 V

Inverter switches S3 ~ S6

IPP60R125CP, 600 V, CoolMos.

T300-40 MPP Powder core

Output filter inductor Lf

Number of turns N = 285, Lf = 5.5mH

Output filter capacitor Cf

0.47 F, 1000 V, HF film capacitor

The anti-parallel body-diode D1 and D2 conduction time

ensures ZCS turn-off of the switches and is given (13). It is

approximately 0.33 s for Vin = 48 V, 500 W.

F. Boost inductor design

The inductances of the boost inductors is calculated as

V DTs T54

(29)

L in

I in

Where, Iin is the input current ripple. The inductances were

computed to be 400 H for Iin 0.4 A.

IV. EXPERIMENTAL RESULTS

The laboratory prototype of the experimental inverter, i.e.,

proposed non-isolated current-fed voltage doubler followed

by full-bridge inverter, rated at 500W is shown in Fig. 5. The

details of the prototype are given in Table II. Gating signals

for the switches were generated using Altera DE0Nano. Fig.

6 presents the experimental results for Vin = 48 V at 500 W.

Input inductor and inductors currents waveforms are shown

in Fig. 6(a). Input current is quite stiff dc. Inductors currents

are 180o phase-shifted with low ripple. Input filter

requirements are reduced because the ripple frequency is 2xfs.

Impulse commutation enabling ZCS turn-off of switch S2 is

shown in Fig. 6(b). The following can be inferred: (1)

Negative portion of iS2 indicates the anti-parallel body-diode

conduction and (2) Voltage across the switch VdS2 rises after

the body-diode commutates. The gating signal for S2 is

removed during the body-diode conduction. Overall, S2 turnsoff with ZCS eliminating the turn-off spike. Additionally, it

should be observed that switch voltage VdS2 is clamped

naturally at Vdc/2. Commutation of S1 takes place after 180.

Transformer voltage VAB with magnitude Vdc/2 is shown in

Fig. 6(c). Series inductor current iLs and the parallel capacitor

voltage VCp are shown. It is evident that the commutation

occurs during the overlap period (VAB = 0). The capacitor

voltage VCp also gets clamped to Vdc/2.

During the overlap period, the resonance causes the current

to rise above boost inductor current value Iin/2. The additional

current flows through the anti-parallel body-diode assisting in

ZCS turn-off of the switches.

During the overlap period no power is transferred to the

load. Once iLs becomes constant following resonance and after

VCp gets clamped to Vdc/2, the rectifier diode Dr1 gets forward

biased supplying power to the load. The current through the

rectifier diode Dr1 and the voltage across it is shown in Fig. 6

(d). This further affirms the ZCS operation of the rectifier

diodes. Fig. 6(d) also emphasizes the fact that the rectifier

diodes commutate with ZCS and the losses associated due to

reverse recovery and ringing are eliminated. Secondary

snubbers are not required due to the aforementioned reason.

The rectifier diodes block the dc link voltage Vdc.

The same explanation holds good for the other operating

condition depicted in Fig. 7 for output power of 100 W at Vin

= 48 V. Similar, waveforms with higher peak current is

observed at Vin = 42 V at output power of 500 W and 100 W

in Fig. 8 and Fig. 9, respectively.

It should be noted that the peak current flowing through the

series inductor Ls is the same under all operating conditions

(Vdc/2Zr) while the ratio of the peak to the constant current

(Iin/2) changes with the load and input voltage variations.

Current (ILs,peak - Iin/2) will be the maximum current flowing

through the body-diode of the switches and with higher input

voltage this circulating current decreases. Hence, to perpetuate

ZCS with change in input voltage, it is necessary to choose Zr

diligently such that ILs,peak gets minimized and at the same time

sufficient circulating current is available to allow body-diode

conduction with variation in input voltage. The experimental

results sighted above match closely with the steady-state

operating waveforms shown in Fig. 4. The additional current

aided by capacitor Cp circulates only during the overlap

period, i.e., resonance duration.

(a)

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10.1109/TIA.2015.2472360, IEEE Transactions on Industry Applications

(d)

(c)

(b)

Fig. 6. Experimental results for Vin = 48 V, 500 W (full load): (a) Input current Iin and Boost inductor currents iL1 and iL2 (2 A/ div; 10 s/div), (b) gate-source

voltage vgs2 (20 V/div, 5 s/div), drain-source voltage vds2 (200 V/div, 5 s/div) and current through switch S2 (20 A/div, 5 s/div), (c) voltage across AB (200

V/div, 5 s/div), voltage across the parallel capacitor Cp (200 V/div, 5 s/div) and current iLs through the series inductor (20 A/div, 5 s/div) and (d) rectifier

diode voltages vDr1 and vDr2 (200 V/div, 5 s/div) and series inductor current iLs (20 A/div, 5 s/div).

(a)

(b)

(c)

Fig. 7. Experimental results for Vin = 48 V, 100 W (20% load): (a) gate-source voltage vgs2 (20 V/div, 5 s/div), drain-source voltage vds2 (200 V/div, 5 s/div)

and current through switch S2 (20 A/div, 5 s/div), (b) voltage across AB (200 V/div, 5 s/div), voltage across the parallel capacitor Cp (200 V/div, 5 s/div) and

current iLs through the series inductor (20 A/div, 5 s/div) and (c) rectifier diode voltages vDr1 and vDr2 (200 V/div, 5 s/div) and inductor current iLs (20 A/div, 5

s/div).

(c)

(b)

(a)

Fig. 8. Experimental results for Vin = 42 V, 500 W (full load): (a) gate-source voltage vgs2 (20 V/div, 2 s/div), drain-source voltage vds2 (200 V/div, 2 s/div) and

current through switch S2 (20 A/div, 2 s/div), (b) voltage across AB (200 V/div, 2 s/div), voltage across the parallel capacitor Cp (200 V/div, 2 s/div) and

current iLs through the series inductor (20 A/div, 2 s/div) and (c) rectifier diode voltages vDr1 (200 V/div, 2 s/div) and diode current iDr1 (20 A/div, 2 s/div).

(b)

(c)

(a)

Fig. 9. Experimental results for Vin = 42 V, 100 W (20 % load): (a) Input current Iin (10 A/ div; 5 s/div) and Boost inductor currents iL1 and iL2 (2 A/ div; 5

s/div), (b) gate-source voltage vgs2 (20 V/div, 2 s/div), drain-source voltage vds2 (200 V/div, 2 s/div) and current through switch S2 (20 A/div, 2 s/div) and (c)

voltage across AB (200 V/div, 2 s/div), voltage across the parallel capacitor Cp (200 V/div, 2 s/div) and current iLs through the series inductor (20 A/div, 2

s/div).

devices. This minimizes the conduction losses in the circuit.

The voltage doubler circuit on the secondary offers 2x voltage

gain and the rest is obtained from the boost converter.

Losses in the rectifier diode have been eliminated because

of voltage doubler circuit. This has a significant impact on

variation in input voltage Vin is between 50 kHz 170 kHz at

full load condition. The frequency variation is less sensitive to

the load variations from full load down to 20% load.

Experimental results for next stage full-bridge inverter are

shown in Fig. 10.

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10.1109/TIA.2015.2472360, IEEE Transactions on Industry Applications

(c)

(a)

(b)

Fig. 10. Experimental results from the inverter circuit (x-axis: 5ms/div): (a) Gate to source voltage vgs5 (20 V/ div) and drain to source voltage vds3 (200 V/ div),

(b) gate to source voltage vgs4 (20 V/ div) and drain to source voltage vds4 (200 V/ div) (c) load current Io (20 A/ div) and load voltage Vo (500 V/ div) at 500 W.

efficiency with input variations that is obvious in PV and fuel

cells. The proposed inverter is also suitable for micro inverter

applications.

V. CONCLUSION

shown in Fig. 10. The gating signals and the voltage across

the switches S4 and S5 in one leg in the circuit is shown in Fig.

10(a) and Fig. 10(b) respectively. It is clear that the pair of

bottom switches S4 and S6 are operated at line frequency

minimizing the switching losses. The other pair is operated at

high frequency (50 kHz). The load current and the load

voltage at 500 W are shown in Fig. 10(c). The LC filter (Lf

and Cf) at the output stage and the line frequency modulation

reduces the distortion in the output voltage and current

waveforms favoring the use of the proposed two-stage

inverter.

Full load efficiency of the impulse commutated current-fed

voltage doubler is about 96.3 % for Vin = 48 V and about 96 %

for Vin = 42 V, respectively. While the efficiency at 20 % load

gets maintained at 91.2 % and 89 % for Vin = 48 V and Vin =

42 V, respectively. The rated efficiency of the overall twostage inverter is obtained as 93.4%. Loss distribution in the

current-fed voltage doubler at rated power of 500 W is shown

in Fig. 11. The efficiency curve with the variability of the

A dual stage non-isolated inverter with front-end currentfed interleaved voltage doubler is proposed for low dc voltage

renewable energy sources as well as energy storage

applications. An impulse-commutated circuit is implemented

to assist in zero current commutation and device voltage

clamping of the switches. ZCS turn-off of all semiconductor

devices is obtained. Voltage doubler offers 2x voltage gain.

The current-fed converter takes care of the stringent current

ripple requirements set by the PV or fuel cells. Impulse

commutation circuit can utilize the circuit parasitics to assist

in soft switching and voltage clamping. It also facilitates load

adaptive ZCS and perpetuates ZCS even with input voltage

variations. The voltage regulation is inherently less sensitive

to load variation making the control simple. Only one leg of

the next stage full-bridge inverter operates at HF while the

other leg operates at line frequency resulting in reduced

switching losses and low distortion in output ac waveforms.

Comprehensive analysis has been presented together with the

experimental results to verify the proposed design and

demonstrate the performance of the inverter.

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Mumbai.

K Radha Sree (S09) received her Bachelor's

degree in Electrical and Electronics Engineering

from Sri Sivasubramaniya Nadar College of

Engineering, affiliated to Anna University,

Chennai, India in 2012. She is currently pursuing

her Ph.D. in the area of Power Electronics in the

department of Electrical and Computer

Engineering, National University of Singapore,

Singapore. Her research interests include development of current-fed

converter technologies for renewable and distributed energy systems.

Akshay Kumar Rathore (M05, SM12)

received his Masters degree from Indian Institute

of Technology (BHU), Varanasi, India in 2003.

He was awarded Gold Medal for securing highest

academic standing. He obtained his PhD from

University of Victoria, Victoria, BC, Canada in

2008. He was a recipient of University PhD

Fellowship

and

Thouvenelle

Graduate

Scholarship. He had two subsequent postdoctoral

research appointments with University of Wuppertal, Germany, and

University of Illinois at Chicago, USA.

Since November 2010, he is an Assistant Professor in Department of

Electrical and Computer Engineering, National University of Singapore,

Singapore. He has published above 120 research papers in international

journals and conferences.

He is an Associate Editor of IEEE Transactions on Industry Applications,

IEEE Transactions on Transportation Electrification, IEEE Journal of

Emerging Selected Topics in Power Electronics, and IET Power Electronics.

He is also an editor of IEEE Transactions on Sustainable Energy.

Dr. Rathore is a winner and recipient of 2013 IEEE IAS Andrew W Smith

Outstanding Young Member Award and 2014 Isao Takahashi Power

Electronics Award.

professor at the University of Technology of

Belfort-Montbeliard (UTBM), Belfort, France.

She received the Master degree in electrical

engineering from Technical University of ClujNapoca in 2009 and the PhD degree in

engineering science in 2012 from the same

university in Romania. Her main research areas

include fuel cell modeling, electric hybrid

vehicle design and real time simulation

technology for energy systems. Since 2012, she is also a faculty member of

the electrical engineering department of Technical University of Cluj-Napoca.

associate professor at the University of

Technology of Belfort-Montbeliard (UTBM),

Belfort, France. He received respectively from

UTBM the Master's degree in electrical and

control system engineering in 2007, and the PhD

degree in renewable energy with distinguished

youth doctor reward in 2010. His main research

fields include fuel cells and their applications in

transportation, multi-physical modeling and real

time simulation systems. He is the head of the energy production division of

energy department of UTBM, and the chair of fuel cell modeling axis of the

Fuel Cell Research Federation (FR CNRS) in France.

http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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