SCHOOL OF ELECTRICAL ENGINEERING

& TELECOMMUNICATIONS
ELEC2141 DIGITAL CIRCUIT DESIGN
ASSIGNMENT 1
DUE DATE: 26TH APRIL 20
William Baxter
z3463372

Question 1
An arithmetic unit is an integral part of a central processing unit in
microprocessors, microcontrollers and microcomputers. Addition, subtraction,
multiplication and division are the basic arithmetic operations that are
performed by the arithmetic unit. In this problem, you are to design a
combinational circuit that does division operation. The circuit will divide a 3-bit
positive binary number a = (a2a1a0)2 by a 2-bit positive binary number b =
(b1b0)2 and calculate a 3-bit quotient q = (q2q1q0)2 and a 2-bit remainder r =
(r1r0)2 so that

a
r
=q+
b
b
The combination circuit will have the 3-bit binary number, a = (a2a1a0)2, and
the 2-bit binary number b = (b1b0)2, as inputs and the 3-bit quotient, q =
(q2q1q0)2, and the 2-bit remainder
r = (r1r0)2, as outputs. You can assume that the binary number, b = (b1b0) =
(00)2, of zero, will never be requested.
Your design solution must include your choice of circuit implementation, its
justification and verification.
[Hint: you may use five-variable Karnaugh maps or functional blocks to solve this
problem.]
Specification
As described in the question above, we are to design the division process for an
arithmetic unit that will divide a positive 3-bit binary number a = (a2a1a0)2 by a
positive 2-bit binary number b = (b1b0)2, with a and b functioning as our inputs.
The implemented circuit will then provide a positive 3-bit binary number q =
(q2q1q0)2 and a positive 2-bit binary number r = (r1r0)2 as outputs.
Formulation
In order to define a relationship between our inputs and outputs, it is very
possible that we may use Karnaugh maps or even functional blocks to form a
possible solution to this problem. However, implementing a solution based off a
Karnaugh map will prove tiresome as there are 5 variables involved; specifically
a2, a1, a0, b1 and b0, each functioning as an input. A logical approach to this
question would be to first derive the truth table for this problem. As stated, there
are five variables present as our input, and so we will require

25=32 rows, with

10 columns, with the last 5 from the right operating as our output values. The
truth table is as follows, with a coded in red, b in blue, q in green, and r in black:

Now that the truth table has been derived, we are now able to determine that 5variable Karnaugh maps and functional blocks are not necessary in finding an
efficient, practical design with a low gate-input-cost (GIC). By inspection, the
table above reveals certain relationships that occur between many, but not all
the input and output variables, if we were to take cases of the divisor. As the
question states that we can assume the binary number b = 00 (0) will never be
requested, we shall take cases with b = 01 (1), b = 10 (2) and b = 11 (3).

When b = 01 (1), we see that the remainder r will always be equal to zero,
as a number divided by 1 will always output a null remainder with a
quotient equivalent to the dividend. From the listed values, we can
determine that q2q1q0 = a2a1a0, with q2 = a2, q1 = a1, and q0 = a0.
When b = 10 (2), we are able to form a relationship for the remainder bits
such that r1 will always be equal to 0, and r0 =a0. Inspecting the quotient

columns, and comparing these values with each a bit input columns, we
see that q2 = 0, q1 = a2, and q0 = a1.
Finally, taking the case where b = 11 (3), inspection of the quotient
columns reveals that
q2 = 0 and q1 = a2a1.
However, there is no
clear relationship combining
0
0
1
0
q0 with our input
variables. Thus, a 3-variable
Karnaugh map
provides a solution.
1
1
0
0

a1 a0
a2

0
0
1
1

00

01

111 10

It is clear that q0 = a2a1 + a2a1a0 [where X denotes a complemented

variable].
Similarly to q0, inspecting the remainder columns for b = 11 (3) reveals no
clear relationships between the inputs and outputs. Once again using 3variable Karnaugh maps for both r1 and r0:

a1 a0

a1 a0
a2

00

01

a2

111 10

00

01

111 10

r0 = a2a1a0 + a2a1a0 +
a2a1a0

r1 = a2a1a0 +
a2a1a0

Optimisation
Having now obtained the equations with respect to our cases, we can now
further optimise these expressions in order to reduce GIC:

When
o
o
o
o
o
When
o
o
o
o

b = 01 (1),
q2 = a2
q1 = a1
q0 = a0
r1 = 0
r2 = 0
b = 10 (2),
q2 = 0
q1 = a2
q0 = a1
r1 = 0

When
o
o
o
o
o

b = 11 (3),
q2 = 0
q1 = a2a1
q0 = a2a1 + a2a1a0
r1 = a2a1a0 + (a2+a0)a1
r0 = a2(a1+a0) + a0(a2
XOR a1)

o r0 = a
It is clear that implementing our design with separate multiplexers for each
output variable will provide a robust circuit that is able to satisfy the division
operation and will prove efficient to troubleshoot; with a2a1a0 operating as
source inputs into our 4-input MUXs and b1b0 as our control inputs; with b
selecting the appropriate input/output values for each MUX whenever EN
(enable) is active high (1). Constructing a circuit in this format will provide a GIC
of 60, as our floating nets will not function as inputs (since b1b0 = 00 (0) will
never be requested, and corresponds to position D0 on each multiplexer). This
creates a much simpler circuit, with a lower GIC than that produced from 5variable Karnaugh maps. As the question does not specify any particular logic

gates to be implemented,
technology mapping will not
be necessary. The circuit
diagram is as shown:
Verification
In this design, the Xilinx ISE
CAD tool was used to
simulate and verify the
circuit. The waveforms are
shown below, representing
the input/output
combinations with respect to
our cases, and are all in
agreement with our truth
table. (As stated above, the
floating nets did not
function as inputs, and so
took no values throughout
the duration of the
simulation, thus producing a
red-lined reading.)

Question 2
Function generators can be
implemented by digital
circuits. In this problem, you
are to design a
combinational circuit that
generates a sinusoid. The
sinusoidal function for angles
less than or equal to

can be approximated by:

( 2 ))

y=2n round( ( 2n1 ) sin x

Where the function round rounds a number to the closest integer, x is a decimal
fraction that can be represented by an (n+1)-bit binary fraction as:

n+1
. x1 x 2 x3 x 4 x
n +1

x=( )2 = xi 2i
i=1

and the value of the sinusoidal function, y, is a decimal representation of an n-bit

binary fraction:
Waveform
Waveform
for for
b =b 10
=
(2)11 (3)

Waveform for b =
01 (1)

y=(. y1 y 2 y 3 y n )2= y i 2i
i=1

For this design, you may assume n = 3, where x and y are decimal fractions
represented by 4-bit and 3-bit binary fractions respectively.
The desired digital circuit will take four binary numbers,

x1 x2 x3 x4 ,

as inputs.

The four binary inputs represent the 4-bit binary fraction of x, which indicates

the sinusoidal calculation for an angle of x 2

radian is requested. For example,

a decimal fraction of x = 0.0625 is represented by binary inputs of 0001, which

o

is the request for calculating the sinusoid for 0.0982rad ( 5.62

desired digital circuit will generate three binary outputs
represent the 3-bit binary fraction of
outputs,

angle. The

y 1 y 2 y 3 , that

y=(. y1 y 2 y 3 )2 . The generated binary

y 1 y 2 y 3 , of the digital circuit will have to go through a DAC (Digital-to-

Analog Convertor) to produce the calculated sinusoid, y, in analog form (in a

strict sense it will be discrete). At the input side, the angle for which the sinusoid
is to be calculated will be processed by some signal conditioning circuit and ADC
(Analog-to-Digital Convertor) to produce the four binary bits,

x1 x2 x3 x4 ,

that

will be applied as inputs to the digital circuit. The complete system of the
sinusoid generator can be illustrated in the form of block diagrams as shown in
Fig. 1.

You are required to design the shaded block, the circuit which does sinusoid
calculation. Use NAND only technology for your digital circuit implementation.
Your solution should include verification.

Specification

In this problem, we are to design the logic that will be implemented in a circuit
responsible for sinusoid calculation within a function generator using NAND only
technology (with the exclusion of inverters). Our 4-bit decimal fraction input x
will be plugged into the sinusoidal function above, approximating an angle less
than or equal to

2 , and returning a 4-bit binary output y.

Formulation
A relationship linking our input and output variables will be clarified through the
derivation of a truth table, with x1, x2, x3 and x4 operating as our inputs and y1,
y2 and y3 as our outputs. For added ease, the table also includes columns for the

x and y decimal fractional equivalents.

Truth table for
Question 2
As there is no clear distinction between either of the input or output variables,
Karnaugh maps will be a suitable method of implementing our solution, and will
complement the condition of using NAND only technology.
x3 x4
x1 x2

x3 x4
00

01

111

10

x1 x2

00

00

00

01

01

11

11

10

10
Karnaugh map
for y1

01

111

Karnaugh map
for y2

10

x3 x4 0
x1 x2
00
01

00
1

01
1

111
0

10
0

11
10
Karnaugh map
for y3
As seen from the Karnaugh maps above, we obtain the initial Boolean equations:
y1 = x1 + x3x2
[GIC = 4]
y2 = x3x1 + x3x2 + x4x3x2 [GIC = 12]
y3 = x4x3 + x3x2x1 + x3x2x1 + x3x2x1 + x4x3x2x1
[GIC =
24]
Optimisation
Although applying two-level and multiple-level optimisation will reduce GIC, in
this particular case, as we are technology mapping to NAND only technology, this
will actually increase the final GIC for y1, y2 and y3. For instance, y1 cannot be
simplified any further, however y2 can be simplified to y2 = x3(x1 + x4x2) +
x3x2, and y3 can be simplified to y3 = x3[x4 + (x3 XOR x1)] + x3(x2x1 +
(x4+x2+x1)). However, once the circuit is converted to its NAND only
equivalent, the GIC of y2 would be equal to 13 (an increase of 1 gate-input),
while the GIC of y3 would equal 36 (an increase of 12 gate-inputs). These are
significant increases from GICs of 5, 12 and 20 for y1, y2 and y3 respectively
when their circuits are reconstructed with NAND only implementation from the
initial equations obtained from the Karnaugh maps. Thus, the optimised Boolean
equations obtained from the Karnaugh maps above will function as the
relationships we will use to derive our circuit diagrams. Hence, prior to
technology mapping, the total GIC will be equivalent to 4 + 12 + 24 = 40. Each
output will have its own individual circuit in order to improve any troubleshooting
and further analysis.

Circuit diagram for y1 prior to

technology mapping (GIC = 4)

Circuit diagram for y2 prior to

technology mapping (GIC =
12)

Circuit diagram for y3 prior to

technology mapping (GIC =
24)

Technology Mapping
The problem requires us to implement our solution with NAND only technology,
thus the resulting logic gates in the circuits above must be replaced with their

respective NAND equivalents. This is shown below. As done previously, it will

prove simpler to analyse if we were to separate each variable output into its own
separate circuit, rather than one entire netlist. After implementation, it is seen
that our new total GIC is equal to 5 + 12 + 24 = 41.

Circuit diagram for y1 using

NAND only technology (GIC =
5)

Circuit diagram for y2 using

NAND only technology (GIC
= 12)

Verification

Again, for this problem, theCircuit

Xilinx diagram
ISE CAD for
tooly3
was
used to simulate and verify
using
the circuits. Although we could have combined the separate circuits to form one
NAND only technology (GIC =
entire netlist, having separate circuits would prove easier to troubleshoot. Hence,
24)
the waveforms are shown below, representing
all possible input/output
combinations that are in agreement with our formulated truth table.

Waveform for
y1

Waveform for
y2
Waveform for
y3

Question 3
Design a digital circuit that controls a security system. The security system
consists of a floodlight (F), a daylight detector (D), a motion detector for
potential criminals (C) and a switch that sets the security mode. The switch has
four settings marked as mode 0, 1, 2 and 3.
When the switch is set to mode 0, the floodlight will be turned OFF. When the
switch is set to mode 1, the floodlight should be turned ON. The switch needs to
be set to mode 2 if the floodlight is to be turned ON when a potential criminal is

detected at night time. When turning the floodlight ON at night time is required,
the switch is to be set to mode 3.
The switch outputs 2-bit binary code (A, B) corresponding to its mode. For
example, when the switch is set to mode 2, it outputs AB = 10. Assume the
floodlight and detector signals are active high. This means floodlight is turned
ON when driven by logic 1 and the detector output is 1 when detection is
asserted.
The desired digital circuit will generate a binary output which will control the
floodlight through a driving circuit and will take the daylight detector, the motion
detector, and the binary outputs from the switch that sets the security mode as
inputs.
Your design should include your design procedure, choice of implementation, and
verification.
Specification
The above problem requires us to design a digital circuit that controls a security
system, consisting of a flood light (F), a daylight detector (D) and a motion
detector for any potential criminals (C), as well as a switch that sets the
corresponding security mode. This switch is marked as mode 0, 1, 2 and 3, with
the floodlight, daylight and criminal detector operating as active high (i.e. if D =
0, then it is night time, and if C = 1, then a criminal is detected). The modes are
as follows:
When the switch is set to mode 0, floodlight is turned OFF.
When the switch is set to mode 1, floodlight is turned ON.
When the switch is set to mode 2, floodlight will be turned ON when C = 1.
When turning the floodlight ON when D = 0, then the switch is set to mode
3.
With a definition of these different modes, A, B, C and D will function as our input
variables, and F as our output.
Formulation
As there are only 4 input-variables, A, B, C and D, with a single output of F, we
must first derive the truth table in order to determine a possible relationship
between our input/output combinations. Unlike the previous problem, this
question does not specify any particular logic gates to be implemented in our
solution, so technology mapping will not be necessary.

Truth table for

Question 3
As there are only 4 variables involved in this particular question, we will once
again utilise Karnaugh maps to determine a Boolean equation for F in terms of
our inputs A, B, C and D. This will provide a simple, straight-forward solution
regarding our problem that will prove efficient to troubleshoot.
CD
AB

0
00

0
01

00

01

11

10

0
0
111
10

With appropriate grouping of our minterm values inside the Karnaugh map, we
obtain the initial Boolean equation F = AB + BD + ACD, giving us a GIC equal
to 12.
Optimisation
Using multiple-level optimisation, we are able to determine an equation for F
with a smaller GIC than the initial expression obtained from our Karnaugh map.
F = AB + BD + ACD
= B (A + D) + ACD
= B (AD) + ACD
This final equation gives us a GIC of 10, producing a circuit that would function
more efficiently than that of a multiplexer, as in modes 2 and 3, Karnaugh maps
would have to be used again in order to determine a possible relationship
between C, D and F. The GIC of a MUX implementation would then approximately
exceed that of our original Karnaugh map implementation.
Circuit diagram
for F

Verification
As with the previous questions, this problem used the Xilinx ISE CAD tool to
simulate and verify our circuit, cross referencing the input/output combinations
with those of our truth table, which are in agreement with one another. The
verification is shown below: