9/28/13

Computer Organization and Architecture MCQ

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Computer Organization and Architecture MCQ

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Machine Instructions and Addressing
Modes
ALU and Data-Path
CPU Control Design and Memory
Interface
I/O Interface (Interrupt and DMA
mode)
Instruction Pipelining and Cache
Main Memory and Secondary Storage

Show

Stack overflow causes

A.
B.
C.
D.

Hardware interrupt
External interrupt
Internal interrupt
Software interrupt

Submitted By Payal Preet

Answer C
Explanation Stack overflow occurs while execution of a program due to logical faults. So it is a
program dependent, hence interrupt activated.
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Which method is used for resolving data dependency conflict by the compiler itself?
A.
B.
C.
D.

Delayed load
Operand forwarding
Pre fetch target instruction
Loop buffer

Submitted By Payal Preet

Answer A
Explanation In case of delayed load technique the compiler detects the data conflict and reorder the
instruction as necessary to delay the loading of the conflicting data by inserting no operation
instructions.
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Fetch_And_Add(X,i) is an atomic Read-Modify-Write instruction that reads the value of
memory location X, increments it by the value i, and returns the old value of X. It is used in the
pseudocode shown below to implement a busy-wait lock. L is an unsigned integer shared variable
initialized to 0. The value of 0 corresponds to lock being available, while any non-zero value
corresponds to the lock being not available.
AcquireLock(L){
while (Fetch_And_Add(L,1))
L = 1;
}
ReleaseLock(L){
L = 0;
}
This implementation
A. fails as L can overflow
B. fails as L can take on a non-zero value when the lock is actually available
C. works correctly but may starve some processes
D. works correctly without starvation
Submitted By Payal Preet
Answer B
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An interrupt can be temporarily ignored by the counter is called
A.
B.
C.
D.

Vector interrupt
Non maskable interrupt
Maskable interrupt
Low priority interrupt

Submitted By Payal Preet

Answer C
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Example of 16 bit microprocessor are
A.
B.
C.
D.

8085/Z80/6800
8086/68000/Z8000
80386/80486
None of above

Submitted By Raghu Garg

Answer B
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ADI
A.
B.
C.
D.

Add to Accumulator using carry Flag

Add to Accumulator
Add Immediate data to Accumulator
Add Immediate data to Accumulator Using carry

Submitted By Raghu Garg

Answer C
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9/28/13

Computer Organization and Architecture MCQ

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Identify the devices given below with their IC numbers :
(i) USART
(a) 8251
(ii) Micro controller
(b) 8051
(iii) Interrupt controller (c) 8259
(iv) DMA controller
(d) 8257
A. (a) (b)

(c) (d)

B. (b) (a) (d) (c)

C. (c) (d) (a) (b)
D. (d) (a) (b) (c)
Submitted By Payal Preet
Answer A
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The ascending order or a data Hierarchy is
A. bit - bytes - fields - record - file - database
B. bit - bytes - record - field - file - database
C. bytes - bit- field - record - file - database
D. bytes -bit - record - field - file - database
Submitted By Payal Preet
Answer A
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In a k-way set associative cache, the cache is divided into v sets, each of which consists of k lines. The
lines of a set are placed in sequence one after another. The lines in set s are sequenced before the
lines in set (s+1). The main memory blocks are numbered 0 onwards. The main memory block
numbered j must be mapped to any one of the cache lines from
A.
B.
C.
D.

( j mod v ) * k to ( j mod v ) * k + (k - 1)
( j mod v ) to ( j mod v ) + (k - 1)
( j mod k ) to ( j mod k ) + (v - 1)
( j mod k ) * v to ( j mod k ) * v + (v - 1)

Submitted By Payal Preet

Answer B
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How many address lines are needed to address each memory locations in a 2048 x 4 memory chip?
A.
B.
C.
D.

10
11
8
12

Submitted By Payal Preet

Answer B
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