IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 36, NO.

6, NOVEMBER/DECEMBER 2000

1645

Multilevel Inverter Modulation Schemes to Eliminate

Common-Mode Voltages
Haoran Zhang, Member, IEEE, Annette von Jouanne, Senior Member, IEEE, Shaoan Dai, Student Member, IEEE,
Alan K. Wallace, Fellow, IEEE, and Fei Wang, Senior Member, IEEE

AbstractIt is well known that conventional two-level

pulsewidth modulated (PWM) inverters generate high-fre. Similarly,
quency common-mode voltages with high
commonly used multilevel inverter modulation schemes generate
common-mode voltages. Common-mode voltages may cause motor
shaft voltages and bearing currents and conducted electromagnetic
interference (EMI). Premature motor bearing failures and electronic equipment malfunctions have been reported to be directly
related to bearing currents and EMI. In this paper, approaches to
eliminating common-mode voltage when using multilevel PWM
inverters are presented. It is shown that inverters, which have an
odd number of levels, will generate zero common-mode voltage by
switching among certain states. Therefore, motor bearing currents
will be eliminated and conducted EMI will be reduced. Both
sinusoidal PWM and space-vector modulation (SVM) schemes are
discussed and detailed comparative simulation results between
conventional and novel modulation schemes are provided. The
value of the proposed technique is demonstrated experimentally
by applying the novel SVM approach to a conventional multilevel
inverter.
Index TermsCommon-mode voltages, modulation schemes,
motor drive, multilevel converter, multilevel inverter.

I. INTRODUCTION

ONVENTIONAL two-level pulsewidth modulated

(PWM) inverters and multilevel PWM inverters generate
common-mode voltage within the motor windings which may
result in motor and drive application problems [1][3]. The
common-mode voltage enables motor shaft voltage to build up
through electrostatic couplings between the rotor and the stator
windings and between the rotor and the frame, resulting in
excessive bearing currents when the shaft voltage exceeds the
dielectric capability of the bearing grease. It has been found that
bearing currents may cause premature motor bearing failures.
At the same time, the common-mode voltage will cause a much
larger common-mode leakage current to flow into the ground
via electrostatic coupling between the stator windings and the
grounded frame. Since this current will eventually flow back to
Paper IPCSD 00030, presented at the 1998 Industry Applications Society
Annual Meeting, St. Louis, MO, October 1216, and approved for publication in
the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Industrial Drives
Committee of the IEEE Industry Applications Society. Manuscript submitted
for review October 15, 1998 and released for publication June 19, 2000.
H. Zhang is with Texas Instruments Incorporated, Tucson, AZ 85706 USA
(e-mail: zhang_haoran@ti.com).
A. von Jouanne, S. Dai, and A. Wallace are with the Department of Electrical
and Computer Engineering, Oregon State University, Corvallis, OR 97331-3211
USA (e-mail: avj@ece.orst.edu; dai@ece.orst.edu; wallace@ece.orst.edu).
F. Wang was with GE Industrial Systems, Salem, VA. He is now with the GE
China Technology Center, Shanghai, China (e-mail: f.wang@ieee.org).
Publisher Item Identifier S 0093-9994(00)10423-2.

the input terminals through the ground conductor and the power
mains, it will cause significant common-mode electromagnetic
interference (EMI) emission. In addition, the leakage current
may cause false tripping of ground current relays installed for
protection. There have been a number of mitigation techniques
suggested for the bearing current problem and conducted EMI.
However, few of them have addressed the common-mode
voltage directly and successfully and none of them have been
found within the context of multilevel PWM inverters. In [4],
a dual-bridge inverter (DBI) is presented to generate zero
common-mode voltage. Although the motor shaft voltage and
the resulting bearing currents are eliminated successfully, a
double-winding (i.e., a dual voltage) induction motor becomes
necessary. The DBI has also been shown to be able to reduce
conducted EMI significantly [5]. In [6], an active filter is proposed to cancel the common-mode voltage and reduce ground
current and conducted EMI, however, a common-mode transformer of significant size has to be used. Besides these efforts
devoted to new inverter topologies, a space-vector algorithm
was also proposed to minimize the neutral-to-ground voltage
by synchronizing the
of the motor stator winding to
switching sequence of the rectifier and inverter, which limits
the current control capabilities [7].
Multilevel inverters have received increased interest due
to their operational advantages [8][17]. Three-level PWM
inverters, usually in the form of either diode-clamped multilevel
inverters (DCMLIs) or flying-capacitor multilevel inverters
(FCMLIs), are typically considered for medium-voltage level
(2300/4160 V) drives to reduce the voltage rating of the power
switching devices as well as the harmonic components of the
output voltages. However, commonly used modulation schemes
still result in nonzero common-mode voltages [8][17]. In this
paper, two modulation schemes are suggested for the control
of multilevel inverters to eliminate common-mode voltages.
It will be shown that a three-level inverter will not generate
common-mode voltages when the inverter output voltages
are limited within certain of the available switching states.
The same concept could be extended to other odd number
multilevel inverters. At medium voltage levels, such controlled
multilevel inverters will still provide reduced device voltage
ratings and improved harmonic characteristics over two-level
inverters, whereas, at low voltage levels (230 V/460 V),
three-level inverters could be considered mainly for the purpose
of cancellation of common-mode voltages. Simulation results
using Matlab are provided in this paper to verify the concept,
and experimental results confirm the value of the proposed
switching-state algorithm.

00939994/00$10.00 2000 IEEE

1646

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 36, NO. 6, NOVEMBER/DECEMBER 2000

Fig. 1. Output stage of an NPC inverter.

Fig. 3. Seven states with zero common-mode voltage.

Fig. 2. Possible switching states of a three-level inverter.

II. MODULATION SCHEMES FOR COMMON-MODE VOLTAGE

ELIMINATION
The output stage of conventional two-level PWM inverters
consists of three phase legs with two switches on each leg. The
or
. Therefore,
output of each phase is either
the combinations of the three-phase output voltages result in
for
) switching states, i.e.,
,
,
8(
,
,
,
,
, and
. To be more clear,
represents the following output
,
, and
. Since the
voltage:
,
common-mode voltage is defined as
it is not zero for all of the above switching states.
The first three-level diode-clamped voltage-source inverter,
the neutral-point-clamped (NPC) inverter, was first proposed
by Nabea et al. [8]. Fig. 1 shows the output stage of the NPC
voltage-source inverter (VSI). It consists of 12 switches, 12 antiparallel-connected freewheeling diodes, six clamp diodes, and
a split dc bus via two capacitors. There are two important features of the NPC-VSI compared to conventional two-level inverters. First, four switches are used in series for each inverter
leg instead of two, allowing the off-state switches to sustain only

Fig. 4. Synthesis of the reference voltage vector V

half of the dc-bus voltage instead of the full voltage. Second,

,
the output voltage of each phase has three levels, i.e.,
. An increased number of voltage levels results
0, and
in increased switching states. In this case, the NPC-VSI has 27
states as shown in Fig. 2 [9]. Among these switching states,
there are seven states that will result in zero common-mode volt,
,
,
,
,
,
ages. They are
and (0 0 0), i. e., (see Figs. 3 and 4). It is obvious that the
common-mode voltage of the NPC inverter is zero for all the
above seven states. Therefore, by limiting the switching states
only to those listed above, an NPC inverter will not generate
common-mode voltage. This idea could be equally applied to
FCMLIs and higher level inverters. However, since only voltage
levels of odd numbers contain the state of zero output voltage
(0 0 0), even number level inverters (i. e., two, four, six levels,
etc.) cannot be controlled in this way to achieve common-mode
voltage cancellation.
Like conventional inverters, the main purpose of the control
of multilevel inverters is to synthesize the output voltage as close
as possible to the desired waveform, e.g., sinusoidal waveforms.

ZHANG et al.: MULTILEVEL INVERTER MODULATION SCHEMES

1647

Fig. 5. Sine-triangle intersection (SPWM) waveforms for a three-level

inverter.

Fig. 7. Three-level inverter with conventional SPWM.

Fig. 6. Sine-triangle (SPWM) for common-mode voltage cancellation.

Fig. 8. Three-level inverter with SPWM with common-mode voltage

cancellation.

Many modulation schemes have been developed with considerations to harmonic generation and switching loss minimization. However, the traditional sinusoidal PWM (SPWM) and the
space-vector modulation are still considered good choices for
multilevel PWM inverters due to the resulting overall inverter
performance. Therefore, detailed investigation into both modulation schemes to achieve common-mode voltage elimination is
presented in the following sections.
A. Voltage Space-Vector PWM
Any three-phase quantities, e.g., three-phase voltages or
currents, can be represented by a space vector in the plane
via Parks transformation. The vector starts from the origin and
ends at a certain point so that the length and the phase angle
of the vector together represent the instantaneous values of the
particular three-phase quantities. If the three-phase quantities
are sinusoidal functions of time and are symmetrical (balanced), the vector will be rotating at a constant angular velocity

and has a constant length and, thus, the locus of the vector
forms a circle. In other words, a rotating voltage vector can
represent three-phase sinusoidal voltages mathematically. If the
three-phase quantities are not symmetrical, Parks transformation gives not only , components, but also a zero-sequence
component that is the mean value of the three-phase quantities.
As far as the output voltages of a PWM-VSI are concerned,
this zero-sequence component is the common-mode voltage of
the inverter.
The basic idea of voltage space-vector modulation is to control the inverter output voltages so that their Park representation approximately equals the reference vector, which is the
Park representation of the desired three-phase voltage [13]. In
the case of a three-level inverter, the 27 switching states create
19 voltage vectors, including a zero vector as shown in Fig. 2.
These voltage vectors divide the plane into 24 triangular
sections. When the reference voltage vector falls in one of these
sections, adjacent voltage vectors are selected to synthesize the

1648

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 36, NO. 6, NOVEMBER/DECEMBER 2000

Fig. 11. Voltage spectra of a two-level inverter with SVM (m

= 1:15).

Fig. 9. Three-level inverter with SVM.

Fig. 12.

Fig. 10. Three-level inverter with SVM with common-mode voltage

cancellation.

desired voltage vector based on the time-averaging principle,

resulting in three-phase PWM waveforms. If the synthesized
voltage vector is a good approximation to the reference vector,
the three-phase PWM voltages should be good approximations
to the desired three-phase voltages.
Since three-level inverters have many more switching states
than two-level inverters, the algorithm for the determination of
belongs to and the selection of the
which triangular section
switching states and switching pattern are more difficult. However, they become quite straightforward if coordinate transformation is used. Fig. 3 shows the synthesis algorithm of an arbiin reference frame using aptrary reference voltage
propriate space vectors and coordinate transformations. First of
all, the whole voltage vector space is divided into six equal sectors, I-VI, by the dotted lines. By the examination of the phase

Voltage spectra of a two-level inverter with SPWM (m

= 1).

angle of
, the sector wherein
resides can be easily located. As an example shown in Fig. 3, the reference vector
is inside sector I. To synthesize
, it is also necessary to determine which triangular section it belongs to in the plane.
To obtain this information, coordinate transformations could be
is in sector I, it is apused. In the shown example, since
in
propriate to transform the vector in into
using the following equation:
(1)
It is again straightforward to locate the exact triangle wherein
resides by looking at the phase angle of
. In this ex,
and
. It
ample, it is the triangle defined by vector
should be noted that, whichever triangle is located, it belongs
to the hexagon centered at . By acknowledging this, a simple
control algorithm similar to that of the conventional two-level
SVM is obtained, which also features low harmonic distortion
in the PWM output voltage waveforms.

ZHANG et al.: MULTILEVEL INVERTER MODULATION SCHEMES

Fig. 13.

Voltage spectra of a three-level inverter with SVM (m

Fig. 14.

Voltage spectra of a three-level inverter with SPWM (m

1649

= 1:15).

Fig. 15. Voltage spectra of a three-level inverter with SVM and common-mode
= 1).
voltage cancellation (m

= 1).

Fig. 16. Voltage spectra of a three-level inverter with SPWM and

common-mode voltage cancellation (m
= 0:87).

For example, a reference voltage in sector I will be syntheand two of , which define the hexagon censized by
and two of the six vectors that detered at . Similarly,
could synthesize another reffine the hexagon centered at
erence voltage vector, which is located in sector II. In general,
any reference voltage within the boundary defined by the outer
, should be first allocated into
hexagon in coordinate,
one of the six smaller hexagons. For the voltage reference within
in refereach hexagon, it should be expressed as
ence frame and then synthesized using the same switching pattern and timing calculation as those for a two-level inverter. It
and
should be noted that, according to Figs. 2 and 3, both
have two states. When synthesizing a voltage in sector I, for
and state
of
are used and
example, both state
of
is used. However, when synthesizing a
only state
and state
voltage vector in sector II, both state
of
are used and only the state
of
is used. The reand
are never used.
dundant zero states

Fig. 4 shows the maximum obtainable voltages of the NPC

.
SVM in domain. The largest voltage vectors are
However, if a three-phase balanced voltage set is to be synthesized using the SVM scheme described above, the maximum
voltage vectors will be , the amplitude of which is the
same as that of a two-level SVM. Since the modulation index is
defined as
(2)
is the magnitude of the fundamental component of
where
the phase-to-neutral voltage, the maximum modulation index
with linear modulation is, therefore, [13]:
(3)
This control algorithm has resulted in significantly improved
output voltage waveforms compared with two-level SVM
inverters. However, using most of the 27 states or all the 19

1650

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 36, NO. 6, NOVEMBER/DECEMBER 2000

voltage vectors to synthesize the PWM output voltage inevitably

generates nonzero common-mode voltages. To eliminate the
common-mode voltage, only the above-mentioned seven vectors
out of 19 voltage vectors should be used to synthesize the
output voltage. Similar to the SVM for two-level PWM inverters,
the six nonzero vectors divide the plane into six sectors
as shown in Fig. 4. If, for instance, the reference vector sits in
and , the switching state of
the sector defined by vectors
the NPC inverter should be selected alternatively among those
corresponding to vectors , , and .
From the time-averaging principle, the time duration for each
state is determined by the following equation:

(4)
In the above equation, all vectors are constant and
therefore, the volt-second equation is obtained

,
(5)

Fig. 17. Multilevel inverter common-mode voltage with conventional SVM:

dc-link voltage = 750 V; f = 1:0 Hz; modulation index = 0:175.

and
, ,
can be calculated from the
Given
second equation. The time for zero state is given by
(6)
It should be pointed out that the maximum modulation index for
times that of the conventional
this modulation scheme is
two- level SVM according to Fig. 4. It can be verified from (3)
,
that the maximum modulation index in this case is
which is the same as that with SPWM for two-level inverters.
B. SPWM
SPWM has been widely used in conventional two-level
inverters due to its simplicity and low harmonic distortion characteristics. For similar reasons, this method has been extended
to multilevel inverter control. It has been suggested that
triangle carrier signals should be used for an -level inverter and
only one sinusoidalmodulation signal foreach phase [10], [11].
Fig. 5 shows the waveforms of sine-triangle intersection
(SPWM) and the resulting phase-to-neutral voltage for an NPC
inverter. Two carriers together with three modulation signals
have been used to obtain SPWM control (only one modulation
signal is shown). The intersection of the sinusoidal signal with
the upper triangle signal results in the positive PWM phase
voltage, whereas the intersection of the sinusoidal and the lower
triangle signals results in the negative PWM phase voltage.
AlthoughthisSPWMmethodprovideslowharmoniccontentin
the output voltages, it does not guarantee that the switching states
of the inverter are within those seven states which would result in
zero common-mode voltage. An alternative SPWM scheme can
be used which does not generate nonzero common-mode voltages. Similar to the SPWM for two-level inverters, this method
employs one triangle carrier signal and three balanced sinusoidal
,
, and
). At first, two of the
modulation signals (i.e.,
and
, are compared with
three modulation signals, e.g.,
the carrier signal resulting in two intermediate PWM signals
and for one phase (not shown). Then, subtraction of from
creates the PWM signal for the same phase, asshown in Fig. 6. The
same algorithmshould be applied to the other two phases.

Fig. 18. Multilevel inverter common-mode voltage with modified SVM:

dc-link voltage = 750 V; f = 1:0 Hz; modulation index = 0:175.

To summarize, we have the following equations:

(7)
Therefore, the common-mode voltage

is equated as

(8)
It is important to note that this SPWM scheme guarantees
that the switching happens only among those states with zero
common-mode voltage.

ZHANG et al.: MULTILEVEL INVERTER MODULATION SCHEMES

1651

III. SIMULATION RESULTS

The concept of common-mode voltage cancellation using
three-level inverters is proven by simulation in Matlab. Figs. 7
and 9 show the phase-to-neutral, the phase-to-phase, and the
common-mode voltages of a three-level inverter using both
conventional SPWM and SVM. The peak-to-peak value of
the common-mode voltage is as high as 1/3 of the dc-link
voltage. However, common-mode voltage cancellation using
the suggested SPWM and SVM is obtained, as shown in Figs. 8
and 10, respectively.
In addition, frequency spectra are obtained as a result of the
fast Fourier transform (FFT) on the output voltages with maximum fundamental component under linear modulation condition. Figs. 11 and 12 show the frequency spectra of the output
voltage of a two-level inverter using both SVM
and SPWM
, respectively. These results serve
as bases of comparison for the proposed modulation schemes.
The frequency spectra for a three-level inverter with both SVM
and SPWM are shown in Figs. 13 and 14, respectively. Compared to two-level inverters, three-level inverters with the established modulation schemes have significantly reduced harmonic
components while maintaining the same maximum modulation
indexes. Figs. 15 and 16 are voltage spectra of the proposed
three-level SVM and SPWM for common-mode voltage cancellation. Fig. 15 shows that the proposed three-level SVM with
common-mode voltage cancellation has the same modulation
index as that of SPWM without common-mode voltage cancel. However, the harmonic components of the
lation
output voltage are lower than those obtained from two-level inverters but higher than those from three-level inverters with conventional SPWM and SVM. On the other hand, the modulation
index of three-level SPWM with common-mode voltage cancel. The harmonic conlation is limited to
tent of its output voltage is close to that generated by three-level
inverters with SVM and common-mode voltage cancellation.

Fig. 19. Multilevel inverter line-to-line voltage with conventional SVM:

dc-link voltage = 750 V; f = 1:0 Hz; modulation index = 0:175 (only
the space vectors of the inner hexagon are used, resulting in a three-level
waveform).

IV. EXPERIMENTAL RESULTS

In order to investigate the validity of the proposed schemes
and their practical capabilities, experimental results were obtained by applying the proposed modified SVM approach to
a conventional multilevel (three level) inverter with a nominal
dc-link voltage of 750 V. The load was a 15-hp 150-r/min 460-V
5-Hz synchronous motor. For comparison purposes, the conventional SVM approach was also used with a switching frequency of 500 Hz. To apply the modified SVM scheme with
common-mode voltage cancellation to the conventional multilevel inverter hardware, an effective switching frequency of
1000 Hz was necessary, due to the available timer configuration. The experimental results of the conventional and modified
cases are shown in Figs. 1724. Figs. 17 and 21 show considerable common-mode voltage, with modulation indexes of 0.175
and 0.58, respectively. In comparison, Figs. 18 and 22 show significant common-mode voltage reduction, in agreement with the
simulation results considering the practical hardware and switch
constraints.
For conventional modulators operating with low modulation indexes, i.e., below 0.433, only the space vectors in the
inner hexagon (see Fig. 2) are used, resulting in a three-level
line-to-line waveform as shown in Fig. 19. For the modified

Fig. 20. Multilevel inverter line-to-line voltage with modified SVM: dc-link
voltage = 750 V; f = 1:0 Hz; modulation index = 0:175 (the space vectors
of the inner and outer hexagon are used, resulting in a five-level waveform).

SVM shown in Fig. 20 with a modulation index of 0.175, since

the states that generate common-mode voltage are not used,
space vectors from the outer hexagon are also used, resulting
in a five- level waveform. Figs. 23 and 24 show the line-to-line
voltages with modulation indexes of 0.58, for the conventional
and the modified SVM, respectively.
V. CONCLUSIONS
Common-mode voltage generated by conventional PWM inverters has been found to be a major cause of premature motor
bearing failures due to the resulting leakage currents through the
bearings. Similarly, the resulting current through the parasitic
capacitance between the motor windings and the frame adds to
the total leakage current through the ground conductor resulting

1652

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 36, NO. 6, NOVEMBER/DECEMBER 2000

Fig. 21. Multilevel inverter common-mode voltage with conventional SVM:

dc-link voltage = 750 V; f = 3:33 Hz; modulation index = 0:58.

Fig. 23. Multilevel inverter line-to-line voltage with conventional SVM:

dc-link voltage = 750 V; f = 3:33 Hz; modulation index = 0:58.

Fig. 22. Multilevel inverter common-mode voltage with modified SVM:

dc-link voltage = 750 V; f = 3:33 Hz; modulation index = 0:58.

Fig. 24. Multilevel inverter line-to-line voltage with modified SVM: dc-link
voltage = 750 V; f = 3:33 Hz; modulation index = 0:58.

in increased conducted EMI and false tripping of relays. It has

been proven experimentally in previous work that cancellation
of the common-mode voltage will eliminate the bearing currents
and reduce the conducted EMI significantly. In this paper, it is
shown through simulation and experimental results that multilevel PWM inverters with modified modulation schemes will
not generate common-mode voltages. Both SVM and sinusoidal
SPWM are analyzed based on three-level inverters. This concept
can be applied to both mediumvoltage (2300/4160 V) multilevel inverter applications as well as low-voltage applications to
eliminate the common-mode voltage and improve the reliability
of motor drive systems.

REFERENCES

ACKNOWLEDGMENT
The authors would like to thank GE Industrial Systems,
Salem, VA, for the use of the multilevel inverter hardware to
obtain the experimental results.

[1] A. von Jouanne, P. Enjeti, and W. Gray, Application issues for PWM
adjustable speed AC motor drives, IEEE Ind. Applicat. Mag., vol. 2, pp.
1018, Sept./Oct. 1996.
[2] J. M. Erdman, R. J. Kerkman, D. W. Schlegel, and G. L. Skibinski, Effect of PWM inverters on AC motor bearing currents and shaft voltages,
IEEE Trans. Ind. Applicat., vol. 32, pp. 250259, Mar./Apr. 1996.
[3] E. Zhong and T. A. Lipo, Improvements in EMC performance of
inverter-Fed motor drives, IEEE Trans. Ind. Applicat., vol. 31, pp.
12471256, Nov./Dec. 1995.
[4] A. von Jouanne and H. Zhang, A dual-bridge inverter approach to eliminating common mode voltages and bearing and leakage currents, IEEE
Trans. Power Electron., vol. 14, pp. 4348, Jan. 1999.
[5] H. Zhang and A. von Jouanne, Suppressing common-mode conducted
EMI generated by PWM drive systems using a dual-bridge inverter, in
Proc. IEEE APEC98, vol. 2, 1998, pp. 10171020.
[6] S. Ogasawara, H. Ayano, and H. Akagi, An active circuit for cancellation of common-mode voltage generated by a PWM inverter, in Proc.
IEEE PESC97, vol. 2, 1997, pp. 15471553.
[7] A. M. De Broe, A. L. Julian, and T. A. Lipo, Neutral-to-ground
voltage minimization in a PWM-rectifier/inverter configuration, in
Proc. PEVD96, 1996, pp. 564568.

ZHANG et al.: MULTILEVEL INVERTER MODULATION SCHEMES

[8] A. Nabea, I. Takahashi, and H. Akagi, A new neutral-point-clamped

PWM inverter, IEEE Trans. Ind. Applicat., vol. IA-17, pp. 518523,
Sept./Oct. 1981.
[9] S. Ogasawara and H. Akagi, A vector control system using a neutralpoint-clamped voltage source PWM inverter, in Conf. Rec. IEEE-IAS
Annu. Meeting, 1991, pp. 422427.
[10] G. Carrara, S. Gardella, M. Marchesoni, R. Salutari, and G. Sciutto, A
new multilevel PWM method: A theoretical analysis, in Proc. IEEE
PESC90, 1990, pp. 363371.
[11] G. Sinha and T. A. Lipo, A four-level rectifier-inverter system for drive
applications, IEEE Ind. Applicat. Mag., vol. 4, pp. 6674, Jan./Feb.
1998.
[12] P. M. Bagwat and V. R. Stefanovic, Generalized structure of a multilevel
PWM inverter, IEEE Trans. Ind. Applicat., vol. IA-19, pp. 10571069,
Nov./Dec. 1983.
[13] H. W. van Der Broeck, H. Skudelny, and G. V. Stanke, Analysis and
realization of a pulse width modulator based on voltage space vectors,
IEEE Trans. Ind. Applicat., vol. 24, pp. 142150, Jan./Feb. 1988.
[14] M. Marchesoni and M. Mazzucchelli, Multilevel converter for high
power ac drives: A review, in Proc. IEEE Int. Symp. Industrial Electronics, 1993, pp. 3843.
[15] J. S. Lai and F. Z. Peng, Multilevel convertersA new breed of power
converters, IEEE Trans. Ind. Applicat., vol. 32, pp. 509517, May/June
1996.
[16] B. Mwinyiwiwa, Z. Wolanski, and B. T. Ooi, Microprocessor implemented SPWM for multiconverters with phase-shifted triangle carriers,
in Conf. Rec. IEEE-IAS Annu. Meeting, 1997, pp. 15421549.
[17] L. M. Tolbert, F. Z. Peng, and T. G. Habetler, Multilevel converters for
large electric drives, IEEE Trans. Ind. Applicat., vol. 35, pp. 3644,
Jan./Feb. 1999.

1653

Shaoan Dai (S00) received the B.S. and M.S.

degrees from Harbin Institute of Technology,
Harbin, China, in 1987 and 1990, respectively. He
is currently working toward the Ph.D. degree in the
Department of Electrical and Computer Engineering,
Oregon State University, Corvallis.
He was an Assistant Professor and then an Associate Professor in the Department of Control Engineering, Harbin Institute of Technology, from 1990
to 1996 and from 1996 to 1999, respectively. His interests are focused on power electronics, adjustablespeed drives, and control engineering.

Haoran Zhang (S98M99) received the B.E.E.

degree from Tsinghua University, Beijing, China,
the M.E.E. degree from the Institute of Electrical
Engineering, Chinese Academy of Sciences, Beijing,
China, and the Ph.D. degree in electrical engineering
from Oregon State University, Corvallis, in 1985,
1988, and 1998, respectively.
From 1988 to 1995, he was an Assistant Professor
in the Department of Control Engineering, Harbin Institute of Technology, Harbin, China. He is currently
an IC Design Engineer with Texas Instruments Incorporated (formerly Burr-Brown Corporation), Tucson, AZ. His research interests
include power electronics, adjustable-speed drives, and power management integrated circuits.

Alan K. Wallace (M78SM84F00) received the

B.Eng. and Ph.D. degrees in electrical power engineering from the University of Sheffield, Sheffield,
U.K., in 1963 and 1966, respectively.
From 1966 to 1967, he was with Imperial Chemical Industries, working on the application of digital
computers to process control. In 1967, he joined the
University of Nottingham, Nottingham, U.K., where
taught electrical machine design and power system
analysis until 1974. From 1974 to 1984, he was engaged in design and development of propulsion systems in the mass transit industry in Canada. He worked with Spar Aerospace
of Toronto and Canadair Services and was Manager of Power Distribution for
the Urban Transportation Development Corporation, Kingston, ON, Canada.
In 1984, he joined the Department of Electrical and Computer Engineering,
Oregon State University, Corvallis, where he currently teaches and conducts
research. He is also the EPRI/OSU Director of the Motor Systems Resource Facility (MSRF). From 1991 to 1992, he was a Visiting Research Fellow at the
University of Cambridge, Cambridge, U.K. His interests are primarily in adjustable-speed drives, variable speed generation, linear motor applications to
transportation, and power electronic applications.
Dr. Wallace is a member of the Institution of Electrical Engineers, U.K., and
from 1988 to 1991, he was an Associate Editor of the IEEE TRANSACTIONS ON
POWER ELECTRONICS.

Annette von Jouanne (S94M95SM00)

received the B.S. and M.S. degrees in electrical
engineering with an emphasis in power systems
from Southern Illinois University, Carbondale, and
the Ph.D. degree in electrical engineering/power
electronics from Texas A&M University, College
Station, in 1990, 1992, and 1995, respectively.
While at Texas A&M University, she also worked
with Toshiba International Industrial Division
and International Power Machines on joint university/industry research. In 1995, she joined the
Department of Electrical and Computer Engineering, Oregon State University,
Corvallis, where she is currently an Associate Professor, working primarily
on power electronic converters, power quality, adjustable-speed drive (ASD)
ride-through, and investigating and mitigating the adverse effects of applying
ASDs to ac motors. She is also the Co-Director of the Motor Systems Resource
Facility (MSRF), an EPRI/OSU Center for motors and drives research and
testing.
Dr. von Jouanne received the 2000 IEEE Industry Applications Society
(IAS) Outstanding Young Member Award, the IAS Magazine Prize Paper
Award, and the National Science Foundation CAREER Award. Since 1997,
she has also served as an Associate Editor of the IEEE TRANSACTIONS ON
INDUSTRIAL ELECTRONICS. She is a Registered Professional Engineer in the
State of Washington.

Fei (Fred) Wang (S85M91SM99) received the

B.S. degree from Xian Jiaotong University, Xian,
China, and the M.S. and Ph.D. degrees from the University of Southern California, Los Angeles, in 1982,
1985, and 1990, respectively, all in electrical engineering.
He was a Research Scientist in the Electric Power
Laboratory, University of Southern California, from
1990 to 1992. He joined the GE Power Systems Engineering Department, Schenectady, NY, as an application engineer in 1992. From 1994 to 2000, he was
a Senior Development Engineer with GE Industrial Systems, Salem, VA. He is
currently Manager of the Electrical Systems Technologies Program at the GE
China Technology Center, Shanghai, China. His interests and responsibilities
are in the areas of power electronics, controls, electric machines, and motor
drives.