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Erode 638 153, Tamil Nadu, India.
Phone: 0424 2500073, Mail: selvaec@gmail.com
Mobile: 096553 21216. www.sseservices.in

SRI SELVAKUMARAN PROJECTS & PLACEMENTS DIVISION

This is a one type educational service to the third year ECE students for having their Analog and Digital
Communication lab experiments using only discrete components. We congratulate our esteemed
Professor S. Saravanan, Erode for providing all experiments details given here from his industrial experience.
This will facilitate the students knowledge in building the circuits by their own without firing the hand.

Expt No. 1
AMPLITUDE MODULATION AND DEMODULATION
Date:
AIM: To construct an amplitude modulation circuit and measure the Modulation Index. To recover the
modulating signal from the AM wave by using a Diode Detector circuit.
TE S T RI G S :
S.NO.

NAME

RANGE

QNTY

DSO

0 30 MHZ

FUNCTION GENERATORS

0 2 MHZ

VARIABLE POWER SUPPLY

0 30 V ( DUAL )

COMPONENTS:
S.NO.

NAME

PART NUMBER

QNTY

RESISTORS

33K, 39K, 47K, 68E, 68E, 100K, 1K

1 each

CAPACITORS

10uF, 0.01uF, 0.1uF

1, 2, 1 each

DIODE

OA79

BREAD BOARD

POTENTIOMETERS

100K

IC

CA3080

SRI SELVAKUMARAN EDUCATIONAL SERVICES

www.sseservices.in

Mobile: 096553 21216

THEORY:
Amplitude modulation (AM) is a method of impressing a message signal onto an alternating-current (AC)
carrier waveform. The highest frequency of the modulating data is normally less than 10 percent of the
carrier frequency. The instantaneous amplitude (overall signal power) varies depending on the
instantaneous amplitude of the modulating signal.
In AM, the carrier itself does not fluctuate in amplitude. Instead, the modulating signal appears in the form
of signal components at frequencies slightly higher and lower than that of the carrier. These components
are called sidebands. The lower sideband (LSB) appears at frequencies below the carrier frequency; the
upper sideband (USB) appears at frequencies above the carrier frequency. The LSB and USB are
essentially "mirror images" of each other in a graph of signal amplitude versus frequency. The sideband
power accounts for the variations in the overall amplitude of the signal.
An Amplitude Modulated Signal is represented as follows.
Vam(t) = [ Ec + EmSin(2fmt) ] [ Sin(2fct) ]
Where Ec + EmSin(2fmt) is the Amplitude Modulated Wave
Em is the peak change in the amplitude of the Envelope ( volts )
fm is the frequency of the modulating signal.
PURPOSE:
This experiment demonstrates the principle of Multiplier operation using the CA3080 Operational
Transconductance Amplifier. A simple demodulator demonstrates one method of recovering an amplitude
modulated signal using a diode detector known as envelope detector. The modulation index m is
calculated that indicates by how much the modulated variable varies around its unmodulated level. It
relates to the variations in the amplitude of the carrier signal. The value of m is within the range of 1.

PINOUT DI AGRAM OF CA3080:

PINOUT DI AGRAM OF OA79 (germanium diode)

MODULATOR:
+9V
R7
100K Of f set Null
R2
47K

+9V

-9V
Carrier
Signal

R1

54

33K

AM Out

R4
68E

R3
68E

R6
100K

R5
39K

-9V
Modulating Signal
0

DEMODULATOR:

AM In

D1

R8

C3

Message Out

0.1uF
OA79

1K
C1
0.01uF

C2
0.01uF

If you have any feedback and suggestions for the betterment of our services, please mail the same at our
Email ID:selvaec@gmail.com

MODULATION GRAPH:

PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

Connections are made for the AM Modulator and Demodulator as shown in the circuit diagrams.
Frequency of the input carrier is fixed at constant amplitude of 1 volt and 150 KHz.
A message signal of 1 KHz at 0.5 volt amplitude is applied at the modulating signal input.
The Vmax and Vmin are measured and tabulated to calculate the Modulation Index m
The amplitude of the message signal is varied in steps till the Vmin reaches the minimum.
The same set of amplitude values are used for two or three modulating frequencies and values
tabulated.
The maximum value of m is observed to be 1.
The demodulated message signal is observed from the output of the Envelope Detector and
tabulated in the demodulator side of the tabulation..
A selection of RC network is important for a faithful recovery of the message signal.
All optimum parameters like Vcc are noted down.

TABULAR COLUMN:
Vc = 150 KHz @ 1 Volt Amplitude

S.No.
Fm

Modulator
Side
Vm
Vmax
0.5

1 KHz

1
1.5
2

Demod Side
Vmin

Fo

Vo

0.5
2

2 KHz

1
1.5
2
0.5

3 KHz

1
1.5
2

REFERENCES:
1.
2.
3.
4.
5.
6.

CA3080/CA3080A DATASHEET.
OA79 DATASHEET.
Understanding and Using OTA Op-Amp Ics ( Nuts and Volts Magazine )
Electronic Communications Systems V Edition by Wayne Tomasi Pearson Education.
Communication Lab Manual ECE Department SSIT, Tumkur
Communication Lab Manual ECE Department Easwari Engg College, Chennai.

RESULT: Thus the modulation Index of an Amplitude Modulation Circuit was calculated and the
message signal was recovered using an Envelope Detector.

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(M.E / M.Tech, M.B.A &
M.C.A)

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M.B.A & M.C.A) courses, College address and phone number.

Price: Rs. 250.00

For copies contact: Selvakumaran @ 096553 21216.

Expt No. 2
FREQUENCY MODULATION AND FSK GENERATION
Date:
AIM: To construct a Frequency Modulation circuit using a sinusoidal input waveform and to measure the
Modulation Index. To use the same circuit for FSK generation with a square waveform.
TE S T RI G S :
S.NO.

NAME

RANGE

QNTY

DSO

0 30 MHZ

FUNCTION GENERATOR

0 2 MHZ

VARIABLE POWER SUPPLY

0 30 V ( DUAL )

COMPONENTS:
S.NO.

NAME

PART NUMBER

QNTY

RESISTORS

1.5K, 5.6K, 10K

1 EACH

CAPACITORS

1 nF

INTEGRATED CIRCUIT

NE/SE566D

BREAD BOARD

THEORY:
FREQUENCY MODULATI ON:
Frequency modulation (FM) is a method of impressing data onto an alternating-current (AC) wave
by varying the instantaneous frequency of the wave. This scheme can be used with analog or digital data.
In analog FM, the frequency of the AC signal wave, also called the carrier, varies in a continuous
manner. Thus, there are infinitely many possible carrier frequencies. In narrowband FM, commonly used
in two-way wireless communications, the instantaneous carrier frequency varies by up to 5 kilohertz (kHz,
where 1 kHz = 1000 hertz or alternating cycles per second) above and below the frequency of the carrier
with no modulation.
In wideband FM, used in wireless broadcasting, the instantaneous frequency varies by up to
several megahertz (MHz, where 1 MHz = 1,000,000 Hz). When the instantaneous input wave has positive
polarity, the carrier frequency shifts in one direction and when the instantaneous input wave has negative
polarity, the carrier frequency shifts in the opposite direction. At every instant in time, the extent of carrierfrequency shift (the deviation) is directly proportional to the extent to which the signal amplitude is positive
or negative.

In digital FM, the carrier frequency shifts abruptly, rather than varying continuously. The number
of possible carrier frequency states is usually a power of 2. If there are only two possible frequency
states, the mode is called frequency-shift keying (FSK). In more complex modes, there can be four, eight,
or more different frequency states. Each specific carrier frequency represents a specific digital input data
state. Frequency Modulation is widely used in communication systems. The most well known use is in
FM broadcasting. Digital FM is used in modems and multi tone selective signaling systems.
The general definition of frequency modulated signal SFM(t) is given by the formula:

S FM ( t
)

A C cos( 2 f C t

( t ))

A C cos( 2 f C t

2 K

m(

)d )

where,

m( )
AC

is the modulating signal.

is the amplitude of the carrier.
is the carrier frequency.

fC
Kf

is the frequency deviation constant measured in Hz/V.

FREQUENCY SHIFT KEYING:

Frequency-shift keying (FSK) is a frequency modulation scheme in which digital information is
transmitted through discrete frequency changes of a carrier wave. The simplest FSK is binary FSK
(BFSK). BFSK literally implies using a pair of discrete frequencies to transmit binary (0s and 1s)
information. With this scheme, the "1" is called the mark frequency and the "0" is called the space
frequency. The time domain of an FSK modulated carrier is illustrated in the waveforms.
PURPOSE:
This experiment demonstrates some of the principles of VCO operation using the NE566
integrated circuit by implementing a Frequency Modulation Circuit. The modulation index h is calculated
that indicates by how much the modulated variable varies around its unmodulated level. It relates to the
variations in the frequency of the carrier signal.
h = f/Fm where f is the frequency deviation and Fm is the modulating frequency.
An FSK signal is generated by replacing the sine wave input with a square wave. The MARK and
SPACE frequencies are observed for 2 KHz signal.
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off marks & rank for all above courses, College address and phone number.

Price: Rs. 280.00

PINOUT DI AGRAM OF NE566:

Figure 1
C I R C U I T DI AG R AM S :
FM & FSK MODULATOR:
12 V+
R2
1. 5K
C3

C2

TRIANGLE WAV E OUTPUT

U1A

R1

0. 001UF
6

0.01UF

R1
?

V+

M ODULATING SIGNAL
INPUT

VCC

OUT

TRI OUT
NE556

C1
7

R3

SQUARE WAV E OUTPUT

?
C1
1

10K

GND

SQ OUT

Figure 2
The NE/SE566 Function Generator is a general purpose voltage-controlled oscillator designed for
highly linear frequency modulation. The circuit provides simultaneous square wave and triangle wave
outputs at frequencies up to 1MHz. A typical connection diagram is shown in Figure 2. The control
terminal (Pin 5) must be biased externally with a voltage (Vc) in the range
V+ Vc V+
where VCC is the total supply voltage. In Figure 2, the control voltage is set by the voltage divider
formed with R2 and R3. The modulating signal is then AC coupled with the capacitor C2. The modulating
signal can be direct coupled as well, if the appropriate DC bias voltage is applied to the control terminal.
The frequency is given approximately by

fo
=

and R1 should be in the range 2k< R1<20k. A small capacitor (typically 0.001uF) should be connected
between Pins 5 and 6 to eliminate possible oscillation in the control current source. The value of C1 is
1nF.
WAVEFORMS:
FREQUENCY MODULATI ON:

FREQUENCY SHIFT KEYING

PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
9.

Connections are made as per the circuit

diagram of Figure 2
Without applying the modulating signal,
measure the carrier frequency Fc at the
output of NE566.
Apply a modulating signal Fm of 1 KHz to
NE566 and observe the FM wave.
Note down the change in the frequency of
the waveform =Fc ~ fFM
Vary the modulating frequency upto 5 KHz
and tabulate the readings.
Calculate the modulation Index h = /Fm
Calculate the BW = 2 ( Fm + )
To generate an FSK waveform, the input
frequency of 2 KHz should be a square
wave.
The MARK and SPACE frequency are
tabulated.

TABULATION FOR FM:

S.No.

Modulating
Signal Fm

1 KHz

2 KHz

3 KHz

4 KHz

5 KHz

Frequency
Modulation f FM

Frequency
deviation =Fc ~ f FM

Modulation
Index h=/Fm

BW =
2 ( Fm + )

TABULATION FOR FSK:

Signal

Amplitude(V)

Time period(sec)

Modulating signal
Carrier signal
Mark Frequency
Space Frequency

Result: Thus an FM and FSK modulation signal were generated and the properties were tabulated.
Sri Selvakumaran Institution Excellence (SSIE) is the one unique academy offering
consultancy service to the poor performing Engineering and Polytechnic institutions across
the nation. We are delivering many consulting activities for improving institution quality
through
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boards such as ISO, NBA, NAAC, UGC act (2F & 12B) &
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agencies.

Our service network offers the following supports to the

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3. National Assessment and Accreditation Council (NAAC)
4. UGC act 2F & 12B Status
5. Institution Autonomous and Funding Schemes

Expt No. 3
BALANCED MODULATOR
Date:
AIM: To construct a Balanced Modulator and note down its working principle.
TE S T RI G S :
S.NO.

NAME

RANGE

QNTY

DSO

0 25 MHZ

FUNCTION GENERATOR

0 2 MHZ

VARIABLE POWER SUPPLY

0 30 V ( DUAL )

COMPONENTS:
S.NO.

NAME

PART NUMBER

QNTY

RESISTORS

100K

CAPACITOR

220pF

DIODES

IN4148

BREAD BOARD

INDUCTOR

1
Decade Inductance
Box

THEORY:
A Balanced Modulator generates a DSB signal. The inputs to a balanced modulator are the carrier and a
modulating signal. The output is the upper and lower sidebands. A balanced modulator suppresses the
carrier, leaving only the sum and the difference frequencies at the output. The output of a balanced
modulator can be further processed by filters or phase-shifting circuitry to eliminate one of the sidebands,
thereby resulting in an SSB signal. One of the most popular and widely used balanced modulator is the
diode ring or lattice modulator illustrated in figure 1. Figure 1.

D4
D1N4148

D1
D1N4148

T1
1

5 T2
6

Modulating
Signal

6
4

DSB Output
4

TR ANSFORMER CT

D3

D2

TRANSFORMER CT

D1N4148
D1N4148

V1

Carrier Signal

It consists of an input transformer T1, an output transformer T2, and four diodes connected in a
bridge configuration. The carrier signal is applied to the center taps of the input and output transformers.
The modulating signal is applied to the input transformer T1. The output appears across the secondary of
the output transformer T2.
The carrier sine wave, which is usually considerably higher frequency and amplitude than the
modulating signal is used as a source of forward and reverse bias for the diodes. The carrier turns the
diodes off and on at a high rate of speed. The diodes act like switches which connect the modulating
signal at the secondary of T1 to the primary of T2.
The greatest carrier suppression will occur when the diode characteristics are perfectly matched.
A carrier suppression of 40 dB is achievable with well-balanced components.

100k

100k
D1
V1
Modulating Signal

DSB Output

D3

D1N4148
V1

D2
D1N4148

1.

Connections are

D1N4148
L1
2.2mH

Carrier Signal

3.
4.
5.
6.
7.

CIRCUIT DIAGRAM:
Figure 2.

R2

R1

D4
D1N4148

made as shown in
figure 2.

C1
220pF

2.

A carrier wave of
200KHz at 1 volt
pp amplitude and a
message signal of

1 KHz at less than 1 Volt pp are applied as shown in the circuit diagram.
The output waveform is noted to have a suppressed carrier.
The output frequency of the carrier is noted and tabulated as shown.
The carrier frequency is varied and the inductance value is tuned to have maximum amplitude.
All the parameters are tabulated for fc = 150 KHz and 100 KHz.

T A B U L A T I ON :
Carrier
Frequency fc

Modulating
Frequency fm

Amplitude of
fm

200 KHz

1 KHz

0.5 V

150 KHz

1 KHz

0.5 V

100 Khz

1 KHz

0.5 V

S.No.

Output Carrier
Frequency Fo

RESULT: Thus a simple balanced modulator is built to understand its working principle.
REFERENCE:
1.
2.

COMMUNICATION LABORATORY MANUAL, UNIVERSITY OF FLORIDA

DIGITAL AND ANALOG COMMUNICATION SYSTEMS, Leon W. Couch

Vo

Expt No. 4
PRE-EMPHASIS & DE-EMPHASIS
Date:
AIM: To design a Pre-Emphasis and De-Emphasis circuit for a desired roll-over frequency and compare
the practical output with theoritical calculations.
TE S T RI G S :
S.NO.

NAME

RANGE

QNTY

DSO

0 30 MHZ

FUNCTION GENERATOR

0 2 MHZ

VARIABLE POWER SUPPLY

0 30 V ( DUAL )

S.NO.

NAME

PART NUMBER

QNTY

RESISTORS

100E, 820E, 2.2K, 15K

1 each

CAPACITORS

100nF

INTEGRATED CIRCUIT

LM741

BREAD BOARD

COMPONENTS:

THEORY:
When an FM system is compared to an AM system with a modulation index of 1 operating under
similar noise conditions, then it can be shown that the FM signal has a signal to noise ratio which is 3m2
better than the AM system. m here is the modulation index or deviation ratio for the FM signal.

In an FM system the
higher
frequencies
contribute
more to the noise than the lower
frequencies. Because of this all
FM systems adopt a system of
pre-emphasis where the higher
frequencies are increased in
amplitude before being used to
modulate the carrier.
The
transfer
function
sketched above is used for a pre-

emphasis circuit for FM signals in the FM band. The Time T = 75s. For FM systems in the FM band m ~
5 resulting in a S/N improvement of 19dB. With pre-emphasis this can be increased by 4dB for a total of
23dB.

At the receiver the higher frequencies must be deemphasized in order to get back the original baseband signal.
The transfer function of the de-emphasis circuit is shown
above.

PURPOSE:
This experiment demonstrates the use of Pre-Emphasis and De-Emphasis circuits in FM
Transmitters and Receivers respectively as discussed in the Theory part of this experiment. A separate
circuit and its design are used to build the circuits and to observe their performances.
The Frequencies F1 and F2 are selected according to the desired levels of frequency response at
the source and the destination. Usually the values of 100 Hz and 20 KHz are selected as the Audio
spectrum and the boost and cut frequencies are used in the design.
PINOUT DI AGRAM OF LM741:

CIRCUIT DIAGRAMS: PRE-EMPHASI S:

R1

Rf

Figure 1 DESIGN:

U1
2

$PIN 6

LM741

5
6

OS1

Vo

F1 = 1/(2rC) and F2 = 1/(2RC)

Choose C = 100nF, then r = 820E and R = 100E

Given: F1 = 2.1 KHz and F2 = 15 KHz

OU T
V-

7
V+

+V cc

1Vac
0Vdc

Vi

-V cc

Also r/R = Rf/R1, then R1 = 2.2K and Rf = 15K

TABULAR COLUMN:

Input Vi = 500
mV
Output
S.No Frequen Vo
.
cy
1
100
2

250

500

1k

2.5k

Gain = 20 Log
V0/Vi

DE-EMPH ASIS:
R1

Rf

Figure 2 DESIGN:

+V cc

Fc = 1/(2RdCd)
Choose Cd = 100nF and Fc = F1 = 2.1 KHz

V+
Rd

OUT

OS1

3 LM741

V-

Vi

$PIN6

Vo

Then Rd = 820E

Also r/R = Rf/R1, then R1 = 2.2K and Rf =

1Vac
0Vdc

U1

-V cc

15K

TABULAR COLUMN:

Input Vi = 500
mV
S.No Frequen Output
.
cy
Vo
1
100
2

250

500

1k

2.5k

Gain = 20 Log
V0/Vi

PROCEDURE:
1.
2.
3.
4.
5.
6.
7.

The values of the Resistors and the Capacitors are calculated using the design formulas for lower
cut-off frequency F1 and Upper cut-off frequency F2 for Pre-Emphasis circuit.
Similarly the cut-off frequency F1 for De-Emphasis circuit is used to arrive at the values of the
passive components.
Connections are made as shown in the figures of Pre-Emphasis and De-Emphasis circuits.
A minimum of 500 mV is applied as Vi to the inputs.
The frequency is varied in steps throughout the audio range and the corresponding readings are
tabulated.
The gain is calculated as shown in the Tabular Columns.
A graph of Frequency versus Output Voltage is drawn on a Semi-Log Graph Sheet.

GR A P H S :
The Graphs for both the circuits will resemble as shown in the theory part.
REFERENCES:
1.
2.
3.
4.

LM741 DATASHEET
Electronic Communications Systems V Edition by Wayne Tomasi Pearson Education.
Communication Lab Manual ECE Department SSIT, Tumkur
Communication Lab Manual ECE Department Easwari Engg College, Chennai.

RESULT: Thus a circuit to improve the frequency response of FM receivers was studied using PreEmphasis and De-Emphasis.

Students Industrial Projects

As per various Universities regulation - Students in final year have to select an industrial project in the
respective industry where they will understand the industry problem and then solve it in an utmost
manner for that industry. Thus we are providing this oppurtunity to the studetns by training them and then
giving them industrial projects.
There is a range of opportunities for companies to become involved in the work through student projects
for its education programmes. The host company benefits from the input of a very high caliber student or
team of students and will receive a report and presentation on the project at its completion.
All project opportunities are undertaken as part of taught academic courses delivered by the Institute
which is part of the University. The projects make valuable contributions to the learning of students
undertaking UG studies. Students will typically undertake the project at a company location, which

for practical purposes.

IEEE Projects for ECE, EEE, and E&I Students
IEEE Projects for CSE & IT Students

Expt No. 5
PHASE LOCKED LOOP AND APPLICATIONS
Date:

AIM: To construct a Phase Locked Loop and to observe the locking frequency range.
TE S T RI G S :
S.NO.

NAME

RANGE

QNTY

DSO

0 30 MHZ

FUNCTION GENERATOR

0 2 MHZ

VARIABLE POWER SUPPLY

0 30 V ( DUAL )

Sri Selvakumaran Institution Excellence

Sri Selvakumaran Institution Excellence(SSIE) is offering consultancy service to

the poor performing Engineering and Polytechnic institutions across the nation.
We are delivering many consulting activities for improving their institution quality
through many accreditation boards such as ISO, NBA and NAAC and guide them
for getting financial support from the various funding agencies.
Ne w
Process

Accreditation

The National Board of Accreditation, New Delhi has revised its process of accreditation system with
its new format version 3.0, May 2011. In order to complete new system, students, faculty members
and management people are have to know and implement the new NBA process for three academic
years.
We are offering many services such as
1. One day seminar,
2. Making application for NBA,
3. Guidance for preparing three years NBA files,
4. Setting up various institution and department development cell,
5. Assist for students placement and higher education,
6. Assist for improving students admission quality,
7. Guidance for getting financial grant,
8. Defining Program Educational Objectives (PEOs).

Expt No. 6
PWM GENERATION AND DETECTION
Date:
AIM: To generate a Pulse Width Modulation signal for a sinusoidal message signal and to compare the
detected message signal with the input signal.
TE S T RI G S :
S.NO.

NAME

RANGE

QNTY

DSO

20 MSPS

FUNCTION GENERATOR

0 2 MHZ

VARIABLE POWER SUPPLY

0 30 V ( DUAL )

COMPONENTS:
S.NO.

NAME

PART NUMBER

QNTY

RESISTORS

1.5K, 10K,1K

2,1,1

CAPACITORS

100nF, 10nF, 1.5uF

1,1,2

BREAD BOARD

IC

LM741

POTENTIOMETER

100K

THEORY:
Pulse-width modulation (PWM) is a digital modulation technique, which converts an analog signal
into a digital signal for transmission. The modulator converts an audio signal (the amplitude-varying
signal) into a sequence of pulses having a constant frequency and amplitude, but the width of each
pulse is proportional to the Amplitude of the audio signal.
In this experiment, a square-wave generator or a monostable multivibrator can be used to generate the
PWM signal, whose output pulse width is determined by the values of R4, C3, and Vin(+). The LM741
operational amplifier acts as a voltage comparator.
The reference voltage at Vin(+) input (pin 3) is determined by the resistor values of R3 and R5. The
combination of R4 and C3 provides the path for charging and discharging. When no audio signal is
applied, the dc reference voltage at Vin(+) input can be changed by adjusting the R5 value.
If dc level of R5 is fixed and an audio signal is applied to the audio input, the audio signal is added to the
fixed dc level and the reference voltage will be changed with the change of audio amplitude. The resulting
PWM signal presents at the output of the comparator.

PIN DIAGR AM OF LM741:

C I R C U I T DI AG R AM S :
PULSE WIDTH MODULATION CIRCUIT:
+12V

U1
3

100K

OS2

OUT

OS1

V+

V-

C4

R5

R3
1k

PWM Output

100nF
LM741

R4
4

1KHz Sine Wave

10k

-12V

C3
10nF

Figure 1
DEMODULATION CIRCUIT:
R1
1.5k

PWM Input

R2
C2

1.5k

1uF

C1
1uF

Modulating
Signal

Figure 2

If you have any feedback and suggestions for the betterment of our services, please mail the
same at our E-mail ID:selvaec@gmail.com

MODULATION GRAPH:

PROCEDURE:
1.

The Circuit of Figure 1 and 2 are connected and cascaded to form a PWM Modulator and
Demodulator.

2.

A 1 KHz Sine Wave with an amplitude of 1 Volt is applied to the input. The non-inverting input is
adjusted to have a zero DC bias by varying the 100K potentiometer R5 to have a 50% duty cycle.

3.

The output PWM is noted for its ON time and OFF time and tabulated.

4.

If the amplitude of the input signal generates a fairly good PWM, then the amplitude is fixed and
the values are tabulated for different frequency inputs.

5.

The corresponding demodulated sine wave is verified.

TABULAR COLUMN:
PWM
S.No.

INPUT FREQUENCY ( KHz )

AMPLITUDE (Vin)
T ON

1 KHz

2 KHz

3 KHz

4 KHz

5 KHz

6 KHz

OFF

RESULT:
Thus a Pulse Width Modulation signal for a sinusoidal message signal was generated and the detected
message signal was compared with the input signal.

Expt No. 7
AGC CHARACTERISTICS
Date:
AIM: To study the principle of an Automatic Gain Control circuit and its performance characteristics.
TE S T RI G S :
S.NO.

NAME

RANGE

QNTY

DSO

100 MSPS

FUNCTION GENERATOR

0 2 MHZ

VARIABLE POWER SUPPLY

0 30 V ( DUAL )

S.NO.

NAME

PART NUMBER

QNTY

RESISTORS

470E, 1K, 10K, 33K, 120K, 240K, 100K

1 each, 240K 2

CAPACITORS

10uF

TRANSISTOR

J176, 2N3904

BREAD BOARD

POTENTIOMETERS

10K

INTEGRATED CIRCUIT

LM358

COMPONENTS:

3
1 each
1

THEORY:
Automatic gain control (AGC) is an adaptive system found in many electronic devices. The
average output signal level is fed back to adjust the gain to an appropriate level for a range of input signal
levels. For example, without AGC the sound emitted from an AM radio receiver would vary to an extreme
extent from a weak to a strong signal; the AGC effectively reduces the volume if the signal is strong and
raises it when it is weaker.
AGC algorithms often use a PID controller where the P term is driven by the error between
expected and actual output amplitude. Automatic Gain Control or AGC is a circuit design which maintains
the same level of amplification for sound or radio frequency. If the signal is too low the AGC circuit will
increase (amplify) the level and if it is too high, will lower it to maintain a constant level as possible.

The Automatic Gain Control principle is widely used in AM receivers and sometimes AGC is
called a compressor-expander.

HOW IT WORKS?:
Using the circuit presented here, we can construct a very inexpensive AGC amplifier with the
following features: a dynamic range greater than 50 dB; negligible distortion to the output waveform; fast
attack and slow decay; an adjustable output level from 0 to 1.2 V p-p; operation from a single 5-V supply;
less than 1-mA current drain; and low cost.
Referring to the circuit diagram, J1 (a Pchannel JFET), coupled with R2 and the equivalent
resistance of R3 and R4, form a voltage divider to the input signal source. With input levels below 40 mV
p-p, the input is evenly divided between R2 (120k) and R3 R4 (120k). The output amplitude of U1A isnt
large enough to turn on J1, which acts as a positive peak detector. The gate of the JFET is pulled to +5 V,
pinching its channel off and creating a very high resistance from drain to source. This essentially removes
it from the circuit.
At input levels above 40 mV p-p, Q1 is turned on at the positive peaks of the output of U1A,
lowering the JFETs gate to source voltage. The channel resistance decreases and attenuates the input
signal to maintain the output of U1A at approximately 1.2 V p-p.
The circuit, as shown, was tested with a sine-wave input ranging from 300 Hz to 30 kHz at 40 mV
to 20 V p-p, a 54-dB range. It maintained the output level at 1.2 V p-p, 0.5 dB, with no visible distortion
when comparing it with the input waveform. With a 40 mV to 20 V p-p input signals, the amplitude of the
signal across the JFET (VDS) measured less than 20 mV p-p.
Other JFETs with VGS(OFF) of 5V or under, such as the 2N5019 or 2N5116, should work equally
well in this circuit, although they havent been tried. To use JFETs with higher VGS(OFF), such as the
2N3993 (it was tried and worked equally well), increase the supply voltage to 12 V.
PURPOSE:
The use of AGC circuits in radio receivers have now being integrated into the monolithic receiver
ICs. Hence this simple to implement design technique is studied which can be used in any other circuit
where constant amplitude output is necessary.
PIN DIAGR AM OF LM358:

PIN DIAGR AM OF J176:

PIN DIAGR AM OF 2N3904:

CIRCUIT DIAGRAM:
C2
10uF

R5
470

R6
33k

5v
2

0
4
V-

R3
240k

C1

LM358

U1A

Audio Input

R2

5v

R7
10k

10uF

120k

0-20v @ 1KHz

OUT

V+

R4
240k

R1
1k

R8

100k

5v

0
C3
10uF

J1
J176

Q1
2N3904

C4
10uF

P1
10k

Audio Output
0-1.2v

PROCEDURE:
1. Connections are made for the AGC circuit as shown in the circuit diagram.
2. The frequency of audio input signal is fixed at constant frequency of 1 KHz.
3. The Amplitude of the input is made to vary in steps from 1 Volt.
4. The output is noted to be constant at 1.2 Volts irrespective of the input amplitude increment in steps
5. The input versus the output amplitude is tabulated as given below.

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T A B U L A T I ON :

Input Frequency = 1
KHz

S.No
.

Input
Amplitu
de Vi

Output
Amplitu
de Vo

Less
than
1.2V
1.2

1.2

1.2

1.2

1.2

1.2

1.2

1.2

10

10

1.2

REFERENCES:
1.
2.
3.
4.

DATASHEETS OF LM358, J176, 2N3904.

Electronic Communications Systems V Edition by Wayne Tomasi Pearson Education.
ECE1352 Analog Integrated Circuits I, University of Toronto.
http://electronicdesign.com/article/analog-and-mixed-signal/effective-agc-amplifier-can-be-built-ata-nominal-.aspx

RESULT: Thus an automatic gain control circuit was rigged up and its performance characteristics was
studied.

Expt No. 8
FM DETECTOR
Date:
AIM: To demodulate an FM signal using a PLL FM Demodulator.
TE S T RI G S :
S.NO.

NAME

RANGE

QNTY

DSO

0 25 MHZ

DUAL DIGITAL SYNTHESIZER FUNCTION GENERATOR

0 2 MHZ

VARIABLE POWER SUPPLY

0 30 V ( DUAL )

COMPONENTS:
S.NO.

NAME

PART NUMBER

QNTY

RESISTORS

680E, 2.2K

1 each

CAPACITORS

1uF, 1nF, 10nF, 750pF

1 each

INTEGRATED CIRCUITS

NE565

1 each

BREAD BOARD

POTENTIOMETERS

1
10K

THEORY:
There are a number of circuits that can be used to demodulate FM. Each type has its own
advantages and disadvantages, some being used when receivers used discrete components and others
now that ICs are widely used.
Below is a list of some of the main types of FM demodulator or FM detector. In view of the
widespread use of FM, even with the competition from digital modes that are widely used today, FM
demodulators are needed in many new designs of electronics equipment.
Slope FM detector
Foster-Seeley FM detector
Ratio detector
PLL, Phase locked loop FM demodulator
Quadrature FM demodulator
Coincidence FM demodulator
Each of these different types of FM detector or demodulator has its own advantages and
disadvantages.

Phase locked loop, PLL FM demodulator or detector is a form of FM demodulator that has gained
widespread acceptance in recent years. PLL FM detectors can easily be made from the variety of phase
locked loop integrated circuits that are available, and as a result, PLL FM demodulators are found in
many types of radio equipment ranging from broadcast receivers to high performance communications
equipments.
The way in which a PLL FM demodulator operates is quite straightforward. The loop consists of a
phase detector into which the incoming signal is passed, along with the output from the voltage controlled
oscillator (VCO) contained within the phase locked loop. The output from the phase detector is passed
into a loop filter and then used as the control voltage for the VCO.

Phase locked loop (PLL) FM demodulator

With no modulation applied and the carrier in the centre position of the pass-band the voltage on
the tune line to the VCO is set to the mid position. However if the carrier deviates in frequency, the loop
will try to keep the loop in lock. For this to happen, the VCO frequency must follow the incoming signal,
and in turn for this to occur the tune line voltage must vary. Monitoring the tune line shows that the
variation in voltage corresponds to the modulation applied to the signal. By amplifying the variations in
voltage on the tune line it is possible to generate the demodulated signal.
PLL FM demodulator performance
The PLL FM demodulator is normally considered a relatively high performance form of FM demodulator or
detector. Accordingly they are used in many FM receiver applications.
The PLL FM demodulator has a number of key advantages:
Linearity:
The linearity of the PLL FM demodulator is governed by the voltage to frequency
characteristic of the VCO within the PLL. As the frequency deviation of the incoming signal
normally only swings over a small portion of the PLL bandwidth, and the characteristic of the VCO
can be made relatively linear, the distortion levels from phase locked loop demodulators are
normally very low. Distortion levels are typically a tenth of a percent.
Manufacturing costs: The PLL FM demodulator lends itself to integrated circuit technology.
Only a few external components are required, and in some instances it may not be necessary to
use an inductor as part of the resonant circuit for the VCO. These facts make the PLL FM
demodulator particularly attractive for modern applications.
PLL FM demodulator design considerations
When designing a PLL system for use as an FM demodulator, one of the key considerations is the loop
filter. This must be chosen to be sufficiently wide that it is able to follow the anticipated variations of the
frequency modulated signal. Accordingly the loop response time should be short when compared to the
anticipated shortest time scale of the variations of the signal being demodulated.

A further design consideration is the linearity of the VCO. This should be designed for the voltage to
frequency curve to be as linear as possible over the signal range that will be encountered, i.e. the centre
frequency plus and minus the maximum deviation anticipated.
In general the PLL VCO linearity is not a major problem for average systems, but some attention may be
required to ensure the linearity is sufficiently good for hi-fi systems.
DEMODULATOR using NE/SE565 :
Pin Description of NE565:
Figure 1.
NE565 as FM Detector:
The 565 Phase-Locked Loop is a general purpose circuit
designed for highly linear FM demodulation. During Lock,
the average DC level of the phase comparator output signal
is directly proportional to the frequency of the input signal.
As the input frequency shifts, it is this output which causes
the VCO to shift its frequency to match that of the input.
Consequently, the linearity of the phase comparator output with frequency is determined by the voltageto-frequency transfer function of the VCO. Because of its unique and highly linear VCO, the 565 PLL can
lock to and track an input signal over a very wide bandwidth with high linearity. A typical connection is
shown in figure 4. The VCO free-running frequency is given approximately by
and should be adjusted to be at the center of the input signal frequency
range. C1 can be any value from 220pF to 750pF, but R1 should be within the range of 2000 to 20000
ohms with an optimum value of the order of 4000 ohms. A small capacitance should be connected to Pin
7 and 8 to eliminate possible oscillation in the control current source.
MODEL GRAPH:
Modulating Signal

Carrier Signal

FM Signal

Demodulated Signal

Figure 2.

CIRCUIT DIAGRAM:
+V cc
10K
R3
R1

C2

2.2k

1n

VOUT

VCON

REF

M e s s age Out

VIN
T CAP

LM565

IN2

-VCC

IN

+VCC

3
R2
680E

T RES

2
1uF

FM Input

C3
10n

10

U1
C1

C4
750pF

Figure 3.

-V cc

PROCEDURE:
1.
2.
3.
4.
5.
6.
7.

Connections are made as shown in figure 3 using the PLL IC NE565.

With the absence of the input FM signal, the output at pin 4-5 should be a square wave.
Adjust the square wave to have an output frequency of 100 KHz by adjusting the 10K POT.
An FM signal is generated with the following settings Fo=100KHz, Fm=1KHz, Fd=10KHz or
more and less than 30 KHz, Wave=Sine and Amplitude=500mV using a Dual Digital
Synthesizer Function Generator. This is the input signal to the demodulator.
The output is a demodulated waveform of 1KHz.
Decreasing or increasing the frequency deviation results in a distorted output.
The frequency of FM carrier signal is varied and tabulated.

T A B U L A T I ON :

S.No Fo KHz Fm
Fd KHz VFM
Vo in
.
KHz
KHz
1
75
1
20 100 mV
2

100

20 101 mV

125

20 102 mV

RESULT: Thus an FM detector circuit was rigged up to extract a message signal from an FM signal. An
undistorted message signal was captured at an optimum frequency deviation setting of 20 KHz.
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Expt No. 9
PAM AND VERIFICATION OF SAMPLING THEOREM
Date:
AIM: To rig up a circuit to generate a Pulse Amplitude Modulation Signal and to verify the sampling
theorm for appropriate message signal to avoid Aliasing.
TE S T RI G S :
S.NO.

NAME

RANGE

QNTY

DSO

100 MSPS

FUNCTION GENERATOR

0 2 MHZ

COMPONENTS:
S.NO.

NAME

PART NUMBER

QNTY

RESISTORS

3.3K, 4.7K, 22K

1 each

CAPACITORS

100nF

TRANSISTOR

SL100

BREAD BOARD

THEORY:
Pulse-amplitude modulation, acronym PAM, is a form of signal modulation where the message
information is encoded in the amplitude of a series of signal pulses.
Example: A two bit modulator (PAM-4) will take two bits at a time and will map the signal amplitude to one
of four possible levels, for example 3 volts, 1 volt, 1 volt, and 3 volts.
Demodulation is performed by detecting the amplitude level of the carrier at every symbol period.
Pulse-amplitude modulation is widely used in baseband transmission of digital data. Some versions of the
widely popular Ethernet communication standard are a good example of PAM usage. In particular, the
Fast Ethernet 100BASE-T2 medium (now defunct), running at 100 Mbit/s, utilizes 5 level PAM modulation
(PAM-5) running at 25 mega pulses/sec over two wire pairs.
Pulse Amplitude Modulation has also been developed for the control of Light Emitting Diodes especially
for lighting applications. LED drivers based on the PAM technique offer improved energy efficiency over
systems based upon other common driver modulation techniques such as Pulse Width Modulation as the
forward current passing through an LED is relative to the intensity of the light output and the LED
efficiency increases as the forward current is reduced.

Figure: 1 Pulse Amplitude Modulation

PURPOSE:
Pulse Amplitude Modulation is the most simplest of all Digital Modulation Techniques currently
available. A simple circuit around a single driver transistor is implemented and the aliasing effect is noted.
CIRCUIT DIAGRAM:
Modulating

Signal
R1
4.7K

PAM
VOFF = 3 V DC
VAMPL = 3V
FREQ = 100Hz

V1

R3
3.

R2
3K Q1
22K
V2

Message
C1
100nF

SL100

5KHz @ 5V

Carrier
Pulse

Figure: 2 Circuit Diagram

FILTER DESIGN:
1.
2.
3.
4.

Let the Cut off frequency of the filter fo >> fm

Choose Fo = 500 Hz = 1/( 2R3C1)
Choose C1 = 100nF, therefore R3 = 3.3K
Rc = 4.7K, Rb = 22K

PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.

The circuit of figure 2 is rigged up with modulating frequency connected to the collector of SL100
with amplitude of 3 volts and at 100 Hz sine wave.
An offset of 1 to 3 Volts DC bias is adjusted in the function generator which supplies the
modulating signal of 100 Hz.
A Carrier signal of 1 to 5 KHz with minimum amplitude of 1 V is applied as shown in the circuit.
The output PAM is available at the collector of Q1.
Adjust the amplitude of both the carrier and the modulating signal to get a pure PAM signal.
The low-pass filter comprising of R3 and C1 demodulates the PAM signal.
All the signals are tabulated.
To verify the Sampling Theorem, the frequency of the carrier and the modulating signals are
altered as
a. Fc < 2Fm
b. Fc = 2Fm
c. Fc > 2Fm
And the output PAM signals is verified with sampling theorem as shown in figure 3.

T A B U L A T I ON :

Vc
S.No (pp)
.
Volt
s

Fc
in
Hz

Reconstruc
ted
Vm
Sign
(pp)
Volt Vo alFo in
Volts Hz
s

1
2
3
4
5
6
PINOUT DI AGRAM OF SL100:
VERIFICATION OF SAMPLING THEOREM:

Figure 3. Verification of Sampling Theorem

REFERENCES:
1. Datasheet of SL100
2. Electronic Communications Systems V Edition by Wayne Tomasi Pearson Education.
3. Communications Lab Manual, ECE Department, S.S.I.T., Tumkur 572105
4. Communications Lab Manual, ECE Department, Easwari Engg College, Chennai 89.
RESULT: Thus a PAM circuit was built and sampling theorem was verified under three conditions of Fm
& Fc.

Expt No. 10
PULSE CODE MODULATION ENCODER AND DECODER
Date
AIM: To rig up a Pulse Code Modulation Circuit and to observe the message pulses at the output of the
Detector. This is to be carried out with the help of trainer kit.
TE S T RI G S :
S.NO.

NAME

RANGE

QNTY

DSO

0 30 MHZ

FUNCTION GENERATOR

0 2 MHZ

VARIABLE POWER SUPPLY

0 30 V ( DUAL )

Sri
Selvakumaran
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S.No
1.
2.
3.

Book Name
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Ex. No. 11
DELTA MODULATION AND DEMODULATION
Date
AIM: To understand the theory of Delta Modulation by rigging up a suitable circuit and to demodulate the
message signal.
TE S T RI G S :
S.NO.

NAME

RANGE

QNTY

DSO

100 MSPS

FUNCTION GENERATOR

0 2 MHZ

VARIABLE POWER SUPPLY

0 30 V ( DUAL )

COMPONENTS:
S.NO.

NAME

PART NUMBER

QNTY

RESISTORS

150K, 100K

1,3

CAPACITORS

100nF, 10nF

1 each

INTEGRATED CIRCUITS

LM741, CD4013, CD4016

1 each

BREAD BOARD

THEORY:
A 1-bit DPCM coder is known as a delta modulator (DM). In other words, DM codes the
differences in the signal amplitude instead of the signal amplitude itself. Yet another name for DM is pulse
width modulation
A delta-modulation encoder is shown in Figure 1; it is known as a single integration modulator.

Figure 1. Delta Modulation Encoder

The input signal is compared to the integrated output pulses and the delta (difference) signal is
applied to the quantizer. The quantizer generates a positive pulse when the difference signal is negative,
and a negative pulse when the difference signal is positive.
This difference signal moves the integrator step by step closer to the present value input, tracking
the derivative of the input signal.
For example if we consider 1.5 kHz sinusoidal input signal with maximum amplitude 1 and delta is
chosen to be 0.125 which is equivalent to 4 bit quantization i.e. 16 quantization levels.
To achieve a resolution equivalent to 4 bit quantization with 4 kHz sampling rate an oversampling
ratio of 16 is needed i.e. (4^2)/(1^2)*4kHz=64 kHz. In Figure 2, 32 times oversampling is used and the
output of the integrator tracks nicely the input signal.
Figure 2. 32 times oversampled DM signal
A delta modulation decoder has to integrate
the modulated signal and low pass filter the output of
the integrator as shown in figure 3.

Figure 3. DM Decoder
PURPOSE:
This experiment demonstrates the principle of Delta Modulation from its first principles as
described in the theory section. An active Integrator circuit can be built using an Op-Amp followed by a
Low Pass Filter to decode the message signal usually voice.

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CIRCUIT DIAGRAM:
Clock In 10 KHz C1
Square Wave

+V cc

+V cc

U1

U2A

3
5

LM741

1
2
3
4
5

Q
Q
CLK
R

6
7

D 4013 R2
S
D2
GND
S2

6
1

R1
100k

VDD
Q2
!Q2
CLK2

14
13
12
11
10

+V cc

X1

1
3
CD4016

9
8

-V cc

8
12

10

11

-V cc
7

R3
150k

100k

13

mr(t)

U3
R4

-V cc

Message In
250 Hz

Out

R2
100k

14

100n

Note: Vcc = 5V
10n
C2

-Vcc = - 5V

-V cc

Figure 4. Delta Modulator

DESCRIPTION OF THE COMPONENTS USED:
LM741:
The amplifiers offer many features which make their application
nearly foolproof: overload protection on the input and output, no
latch-up when the common mode range is exceeded, as well
as freedom from oscillations.

CD4013:
The CD4013B dual D-type flip-flop is a monolithic
complementary MOS (CMOS) integrated circuit constructed
with N- and P-channel enhancement mode transistors. Each
flip-flop has independent data, set, reset, and clock inputs and
Q and Q outputs.
These devices can be used for shift register
applications, and by connecting Q output to the data input,
for counter and toggle applications. The logic level present at
the D input is transferred to the Q output during the positivegoing transition of the clock pulse. Setting or resetting is
independent of the clock and is accomplished by a high level
on the set or reset line respectively.

TRUTH TABLE:

CD4016:

The CD1016 Series Types are Quad Bilateral Switches

intended for the Transmission or Multiplexing of Analog or
Digital Signals. Each of the four independent bilateral switches
has a single control signal input which simultaneously biases
both the P and N device in a given switch ON or OFF.
Applications include
Analog Signal switching / multiplexing / Signal gating /
Squelch Control / Chopper
Modulator / Demodulator
Digital Signal Switching / Multiplexing
CMOS logic implementation
A to D & D to A Conversion
Digital Control of Frequency, Impedance, Phase, and Analog-Signal Gain
PURPOSE:
This experiment demonstrates the principle of Delta Modulation and how the various building
blocks are implemented from the block diagram representations. The demodulation part is left to the
student to design and test its functionality.
PREC AUTIONS:
Clock input should be between 0 and +Vdd for CD4013.
The ICs should be populated on to the Bread Board in location where they have the best fit.

HOW IT WORKS:
The LM741 is operated open loop as a comparator between the input signal m(t) and the
feedback error signal mr(t).
The function of CD4013 is to hold the value of the quantized error signal constant at + or Vcc
during the sampling period.
Both the ICs CD4013 and CD4016 are enabled by the same clock input.
A DC integrator is used in the feedback loop.
The propagation delay in the Flip-flop is considered negligible.
T A B U L A T I ON :

S.No
.
1

Carrier Input ( Square

Wave )
Frequency in
Amplitude in
KHz
V
10
5

10

Message Input ( Sine

Wave )
Frequency in
Amplitude in
Hz
V
250
1
100
0

PROCEDURE:
1.
2.
3.
4.
5.
6.
7.

The circuit of figure 3 is rigged up with all precautionary measures.

The clock signal input is a square wave of 10 KHz with an amplitude of 5V.
The message signal input is a sine wave at 250Hz with amplitude of 1V.
The DSO is used to observe the message signal and the output DM signal.
The amplitude of the carrier and the message signal are adjusted to produce a distortion less DM.
Observe the error signal at pin 3 of U1.
Tabulate the observation.

PS:
Students are advised to design a Demodulator circuit for the block diagram of figure 3.
from the knowledge acquired from the theor y of Linear Integrated Circuits
REFERENCES:
1.

DATASHEETS of LM741, CD4013, CD4016.

2. DIGITAL COMMUNICATIONS LAB, UNIVERSITY OF CENTRAL FLORIDA.

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Expt No. 12
DIGITAL MODULATION TECHNIQUES USING TRAINERS
Date
AIM: To study the various Digital Modulation Techniques and to observe the waveforms using Advanced
Digital Communication Trainer Kit.
TE S T RI G S :
S.NO.

NAME

RANGE

QNTY

DSO

0 30 MHZ

Advanced Digital Communication Trainer

10 Experiments

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