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Lab Report # 01

To measure the effect of drain voltage (VDS) on


drain current (IDS) with zero gate bias

Circuit

Theory:
The field-effect transistor (FET) is a transistor that relies on an
electric field to control the shape and hence the conductivity of a 'channel'
in a semiconductor material. FETs are sometimes used as voltage-controlled
resistors. The concepts related to the field effect transistor predated
those of the bipolar junction transistor (BJT). Nevertheless, FETs were
implemented only after BJTs due to the simplicity of manufacturing BJTs
over FETs at the time

The shape of the conducting channel in a FET is altered when a potential


difference is applied to the gate terminal (potential relative to either
source or drain.) In an n-channel "depletion-mode" device, a negative gate
voltage causes a depletion region to expand in size and encroach on the
channel from the side, narrowing the channel. If the depletion region
completely closes the channel, the resistance of the channel becomes very
large, and the FET is effectively turned off. Positive gate voltage attracts
electrons from the surrounding semiconductor next to the gate, forming a
conductive channel. At low source-to-drain voltages, small changes to the
gate voltage will alter the channel resistance. In this mode the FET operates
like a variable resistor. This mode is not employed when amplification is
needed.
If a larger potential difference is applied between the source and drain
terminals, this creates a significant current in the channel and produces a
gradient of potential from source to drain. This also causes the shape of the
depletion region to become asymmetricalone end of the channel becomes
narrow. If the potential difference is large enough, the depletion region
begins to close the channel. The FET is said to be in saturation. Rather than
entirely blocking the electrons from flowing from source to drain, electrons
flow through the depletion region in a controlled manner. Any attempted
increase of the drain-to-source voltage will lengthen the depletion region,
increasing the channel resistance proportionally with the applied drain-tosource voltage which causes the value of drain current to remain relatively
fixed. This mode of operation is called pinch-off. In this mode, the FET
behaves as a constant-current source rather than as a resistor and can be
used as a voltage amplifier. The value of gate voltage determines the value
of the constant current in the channel.

Procedure:
The circuit was set up as shown in the circuit diagram. The
1K resistor was connected to Drain. The Source and the Gate terminals
were grounded. To measure the VDS a voltmeter was connected across the
transistor , similarly an ammeter to measure the current.
Finally after taking all precautions into account I got up the readings and
plotted them into chart given below:

Observations chart
VDS (V)
2
3
4
5
6
10
12
14
16
18
20

IDS (mA)
3.25
3.35
3.45
3.55
3.5
3.5
3.5
3.5
3.5
3.5
3.5
We see VP = 5V

Uses:
The most commonly used FET is the MOSFET. The CMOS
(complementary-symmetry metal oxide semiconductor) process technology is
the basis for modern digital integrated circuits. This process technology
uses an arrangement where the (usually "enhancement-mode") p-channel
MOSFET and n-channel MOSFET are connected in series such that when one
is on, the other is off. In CMOS logic devices, the p-channel device pulls up
the output and the n-channel device pulls down the output. The great
advantage of CMOS circuits is that they allow no current to flow (ideally),
except during the transition from one state to the other, which is very
short. The gates are capacitive, and the charging and discharging of the
gates each time a transistor switches states is the primary source of power
usage in fast CMOS logic circuits. However as integrated circuits become
smaller, parasitic resistances are becoming more power consumptive than
switching capacitance.