Switching Circuits & Logic Design

Derivation of State Graph and Tables

Professor Chien-Mo James Li
Graduate Institute of Electronics Engineering
National Taiwan University
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Objective of this Chapter

Learn how to draw State Graph and State table

From a given specification

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Flow of Design a Sequential Ckt.

specification
Ch 14
State graph
State Table
Ch 12

Ch 13

K-map
FF, Comb Logic
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Outline

Design of a Sequence Detector.

More Complex Design Problems.
Guidelines for Construction of State Graphs.
Serial Data Code Conversion.
Alphanumeric State Graph Notation.

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Sequence Detector
Job Statement

Please design a sequence detector that has one input one output
Output =1 when input sequence is 101

Example sequence
X

time

10 11 12 13 14

Fig. 14-1
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Design Flow

1. Mealy or Moore?
2. draw state graph
3. Turn state graph to state table
4. K map
5. circuit design

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Partial State Graph (1)

Lets start from Mealy
S0 is initial state

If receive 0, stay in S0
If receive 1, go to S1

Fig. 14-2

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Partial State graph (2)

If receive 101

Output 1
Go to state S1 (why not S0?)

Fig. 14-3
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Complete State Graph (3)

Check if every state that has 2 emanating arc

Fig. 14-4

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Graph to Table
State Table

TABLE 14-1

Transition Table

TABLE 14-2

Present
State

Next state
X=0

X=1

X=0

X=1

S0

S0

S1

S1

S2

S1

S2

S0

S1

A +B +

AB

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Present Output

X=0

X=1

X=0

X=1

00

00

01

01

10

01

10

00

01

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Table to K-map
Next-state map
Output map

Fig. 14-5
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Final Design Done

Mealy machine design

Fig. 14-5
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Redo Design in Moore

State graph for Moore machine is DIFFERENT from state graph for
MEALY
Because
Moore machine: Z = f(PS)
Mealy machine: Z = f(X, PS)

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Partial State Graph for Moore (1)

Same sequence detector

Fig. 14-5
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Complete State Graph

Note S3 needed

Fig. 14-6

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Graph into Table

State Table

X=0

X=1

Present
Output (Z)

S0

S0

S1

S1

S2

S1

S2

S0

S3

S3

S2

S1

TABLE 14-3

Transition table

Present
State

Next state

TABLE 14-4
A +B +

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AB

X=0

X=1

00

00

01

01

11

01

11

00

10

10

11

01

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Table to K-map
Your exercise

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Comparison of State Graphs

Moore reliable, Moore hardware

Moore

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Mealy

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Outline

Design of a Sequence Detector.

More Complex Design Problems.
Guidelines for Construction of State Graphs.
Serial Data Code Conversion.
Alphanumeric State Graph Notation.

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More Complex Design

Two examples

1. Mealy sequence detector

2. Moore odd/even parity detector

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Example 1. Mealy Sequence Detector

Specification

Please design a sequence detector that has one input X and one
output Z
Output Z=1 when input sequence 010 or 1001 detected
X

time

1
0

1
1

1
2

1
3

1
4

1
5

1
6

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Partial State Graph

Assume Mealy machine

First consider the 010 sequence
Fig 14-7
Why Arc a ?
0101

State

Sequence

S0

Reset

S1

S2

01

S3

010

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Partial State Graph (2)

Fig 14-8
Then consider input sequence 1001
Where does arc e go to?

1001

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Complete State Graph (3)

Fig 14-9
Now consider the other sequences

Other than 010 and 1001

Arc f: 000
Arc g: 011
Arc h: 111
Arc i: 1000
State

Sequence

S0

Reset

S1

0 (but not 10)

S2

01

S3

10

S4

1 (but not 01)

S5

100

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*note this change

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Example 2 : Moore Parity Detector

Specification

Please design a parity detector that has one input and one output
Output = 1 if input sequence is odd parity and at least two
consecutive zeros has been received
Partial state graph
For parity checking

Fig. 14-10
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Partial State Graph (2)

Detects if two consecutive zeros

Fig. 14-11
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Complete State Graph (3)

Before 00

After 00

Fig. 14-12
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Outline

Design of a Sequence Detector.

More Complex Design Problems.
Guidelines for Construction of State Graphs.
Serial Data Code Conversion.
Alphanumeric State Graph Notation.

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Guidelines for State Graph

1. construct sample I/O sequence

2. find initial state
3. construct partial graph for sequence that produce output 1
4. construct partial graph for sequence that must be remembered
5. think twice if you need to create a new state or not
6. make sure there is ONE and ONLY ONE emanating arc for each
state for each combination of input
7 check your graph by applying the input sequence

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Three examples
Example 1. Mealy sequence detector (reset every 4 inputs)
Example 2 . Moore sequence detector (skip)
Example 3. Moore sequence detector (skip)

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Example 1
Specification:

Design a Sequence detector with one input and one output

Inputs sequence is grouped in 4
Reset after four bits
Output = 1 if input = 0101 or 1001
Partial state graph

Fig. 14-13
X

0101 0010 1001 0100

0001 0000 0001 0000

No one here
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Complete State Graph

Q: when receive two consecutive zeros, why s1 to s5,

why not S1 to S1? i.e. Why new state s5 is needed?

State

Sequence

S0

Reset

S1

S2

S3

10 or 01

S4

010 or 100

S5

Two inputs, no
1 output

S6

Three inputs,
no 1 output
Fig. 14-14

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Example 2
Specification

Design a sequence detector that has one input X and two outputs
Z1 and Z2
Z1 = 1 when input is 100 AND no 010 occurs before
Z2=1 when input is 010

100110010

1010010110100

Z1

001000100

0000000000000

Z2

000000001

0101001000010

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Partial State Graph (1)

Consider 100 and 010 sequences

Before 010 occurs

Fig. 14-15
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Partial State Graph (2)

After 010 occurs

Fig. 14-16 (a)

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Complete Graph

Fig. 14-16 (b)

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After 010 occurs

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Example 3
Self study

Fig. 14-17
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Outline

Design of a Sequence Detector.

More Complex Design Problems.
Guidelines for Construction of State Graphs.
Serial Data Code Conversion.
Alphanumeric State Graph Notation.

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Serial Communication system

Transmitter and receiver

Clock or no clock
Only one data bit at a time

Fig. 14-18

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Four Coding Schemes

NRZ = Non-return to zero: 0=low; 1=high

NRZI = non-return-to-zero-inverted: 0=unchange; 1 = toggle
RZ = return-to-zero: 0=low, 1=high-low
Manchester: 0 = rising; 1 = falling

Fig. 14-19
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Design
Specification

Design a serial code converter

Convert NRZ into Manchester code

Fig. 14-20 (a)

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Ideal Timing Chart

Note: clcok2 is 2X faster than data rate

Negative edge triggered

1 clock period

Fig. 14-20 (b)

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Design in Mealy
State Graph
State Table

Fig 14-20 (d)

PS

NS
X=0

NS
X=1

Z
X=0

Z
X=1

S0

S1

S2

S1

S0

S2

S0

Fig. 14-20 (c)

Q: why only one emanating arc of state S1 ?

Dont care state transition

Incompletely specified state transition

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FFT
False output is BAD

Why?

Fig. 14-20 (b)

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Redesign in Moore
Table 14-21 (c)

1 is impossible

0 is impossible
Fig. 14-21 (b)
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Timing Chart of Moore

No false output

Fig. 14-21 (a)

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FFT
Q1: have you notice any difference between output waveforms of

Mealy and Moore? (ignore false output)

Q2: Does it matter?

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Outline

Design of a Sequence Detector.

More Complex Design Problems.
Guidelines for Construction of State Graphs.
Serial Data Code Conversion.
Alphanumeric State Graph Notation.

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Alphanumeric State Notation

What is that?

State graph labeled with alphanumeric input variables

Rather than 0s and 1s
Advantages
Make it clear and simpler for us to read and understand

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Example
Specification

Design a sequence detector that has two inputs F/R, three

outputs Z1, Z2, Z3
Output = Z1 Z2 Z3 if input = FFF
Output = Z3 Z2 Z1 if input = RRR
Partial State Graph
Alphanumeric label

Fig. 14-22
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Complete State Graph

Note: F has higher priority over R

When F = 1, R is dont care

Fig. 14-22
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Final Check
Make sure all input labels on emanating arcs from a state is

complete
i.e. ORing all Boolean expressions equals one
F+FR+FR=1
Make sure no emanating arc overlap
i.e. ANDing every pair of Boolean expressions equals zero
F. FR =0
F. FR=0
FR. FR=0

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FFT
False output is BAD

Why?

Fig. 14-20 (b)

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Next Time

ch 9 Multiplexers Decoders and PLD

ch 11 Latches and FF
ch 12 Registers and Counters
ch 13 Analysis of Clock Sequential Ckts
ch 14 Derivation of State Graphs and
Tables
ch 16 Sequential Ckt Design
ch 18 Ckts for Arith. Operations
final exam

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