2.

4GHZ POWER AMPLIFIER DESIGN

(Using MGA-43228 ICs)

1 The steps design for Power Amplifier

1.1 Step 1: Calculate DC bias and DC supply

Figure 1 Avago RF amplifier MGA-43228 pin configuration and internal block diagram

1.1.1 Power supply

Select normal gain mode:

V dd 1=V dd 2=V dd 3=V bias=5 V ,V byp=0 V

I dd 1=50 mA , I dd 2=180 mA , I dd 3=270 mA , I bias =26.5 mA

Vc1 ,

V c 2 and

V c 3 are bias pins that are used to set the bias conditions to

the 3 internal gain stages of the PA.

V c =2.1 V
and

Vc1 ,

pin on demonstration board with

R4 =1.2 kOhm .

V c 2 and

Vc3

R2=1.2 kOhm

supplied through
,

R3=300 Ohm

1.1.2 Note
The MGA-43228 has a specific turn-on and turn-off procedure to prevent
damage to the amplifier. A higher voltage at the

Vc

pins than at the

V bias

pin will cause a high current DC short at the

Vc

pins. The turn-on and turn-off

sequence is shown in figure below. The final step in the turn-on procedure
where bias is applied to

V byp

is only used when the low-gain mode is desired.

1.2 Step 2: Small-signal s-parameter calculation

1.2.1 Calculate stable parameter (Stability)
1.2.1.1 S-parameter of MGA-43228 ICs
We are using bandwidth from 2.4 GHz to 2.5GHz. So, we will calculate at 2.450 GHz
frequency. With polarization conditions as at step1 section:

V dd 1=V dd 2=V dd 3=V bias=5 V ,V byp=0 V , V c =2.1V

S-parameter at 2.44628 GHz frequency:

S 11=0.073174774+ j0.3930799123=0.39983 79.45467

S 12=0.0002703+ j0.0009925=0.0010374.76540

S 21=26.735143984 j19.086788848=32.84925 35.52385

S 22=0.8149916151+ j0.340978547=0.88345 157.29640
1.2.1.2 Conditional stability

Z 11

Z 22

Z L=50Ohm
The Rollets
stability
Figure 1 1Two-ports
Network
2

K=

factor K is defined
as: 1 Network
Figure 2 Two-port
Figure

1|S 11| |S 22| +||

2|S 12 S21|

When| |=|S11 S22S12 S 21|

=S11 S 22 S12 S21 =0.38559124.75974

2

K=

||<1

=>

1|S 11| |S 22| +||

2|S 12 S21|

1|0.39983 79.45467| |0.88345 157.29640| +|0.38559124.75974|

=3.08276>1
2|0.00103 74.76540 32.84925 35.52385|

Additional stability factor B is defined as:

2

B=1+|S11| |S22| ||

1+|0.39983 79.45467| |0.88345 157.29640| |0.38559 124.75974| = 0.23071 > 0

Unconditional stability with all value of input and output impedance.

 1 and

1.2.1.3 Select

for system stable

S 12 S21 2
<1
1S 22 2
S S
S ' 22 =S 22+ 12 21 1 <1
1S11 1
S ' 11=S11 +

The circular locus of

center 1=

S11 S 22
2

=0.18089 j5.35854

|S 11| | |
|S 12||S 21|
Radius R1=
=3.02053
||S11|2||2|
2

The circular locus of

is defined as:

center 2=

S22 S11
2

is defined as:

=1.06741 j0.43961

|S 22| ||
|S12||S 21|
Radius R2=
=0.05348
||S22|2||2|

Figure 2 Circular locus on Smith Chart

 Confirm that with all of input and output impedance, the power
amplifiers operate stability.
1.2.2 Calculate transducer power gain and noise figure
1.2.2.1 Calculate maximum transducer power gain
We have an unconditional stable device k > 1 and

||<1, we can solve for maximum

transducer power gain simultaneous conjugate match conditions:

1 =

MS ML

S ' 11

2 =

S ' 22

B1 B124 |C1|
MS =
=0.28042 88.06656
2 C1

B 2 B224|C 2|
ML =
=0.87398157.61572
2C 2
2

B 1=1+|S11| |S22| ||
B 2=1+|S22| |S 11| ||
C1 =S 11 S 22
C2 =S 22 S11
Maximum transducer power gain:

1=

MS=0.28042 88.06656
2

GTUmax =

2=

ML=0.87398157.61572

|S 21| (1| MS| )( 1| ML| )

2

|( 1 MS S 11 ) ( 1 ML S22 ) MS ML S 12 S21|

Maximum available gain (MAG):

MAG=

|S21| (
k k 21 )=4595.396=37.26193dB
S
| 12|

=4591.19=37.26192 dB

Figure 3 Circular locus of maximum power gain

1.2.2.2 Calculate minimum noise figure

NF=10 log

SNR input
=2.1 dB
SNR output

We have the ratio SNR input good (> 45dB) and noise figure NF = 2.1 dB very small,
so we dont need consider noise parameter. We only transmit maximum power gain.
1.2.2.3 Compromises between power gain and noise parameter
Skip this step
1.2.3 Design input and output matching with

MS=0.28042 88.06656

parameter

Z 22

Z 11

1=

MS ML

2=

ML=0.87398157.61572

R L=50 Ohm

 1=

Z R0
1+ 1
= Z =R 0
=43.47218 j26.44712
Z + R0
1 1

2=

Z out R0
1+ 2
=
=3.49338 j9.84666
E Z out =R0
Z out + R 0
1 2

1.2.3.1 Design input impedance matching with

parameter

Figure 4 Parameters of input matching network

Figure 5 Input Matching Network Design

Figure 6 ADS Simulation of Input Matching Network

Figure 7 Simulation Result

1.2.3.2 Design output impedance matching with

Z output

parameter

Figure 8 Parameters of output matching network

Figure 9 Output Matching Network Design

Figure 10 ADS Simulation of Output Matching Network

Figure 11 Simulation Result

1.2.3.3 Simulation Power amplifier circuit

Figure 12 Power Amplifier Design

Figure 13 Simulation Result

1.2.3.4 Evaluate design power amplifier circuit

Ideal Parameters

37.26193

Gain
Input return loss (IRL)
output return loss (ORL)

Z out
Z

PA circuit
design(Simulation)
37.014 dB

dB

-46.543 dB
-37.506 dB

3.49338 j9.84666

3.43891 j9.80979

43.47218 j26.44712

43.5666 j26.4130

SIMULATION WITH BANDWIDTH FORM 2.4 GHz to 2.5GHz FREQUENCY

Frequenc
y GHz
Gain dB
Input
return
loss (IRL)
dB
output
return
loss
(ORL) dB

2.396
GHz
36.91
-21.914

2.4088

2.434

2.446

2.458

2.471

2.483

2.496

36.977
-35.908

37.273
-22.071

37.014
-46.543

37.165
25.998

37.14
-23.453

36.752
-21.641

36.856
-23.322

-18.682

-23.083

-31.081

-37.506

26.913

-26.412

-17.781

-16.485

1.3 Large Signal S-parameter simulation