International Journal of Engineering Trends and Technology (IJETT) Volume 10 Number 5 - Apr 2014

Design and Simulation of I2C bus using Verilog

G.KrishnaKishore#1,
1

Asst.Professor in VBIT

K.Shruti#2,
2

B.TECH student in VBIT

Abstract: The paper mainly focuses on to Design

and Simulation of I2C Bus Protocol which allows
faster devices to communicate with slower devices
and leads communication with each other over a
serial data bus. I2C bus require less wiring, few
connection pins and less number of traces required
on printed circuit boards.

M.Varsha#3
3

B.TECH student in VBIT

I2C devices available today support 400Kbps

operation. High speed operation may allow I2C to
keep up with the increasing demand for
bandwidth in multimedia and other applications.

Index terms: I2C Bus, master, slave, verilog,

Finite state machine
I. INTRODUCTION
I2C Bus provides communication between system
processor and peripheral devices. It is used to
minimize system-level hardware. Data transfer
over I2C bus will improve system performance
since the transmission of digital data is much less
susceptible to interference from environmental
noise sources.
II. SPECIFICATIONS
The I2C Bus is a two-wire, bi-directional serial bus
that provides a simple and efficient method of
data transmission over a short distance between
many devices. I2C provides good support for
communication with various slow, on-board
peripheral devices. I2C bus is considered to be
simple, with low-bandwidth and it is a short
distance protocol.. I2C also links multiple devices
together. I2C comprises two signals namely serial

data (SDA) and serial Clock (SCL). The device

which initiates a transaction on the I2C bus is
termed the master. A device being addressed by
the master is called a slave. Master controls the
clock signal. The I2C protocol supports multiple
masters and multiple slaves. Masters and Slaves
can receive and transmit data bytes. Standard I2C
devices can operate up to 100Kbps, where as
fast-mode devices operate up to 400Kbps. The

ISSN: 2231-5381

Figure 1: I2C bus configuration

III. FEATURES
I2C requires has only two bus lines; a serial data line
(SDA) and a serial clock line (SCL). Devices that are
connected to the bus are software addressable with
unique addresses. It is a true multi-master bus which
overcomes collision detection and arbitration to prevent
data corruption if two or more masters simultaneously
initiate data transfer. Serial, 8-bit oriented, bidirectional
data transfers can be made at up to 100 Kbit/s in the
Standard-mode, up to 400 Kbit/s in the Fast-mode, up
to 1 Mbit/s in Fast-mode Plus. Serial, 8-bit oriented,
unidirectional data transfers up to 5 Mbit/s in Ultra
Fast-mode. On-chip filtering rejects spikes on the bus
data line to preserve data integrity. The number of ICs
that can be connected to the same bus is limited only by
a maximum bus capacitance. More capacitance may be
allowed under some conditions.

IV. PROTOCOL OF I2C

Physically, the IC bus consists of the 2 active
wires SDA and SCL and a ground connection. The
active wires are bi-directional. The I2C protocol
specification states that the IC that initiates a
data transfer on the bus is considered the Bus
Master. Consequently, at that time, all the other
ICs are considered to be Bus Slaves.

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International Journal of Engineering Trends and Technology (IJETT) Volume 10 Number 5 - Apr 2014

the RW bit. Every slave in the system is assigned

a unique address such that, no two slaves in the
system can have the same address. Only the slave
with an address matching with the one
transmitted by the master will respond by
providing an acknowledge bit in return by pulling
the SDA low at SCL clock cycle.

Figure 2: I2C bus connected between 2 devices. SDA,

SCL connected through pull up
resistors.

A standard communication consists of four parts:

START signal generation

Slave address transfer
Data transfer
STOP signal generation

DATA-TRANSFER:-Once the successful slave

addressing has been achieved, the data transfer
can proceed on a Byte-by-byte basis in the
direction specified by the RW bit sent by the
master. Each transferred byte is followed by an
acknowledge bit on SCL clock cycle. If the slaves
access NEG-Acknowledge, the master can
generate a STOP signal to stop the data transfer
and start a new transfer cycle. If the master, as
the receiving device, does not acknowledge the
slave, the slave releases the SDA line for the
master to generate a STOP or Repeated START
signal.

START signal: - When the bus is free/idle, it means no

master device is engaging the bus where both SCL and
SDA lines are high. A master can initiate a data transfer
by sending a START signal. A START signal, usually
represented by S-bit, which is a high-to-low transition
of SDA while SCL is high. The START signal denotes
the beginning of a new data transfer.
STOP signal: - The master terminates the
communication by generating a STOP signal. A STOP
signal, usually represented by P-bit, which is a low-tohigh transition of SDA while SCL is at logic1.

Figure 4: I2C Data transfer

Figure 5: I2C Data Format

Figure 3: START/STOP conditions
SLAVE ADDRESS TRANSFER: - The first byte of
data transferred by the master immediately after
the START signal is called the slave address. This is
a seven-bit address followed by a RW bit. The
data transfer direction to the slave is signaled by

ISSN: 2231-5381

V. FINITE STATE MACHINE

Design of an I2C bus involves the usage of a Finite
State Machine (FSM). We can easily implement
FSM using Verilog in this paper.

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International Journal of Engineering Trends and Technology (IJETT) Volume 10 Number 5 - Apr 2014

A finite state machine is a sequential circuit that

uses
a finite number of states to keep track of its
history of
Operations, and based on this history and its
current
Inputs, it determines what to do next.
Input
output
States

SIMULATION RESULTS

current
excitation

Next
state
logic

State
Memory
Register

state

state
Output
Control
Logic

Clock

Figure 7: Master-Slave top RTL Schematic

Figure 6: Block Diagram of FSM

VI. RESULT ANALYSIS
The I2C bus protocol is designed using verilog and
implemented in
Xilinx_ISE_DS_Win_13.2_O.61xd.0.0. The device
utilization summary is given below:

Device Utilization Summary (estimated devices)

Logic Utilization
Number of Slice
Registers
Number of Slice
LUTs
Number of fully
used Bit Slices
Number
of
bonded IOBs
Number
of
BUFG/BUFGCTRL
s

Use
d

Availabl
e

Utilizatio
n

94

19200

0%

148

19200

0%

84

158

53%

28

220

12%

32

3%

Figure 8:
Schematic

Internal Master and Slave RTL

Figure 9: Master and Slave top module

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International Journal of Engineering Trends and Technology (IJETT) Volume 10 Number 5 - Apr 2014

VII. CONCLUSION
The design process is simplified using verilog HDL
to design the I2C bus. The designer can write his
design description without choosing any specific
fabrication technology. If a new technology
emerges, designers do not need to redesign the
circuit. He simply input the design program to the
logic synthesis tool and creates a new gate level
netlist using the new fabrication technology. The
logic synthesis tool will lessen the circuit in area
and timing for the new technology.
VIII. REFERENCES
[1] The I2C Bus specifications version 2.1 January
2000
[2] UM10204 I2C -bus specification and user
manual
Rev. 4 13 February 2012
[3] I2C bus Inter Integrated Circuits bus by Philips
Semiconductors
[4] Embedded Platform Excalibur Altera,
http://www.altera.com
[5] Muhammed Ali Maidu, Janice Gillispie Mazidi
& Rolin D. Mckinlay, the 8051 Microcontroller
and
Embedded Systems, using Assembly and C,
second
Edition, Pearson Education.
[6]IEEE Computer Society. IEEE Standard Verilog
Hardware Description Language, IEEE Std 1364

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