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#604 ( Shabbir )

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Email
shabbir.ali46@gmail.com
First Name
Shabbir
Last Name
Test Name
Digital Electronics - Set 3
Time taken
31:06 Min
Obtained Percentage 65 %
Status
Fail

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Q 1)
A cache memory is

Small and fast SRAM

Small and fast DRAM
Small and fast flash
large and slow SRAM
Small and fast DRAM
Q 2)
SRAM has 16 bit address bus (A0-A15) and 8 bit data bus (D0-D7) as input ports. While
integrating this to another controller, all prime numbered address lines are tied to 1'b1. How
much would be the memory space addressed by the system?

(8X8) bits
(128X8) bits
(32X8) bits
(256X8) bits

(256X8) bits
Q 3)
The minimum number of NAND gates required to realize the given SOP expression:
Y=a'b'c'+a'bc'+a'bc+ab'c'+abc'+abc
(Assume that the complements are not available)

3
1
2
4
4
Q 4)
How many blocks will an 'n' variable K-map have?

2n
2^n
2^(n-1)
(2^n)-1
2^n
Q 5)
Which of the following devices can be used to generate arbitary logic functions?

Decoder
Encoder
De-mux
Mux
Mux

Q 6)
Assuming that our technology library consists of gates of a single kind, as shown in figure. What
is the minimum number of such gates required to realize a NAND gate?
1
2
3
4
2

Q 7)
Consider the following. Assuming that the setup time=0.7ns, hold time=1ns, clk to Q
delay=0.3ns and the logic delay of the combinational cloud =5ns, what is the maximum
frequency of operation?
142.8 MHz
312.5 MHz
166.67 MHz
200 MHz
166.67 MHz

Q 8)
Consider the serial in parallel out shift register as shown. What should the register be initialized
with, if we want to see Q3Q2Q1Q0=1001 on the output lines at some point?
0010

1100
0101
1010
1100
Q 9)
On a master-slave flip-flop, when is the master enabled?

when the gate is LOW

when the gate is HIGH
both of the above
neither of the above
when the gate is HIGH
Q 10) Which of the following is correct for a gated D flip-flop?
The output toggles if one of the inputs is held HIGH.
Only one of the inputs can be HIGH at a time.
The output complement follows the input when enabled.
Q output follows the input D when the enable is HIGH.
Q output follows the input D when the enable is HIGH.
Q 11) Convert BCD 0001 0010 0110 to binary.
1111110
1111101
1111000
1111111
1111110
Q 12) How many 1-of-16 decoders are required for decoding a 7-bit binary number?
5
6
7
8
8
Q 13) Which of the following statements accurately represents the two BEST methods of logic circuit
simplification?

Boolean algebra and Karnaugh mapping

Karnaugh mapping and circuit waveform analysis

Actual circuit trial and error evaluation and waveform analysis

Boolean algebra and actual circuit trial and error evaluation
Boolean algebra and Karnaugh mapping
Q 14) How many flip-flops are required to produce a divide-by-128 device?
1
4
6
7
7
Q 15) With regard to a D latch, ________.
the Q output follows the D input when EN is LOW
the Q output is opposite the D input when EN is LOW
the Q output follows the D input when EN is HIGH
the Q output is HIGH regardless of EN's input state
the Q output follows the D input when EN is HIGH
Q 16) A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________
position(s) for each clock pulse.

right, one
right, two
left, one
left, three
left, three
Q 17) With a 50 kHz clock frequency, six bits can be serially entered into a shift register in ________.
12 us
120 us
12 ms
120 ms
120 ms
Q 18) What is the difference between setup time and hold time?
Setup time occurs after the active clock edge, hold time occurs before the active clock edge.
Setup time occurs before the active clock edge, hold time occurs after the active clock edge
Setup time and hold time both occur at the active clock edge
None
Setup time occurs before the active clock edge, hold time occurs after the active clock edge
Q 19) Which term applies to the maintaining of a given signal level until the next sampling?

Holding
Aliasing
Shannon frequency sampling
Stair-stepping
Holding
Q 20) How will we know whether FIFO is full?
A. Read ptr = write ptr and the last location was write
B. Read ptr = write ptr and the last location was read
C. Read ptr < write ptr and the last location was write.
None
B. Read ptr = write ptr and the last location was read
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