SHAHID QURESHI

www.linkedin.com/in/qureshishahid
(408) 466-7456 / shahid.qureshi@sjsu.edu

DIGITAL DESIGN AND VERIFICATION ENGINEER

EXPERIENCE
ASIC ENGINEER INTERN, Palo Alto Networks
Jun15 - Aug15
Worked on the complete ASIC flow from making design specifications, RTL coding, lint, synthesis, test plan, functional verification of
the design with a UVM based environment using BFMs, monitors, sequencers and Stimulus with Sequences and Sequence items.
Designed a flow control monitor that will help the team with performance related debug issues in the lab
NETWORK ENGINEER INTERN, Tata Communications Ltd., India
Dec12 - Mar13
Debugged and restored networks links (VPN, ILL, NPLC, IPLC) in co-ordination with different teams

EDUCATION
M.S.
Electrical Engineering (VLSI)
San Jose State University
GPA: 3.7/4
Coursework: Digital Logic Design and Synthesis, ASIC CMOS Design, SoC Design and Verification using SystemVerilog
B.Tech.
Electronics and Comm.
Dharmsinh Desai University, India
Coursework: ASIC Design, Digital Electronics, Embedded Systems (ARM 7)

May16
May13

PROFESSIONAL COURSES
UCSC Extension
System and Functional Verification using UVM
June15-Aug15
Developed Testbenches with layered, constrained-random and coverage driven environments using the existing UVM base classes for
Agents, Driver, Monitor, Sequencer, Scoreboards and Test cases
UCSC Extension
Advanced Verification with SystemVerilog OOP Testbench
Apr15-June15
Developing an advanced OOP testbench verification environment with transaction-level and layered architecture by building flexible
testbench components with the use of virtual interfaces, classes, mailboxes, dynamic arrays, and queues

SKILLS

Key Skills: Logic Design, ASIC & FPGA Design flow, RTL Design, Simulation, Synthesis, Static Timing Analysis (STA), Place and
Route, functional verification, Assertions, Coverage, debugging
Verification Methodologies: Universal Verification Methodology (UVM)
Tools:
Behavioral SimulationSynopsys VCS, ModelSim
SynthesisSynopsys DC, Design Vision
FPGA toolsQuartus II, NIOS II, Qsys
Place & RouteCadence Encounter
Programming Languages:
Verilog, SystemVerilog, C, C++
Scripting Languages:
PERL

PROJECTS
Functional Verification using SV UVM for 10G Ethernet MAC design
Jun15 - Aug15
Developed a verification environment for an open source 10g ethernet MAC core DUT with a TX, RX and XGMII interface
Verified the functionality of the DUT by building VIP which supports Reset Agent, Configure agent, TX agent, RX agent, respective

sequence items, scoreboard for packet comparison

Ensured completeness of design with testcases and 100% coverage closure
Language: SystemVerilog, Shell scripts
Tools: Synopsys VCS

RTL Design of a DMA Controller

Mar14 - April14

Designed, simulated and synthesized a programmable DMA controller connected to 4 devices

Performed Fetch, Decode, Execution and Jump in separate cycles for 32 bit instructions from processor
Pushed the design running frequency to 300 Mhz using pipeling and optimization techniques
Performed Place and route using Cadence encounter tool
Language: Verilog, PERL
Tools: Synopsys VCS, Synopsys DC, Cadence Encounter

RTL Design of a 4 x 4 Keypad Scanner and Encoder

May14 - July14
Designed, simulated and synthesized a Keypad scanner and encoder interfaced to a 4x4 matrix keypad
Stored Pressed keys in FIFO and converted them to 8-bit packed BCD output with a decoder
Performed STA (Static Timing Analysis) and DTA (Dynamic Timing Analysis)
Designed automation scripts in PERL and Synthesis scripts to automate the simulation, synthesis and generation of reports
Language: Verilog, PERL
Tools: Synopsys VCS, Synopsys DC, Synopsys Design Vision

Image Warping on Altera DE1 FPGA board

Oct14 - Dec14
Implemented an algorithm for warping an image using backward mapping which resulted in a rotated and scaled image with no holes
due to interpolation
Enhanced the performance of the design by using hardware accelerator along with NIOS II processor
Language: Verilog, C, MATLAB
Tools: Quartus II, ModelSim, NIOS II, Qsys, Eclipse

Motion Estimation on Altera DE1 FPGA board

Implemented a motion estimation algorithm to find 16 motion vectors for the current frame from the previous frame
Reduced the no of cycles by designing a hardware accelerator by adding Qsys component designed using Verilog
Language: Verilog, C
Tools: Quartus II, ModelSim, NIOS II, Qsys, Eclipse

Sept14 - Oct14