Junction and Doping Free Transistors For

Future Computing
Chitrakant Sahu and Jawar Singh
PDPM-Indian Institute of Information Technology Design and Manufacturing Jabalpur, MP, India

E-mail: chitrakant.sahu@iiitdmj.ac.in, jawar@iiitdmj.ac.in

Abstract
Continued down-scaling of device dimensions poses severe challenges and difficulties for
complementary metal-oxide semiconductor (CMOS) technology, particularly fabrication complexities,
process variability, and short channel effects (SCEs). These challenges mainly arise due to abrupt
doping profile requirement at junctions and random dopant fluctuations. Recently, the junctionless
field-effect transistors (JLFETs), also known as gated resistors have widely attracted attention, as
+

they do not require formation of any metallurgical junctions (P-N, N -N, or P -P) and doping
concentration gradient throughout the device. Thus, they relax abrupt doping profile requirements and
greatly simplify the fabrication process. A key requirement for JLFETs is the formation of a
semiconductor layer that should be thin and narrow enough to be depleted when the JLFET is in offstate. At the same time, semiconductor layer should be doped enough to achieve an adequate
amount of drain current in on-state. Therefore, JLFETs are generally made of heavily doped silicon
nanowires. The heavily doped nature of JLFETs causes certain problems and to address them the
concept of doping-free (dopingless) JLFETs was recently proposed. In this chapter, detail study of
both junction free and doping free transistors is presented based on 2-D device simulation with model
calibrated to experimental data.

Around 25 pages embedded here!!!

Conclusion:
The simplified fabrication process and easy scaling of junctionless field-effect transistor
(JLFET) over inversion mode FET makes JLFET a potential candidate, however, poor performance
towards process variations and other limitations hinders its applicability for future CMOS technology
based computing. Therefore, an alternate device architecture that preserves the merits of JLFET and
alleviates its drawbacks was exhaustively studied and investigated for digital and analog applications,
is referred as junction and doping free FET (i.e.DL-DGFET). The DL-DGFET architecture has a metalsemiconductor interface in source/drain region, which required metal work function engineering
instead of placing a simple ohmic contact. The benefits of DL-DGFET are large ON to OFF current
ratio, lower Vth roll-off and minimize SCEs, at the same time, undoped silicon in this device makes it
immune to process variations (or RDFs).

Further, the concept of charge plasma (i.e. junction and doping free FET) was explored for
realizing a symmetric bipolar junction transistor (BJT) having performance much better than the
conventional BJT. The bipolar charge plasma transistor (BCPT) made of electron and hole plasmas
on undoped silicon can be realized with less thermal budget as compared to doped transistors and
CMOS devices. The efficacy of the concept was verified using TCAD simulations. The electrical
characteristics of the symmetric BCPT are compared with a conventional doped bipolar transistor and
it exhibits better performance like high current gain than conventional BJT. The dopingless FET and
BJT concept can be also applied for BiCMOS technology to overcome the drawback of low integration
and fabrication complexity.

REFERENCES
[1] Lilienfeld J.E.: Method and apparatus for controlling electric cur-rent. U.S. Patent 1 745
175, 1925.
[2] Colinge J.P., Lee C.W., Afzalian A., ET AL.: Nanowire transistorswithout junctions, Nat.
Nanotechnol., 2010, 5, (3), pp. 225229.
[3] Park C.-H., Ko M.-D., Kim K.-H., ET AL.: Electrical characteristics of 20-nm junctionless
Si nanowire transistors, Solid State Electron.,2012, 73, (7), p. 710
[4] Jeon D.-Y., Park S.J., Mouis M., Barraud S., Kim G.-T., Ghibaudo G.:A new method for
the extraction of flat-band voltage and doping concentrationin tri-gate Junctionless
transistors, J. Solid-State Electron.,81, (2013), pp. 113118
[5] Chen Z., Xiao Y., Tang M., ET AL.: Surface-potential-based draincurrent model for longchannel junctionless double-gate mosfets,IEEE Trans. Electron Devices, 2012, 59, (12),
32923298
[6] Duarte J.P., Choi S.J., Moon D.I., Choi Y.K.: Simple analytical bulkcurrent model for
long-channel double-gate junctionless transistors,Trans. Electron Devices, 2011, 32, pp.
704706
[7] Duarte J.P., Choi S.-J., Choi Y.-K.: A full-range drain current model for double-gate
junctionless transistors, IEEE Trans. ElectronDevices, 2011, 32, (6), 704706
[8] Bulk Planar Junctionless Transistor (BPJLT): An attractive device alternative for scaling,
IEEE Electron Device Lett., 2011, 32, (3),261263
[9] Lee C.W., Afzalian A., Akhavan N.D., Yan R., Ferain I., Colinge J.P.: Junctionless
multigate field-effect transistor, Appl. Phys. Lett.,2009, 94, pp. 10535111053511-2
[10] Trevisoli R., Doria R., de Souza M., Das S., Ferain I., Pavanello M.:Surface-potentialbased drain current analytical model for triple-gatejunctionless nanowire transistors, IEEE
Trans. Electron Devices, 2012, 59, (12), pp. 35103518
[11] Han M.-H., Chang C.-Y., Chen H.-B., Cheng Y.-C., Wu Y.-C.:Device and circuit
performance estimation of junctionless bulkfinFETs, IEEE Trans. Electron Devices, 2013,
60, (6), 18071813

[12] Han M.-H., Chang C.-Y., Jhan Y.-R., ET AL.: Characteristic of p-typejunctionless gateall-around nanowire transistor and sensitivity analysis,IEEE Electron Device Lett., 2013, 34,
(2), pp. 157159
[13] Su C.J., Tsai T.I., Liou Y.L., Lin Z.M., Lin H.C., Chao T.S.:Gate-all-around junctionless
transistors with heavily doped polysiliconnanowire channels, Electron Device Lett., 2011,
32,pp. 521523
[14] Leung, G.; Chi On Chui, Variability Impact of Random Dopant Fluctuation on Nanoscale
Junctionless FinFETs, IEEE Electron Device Letters, 2012, 33 (6), pp.767-769
[15] M. Aldegunde, A. Martinez, and J. R. Barker, Study of discrete doping induced
variability in junctionless nanowire MOSFETs using dissipative quantum transport
simulations, IEEE Electron Device Letters, 2012, 33(2), pp. 194-196
[16] Nawaz, S.M.; Dutta, S.; Chattopadhyay, A.; Mallik, A., Comparison of Random Dopant
and Gate-Metal Work function Variability Between Junctionless and Conventional FinFETs, IEEE Electron Device Letters, 2014, 35(6), pp. 663-665
[17] Gundapaneni, S., Bajaj, M., Pandey, R.K.: Effect of Band-to-Band tunneling on
Junction- less Transistors, IEEE Transactions on Electron Devices, 2012, 59, 1023-1029.
[18] B. Rajasekharan, et al., Fabrication and characterization of the charge-plasma diode,
IEEE Electron Device Letters., 2010, 31(6), pp. 528-530.
[19] R. J. E. Hueting, B. Rajasekharan, C. Salm, et al., Charge plasma P-N diode, IEEE
Electron Device Letters., 2008, 29 (12), pp. 1367-1368.
[20] M. J. Kumar and K. Nadda, Bipolar charge-plasma transistor: A novel three terminal
Device, IEEE Transactions on Electron Devices, 2012, 59(4), pp. 962-967.
[21] Kumar, M.J.; Janardhanan, S., Dopingless Tunnel Field Effect Transistor: Design and
Investigation, IEEE Transactions on Electron Devices, 2013, 60(10), pp.3285-3290
[22] T. van Hemert, R. J. E. Hueting, B. Rajasekharan, C. Salm, and J. Schmitz, On the
modelling and optimization of a novel Schottky based silicon rectifier, in Proc. of ESSDERC,
Sevilla, Spain, Sept 2010, IEEE conference 2010, pp. 460-463.
[23] Sahu, C., Singh, J.,Charge-Plasma Based Process Variation Immune Junctionless
Transistor, IEEE, Electron Device Letters, 2014, 35(3), pp.411-413.
[24] Barraud, S., et al, Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length
Down to 13 nm, IEEE, Electron Device Letters, 2012, 33(9), pp.1225-1227
[25] International Technology Roadmaps for Semiconductor, www.itrs.net
[26] N. Collaert et al., Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN
gate stack, fin widths down to 10 nm and 30 nm gate length, in Proc. Int. Conf.
Integr. Circuit Design Technol. (ICICDT), Jun. 2008, IEEE conference 2008, pp. 59-62.
[27] H. Kawasaki et al., Demonstration of highly scaled FinFET SRAM cells with highK/metal gate and investigation of characteristic variability for the 32 nm node and beyond,

in IEEE Int. Electron Device Meeting Tech. Dig., Dec. 2008, IEEE conference 2008, pp. 1415.
[28] T. Mrelle et al., First observation of FinFET specific mismatch behavior and optimization
guidelines for SRAM scaling, in Int. Electron Device Meeting Tech. Dig., Dec. 2008, IEEE
conference 2008, pp. 14-15.
[29] C. C. Wu et al., High performance 22/20 nm FinFET CMOS devices with advanced
high- K/metal gate scheme, in IEEE Int. Electron Device Meeting Tech. Dig., Dec. 2010,
IEEE conference 2010, pp. 27(1)-127(4)
[30] Sahu, C.; Singh, J., 'Potential Benefits and Sensitivity Analysis of Dopingless Transistor
for Low Power Applications,' IEEE Transactions on Electron Devices, 2015, 62(3), pp.729735.
[31] Sahu, C.; Ganguly A., Singh, J., Design and Performance Projection of Symmetric
Bipolar Charge-plasma Transistor on SOI, IET, Electronics Letters, 2014, 50(20), pp.
1461 - 1463
[32] M. J. Kumar and V. Parihar, "Surface Accumulation Layer Transistor (SALTran): A new
bipolar transistor for enhanced current gain and reduced hot-carrier degradation," IEEE
Trans. Device Mater. Rel., 2004, 4(3), pp. 509-515
[33] Kanika Nadda and M. Jagadesh Kumar, 'Schottky Collector Bipolar Transistor Without
Impurity Doped Emitter and Base: Design and Performance', IEEE Transactions on Electron
Devices, 2015, 60(9), pp. 2956 - 2959
[34] Sajad A Loan, Faisal Bashir, M Rafat, Abdul Rehman Alamoud and Shuja A Abbas, 'A
high performance charge plasma based lateral bipolar transistor on selective buried oxide',
IOP, Semiconductor Science and Technology, 2014, 29(1) pp. 11-15

You may cite this article as

Chitrakant Sahu and Jawar Singh, " Junction and Doping Free Transistors For Future Computing", in
Nano-CMOS and Post-CMOS Electronics: Devices and Modelling, Edited by S. P. Mohanty and A.
Srivastava, The Institute of Engineering and Technology (IET), 2016, ISBN: XXX.