entity half_adder is

Port ( ha1,ha2 : in bit;

ha3: out bit; ha4 : out bit);
end half_adder;
architecture Behavioral of half_adder is
begin
ha3<=ha1 xor ha2;
ha4<=ha1 and ha2;
end Behavioral;
entity and_2 is
port (anda,andb : in bit;
andc : out bit);
end and_2;
architecture archand of and_2 is
begin
andc<=anda and andb;
end archand;
entity not1 is
port(nota : in bit;
notb : out bit);
end not1;
architecture archinv of not1 is
begin
notb<=not nota;
end archinv;

entity full_adder is
Port ( fa1,fa2,fa3:in bit;fa4,fa5: out bit);
end full_adder;
architecture Beh of full_adder is
begin
fa4 <=fa1 xor fa2 xor fa3;
fa5 <= (fa1 and fa2) or (fa2 and fa3) or (fa3 and fa1);
end Beh;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity project is
port(x,y: in bit_vector(3 downto 0); p: out bit_vector(7 downto 0));
end project;
architecture Behavioral of project is
component half_adder
port(ha1,ha2:in bit;
ha3:out bit; ha4:out bit);

end component;
component full_adder
port(fa1,fa2,fa3:in bit;
fa4,fa5:out bit);
end component;
component and_2
port(anda,andb:in bit;andc :out bit);
end component;
component not1
port(nota: in bit;notb: out bit);
end component;
signal t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t14,t15,t16,t17,t18,t19,t20,t2
1,t22,t23:bit;
signal u1,u2,u3,u4,u5:bit;
signal v1,v2,v3,v4,v5,v6,v7,v8,v9,v10,v11,v12:bit;
signal k1,k2,k3,k4,k5,k6,k7,k8:bit;
begin
a1: and_2 port map(x(0),y(0),p(0));
a2: and_2 port map(x(1),y(0),u1);
a3: and_2 port map(x(2),y(0),u2);
n1: not1 port map(y(0),k1);
a4: and_2 port map(x(3),k1,u3);
a5: and_2 port map(x(0),y(1),v1);
a6: half_adder port map(u1,v1,p(1),t1);
a7: and_2 port map(x(1),y(1),v2);
a8: half_adder port map(u2,v2,t2,t3);
a10: and_2 port map(x(0),y(2),v3);
a9: full_adder port map(t1,t2,v3,p(2),t4);
a11: and_2 port map(x(2),y(1),v4);
a12: half_adder port map(v4,u3,t5,t6);
a13: and_2 port map(x(1),y(2),v5);
a14: full_adder port map(v5,t3,t5,t7,t8);
a15: not1 port map(x(0),k2);
a16: and_2 port map(y(3),k2,v6);
a17: full_adder port map(t4,t7,v6,t9,t10);
a18: full_adder port map(x(3),y(3),t9,p(3),t11);
a19: and_2 port map(x(2),y(2),v7);
a20: not1 port map(y(1),k3);
a21: and_2 port map(k3,x(3),u4);
a22: full_adder port map(u4,v7,t6,t12,t13);
a23: not1 port map(x(1),k4);
a24: and_2 port map(k4,y(3),v8);
a25: full_adder port map(t8,v8,t12,t14,t15);
a26: full_adder port map(t14,t10,t11,p(4),t16);
a27: not1 port map(y(2),k5);
a28: and_2 port map(x(3),k5,u5);
a29: not1 port map(x(2),k6);
a30: and_2 port map(k6,y(3),v9);
a31: full_adder port map(u5,v9,t13,t17,t18);
a32: full_Adder port map(t15,t16,t17,p(5),t19);
a33: not1 port map(x(3),k7);
a34: not1 port map(y(3),k8);
a35: and_2 port map(x(3),y(3),v10);
a36: full_adder port map(v10,k7,k8,t20,t21);
a37: full_adder port map(t18,t19,t20,p(6),t22);

a38: full_adder port map('1',t21,t22,p(7),t23);

end Behavioral;