Adder (electronics)

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In electronics, an adder or summer is a digital logic circuit that performs addition of numbers. In
many computers and other kinds of processors, adders are used not only in thearithmetic logic units,
but also in other parts of the processor, where they are used to calculate addresses, table
indices, increment and decrement operators, and similar operations.
Although adders can be constructed for many numerical representations, such as binary-coded
decimal or excess-3, the most common adders operate on binary numbers. In cases where two's
complement or ones' complement is being used to represent negative numbers, it is trivial to modify
an adder into an addersubtractor. Other signed number representations require a more complex
adder.
Contents
[hide]

1Half adder

2Full adder

3More complex adders

o

3.1Ripple-carry adder

3.2Lookahead carry unit

3.3Carry-save adders

43:2 compressors

5References

6External links

Half adder[edit]

Half adder logic diagram

The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The
carry signal represents an overflow into the next digit of a multi-digit addition. The value of the sum
is 2C + S. The simplest half-adder design, pictured on the right, incorporates an XOR gate for S and
an AND gate for C. With the addition of an OR gate to combine their carry outputs, two half adders
can be combined to make a full adder.
[1]

The half adder adds two input bits and generates a carry and sum, which are the two outputs of a
half adder. The input variables of a half adder are called the augend and addend bits. The output
variables are the sum and carry. The truth table for the half adder is:

Inputs

Outputs

Full adder[edit]

Schematic symbol for a 1-bit full adder with Cin and Cout drawn on sides of block to emphasize their use in a multi-bit adder

A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full
adder adds three one-bit numbers, often written as A, B, and C ; A and B are the operands, and C is
a bit carried in from the previous less significant stage. The full adder is usually a component in a
cascade of adders, which add 8, 16, 32, etc. bit binary numbers. The circuit produces a two-bit
output, output carry and sum typically represented by the signals C and S,
where
. The one-bit full adder's truth table is:
in

in

[2]

out

Full-adder logic diagram

Inputs

Outputs

Cin

Cout

A full adder can be implemented in many different ways such as with a custom transistor-level circuit
or composed of other gates. One example implementation is with
and

In this implementation, the final OR gate before the carry-out output may be replaced by an XOR
gate without altering the resulting logic. Using only two types of gates is convenient if the circuit is
being implemented using simple IC chips which contain only one gate type per chip.
A full adder can be constructed from two half adders by connecting A and B to the input of one half
adder, connecting the sum from that to an input to the second adder, connecting C to the other input
and OR the two carry outputs. The critical path of a full adder runs through both XOR-gates and
ends at the sum bit . Assumed that an XOR-gate takes 3 delays to complete, the delay imposed by
the critical path of a full adder is equal to
i

The carry-block subcomponent consists of 2 gates and therefore has a delay of

More complex adders[edit]

Ripple-carry adder[edit]

4-bit adder with logic gates shown

It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each
full adder inputs a C , which is the C of the previous adder. This kind of adder is called
a ripple-carry adder, since each carry bit "ripples" to the next full adder. Note that the first
(and only the first) full adder may be replaced by a half adder (under the assumption
that C = 0).
in

out

in

The layout of a ripple-carry adder is simple, which allows for fast design time; however, the
ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be
calculated from the previous full adder. The gate delay can easily be calculated by
inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit
ripple-carry adder, there are 32 full adders, so the critical path (worst case) delay is 3 (from
input to carry in first adder) + 31 * 2 (for carry propagation in later adders) = 65 gate delays.
The general equation for the worst-case delay for an-bit carry-ripple adder is

The delay from bit position 0 to the carry-out is a little different:

The carry-in must travel through n carry-generator blocks to have an effect on the
carry-out

A design with alternating carry polarities and optimized AND-OR-Invert gates

can be about twice as fast.
[3]

4-bit adder with carry lookahead

To reduce the computation time, engineers devised faster ways to add two
binary numbers by using carry-lookahead adders. They work by creating two
signals (P and G) for each bit position, based on whether a carry is propagated
through from a less significant bit position (at least one input is a '1'), generated
in that bit position (both inputs are '1'), or killed in that bit position (both inputs
are '0'). In most cases, P is simply the sum output of a half adder and G is the
carry output of the same adder. After P and G are generated the carries for
every bit position are created. Some advanced carry-lookahead architectures
are the Manchester carry chain, BrentKung adder, and theKoggeStone
adder.

Some other multi-bit adder architectures break the adder into blocks. It is
possible to vary the length of these blocks based on thepropagation delay of the
circuits to optimize computation time. These block based adders include
the carry-skip (or carry-bypass) adderwhich will determine P and G values for
each block rather than each bit, and the carry select adder which pre-generates
the sum and carry values for either possible carry input (0 or 1) to the block,
using multiplexers to select the appropriate result when the carry bit is known.
Other adder designs include the carry-select adder, conditional sum
adder, carry-skip adder, and carry-complete adder.

Lookahead carry unit[edit]

A 64-bit adder

By combining multiple carry lookahead adders even larger adders can be

created. This can be used at multiple levels to make even larger adders. For
example, the following adder is a 64-bit adder that uses four 16-bit CLAs with
two levels of LCUs

Carry-save adders[edit]
Main article: Carry-save adder
If an adding circuit is to compute the sum of three or more numbers it can be
advantageous to not propagate the carry result. Instead, three input adders are
used, generating two results: a sum and a carry. The sum and the carry may be
fed into two inputs of the subsequent 3-number adder without having to wait for
propagation of a carry signal. After all stages of addition, however, a
conventional adder (such as the ripple carry or the lookahead) must be used to
combine the final sum and carry results.

3:2 compressors[edit]
We can view a full adder as a 3:2 lossy compressor: it sums three one-bit
inputs, and returns the result as a single two-bit number; that is, it maps 8 input
values to 4 output values. Thus, for example, a binary input of 101 results in an
output of 1+0+1=10 (decimal number '2'). The carry-out represents bit one of
the result, while the sum represents bit zero. Likewise, a half adder can be used
as a 2:2 lossy compressor, compressing four possible inputs into three possible
outputs.
[citation needed]

Such compressors can be used to speed up the summation of three or more

addends. If the addends are exactly three, the layout is known as the carry-save
adder. If the addends are four or more, more than one layer of compressors is
necessary and there are various possible design for the circuit: the most
common are Dadda and Wallace trees. This kind of circuit is most notably used
in multipliers, which is why these circuits are also known as Dadda and Wallace
multipliers.