A Complete Single-Chip GPS Receiver with 1.

6-V 24-mW Radio

in 0.18-um CMOS

Takahide Kadoyama, Norihito Suzuki, Noboru Sasho, Hiroshi Iizuka, Ikuo Nagase*,
Hideaki Usukubo*, Masayuki Katakura

Sony Corporation Semiconductor Network Company

Sony Semiconductor Kyushu Corporation*

Atsugi-shi, Kanagawa, Japan

Tel +81 46 230 6116 Fax +81 46 230 5633 E-mail t_kadoya@sabip.semicon.sony.co.jp

Abstract
We have developed a complete single-chip GPS receiver using
0.18-um CMOS to meet several important requirements, such as
small size, low power, low cost and high sensitivity for mobile GPS
applications. This is the first case in which a radio has been
successfully combined with a baseband processor, such as SoC., in a
GPS receiver. The GPS chip, with a total size of 6.4x6.4mm, contains
a 2.3x2.0mm radio part, including RF front end, PLLs, IF functions,
and 500K gates of baseband logic, including mask ROM, SRAM and
Dual Port SRAM[1]. It's fabricated using 0.18-um CMOS
Technology with a MIM option and operates from a 1.6 to 2.0-V
power supply. Experimental results show a very low power
consumption of, typically, 57-mW for a fully functional chip
including baseband, and a high sensitivity of -150dBm. Through
countermeasures for substrate coupling noise from the digital part, the
high sensitivity was successfully achieved without any external LNA.
Keywords:GPS, radio, CMOS, SoC, substrate coupling noise
Introduction
Current products of GPS receiver, which have been used in
conventional systems such as car navigation, have so far been
comprised of several individual chips. Typically, these include a
baseband built in CMOS, a Radio Frequency front end built in a
bipolar technology, and an external LNA. However, small size, low
power, low cost and high sensitivity are demanded for mobile
applications such as cellular phones and PDAs. To achieve small size
and low cost, an integration of the baseband and the radio part is
needed. A stand-alone GPS radio built in CMOS has already been
reported[2]. The greatest difficulty in overcoming the hurdle of
integration is separating the radio part from the digital baseband
interference. It is especially important to minimize substrate coupling
noise to a degree comparable to thermal noise or less at the RF front
end portion. Since the baseband is typically designed in a
leading-edge CMOS technology, it is extremely important that the
radio part is also implemented in CMOS. This results in a requirement
to design the radio part with low voltage operation. On top of this, it is
necessary to minimize the radio area size for high cost-efficiency.
Although it is generally difficult in the case of analog parts to reduce
the size even using leading-edge CMOS technology, we were able to
minimize the radio size by applying several techniques as described
later. The power consumption in the radio part is 24m-W with 1.6-V
supply voltage. Such low power consumption is prominent in the
GPS radio field[2]. This paper details mainly the RF front-end portion.
Receiver Architecture
Fig.1 shows a block diagram of the radio part of the GPS receiver. The
radio has an LNA in the front end, which requires low NF, low power
and high gain; a mixer to downconvert the RF signal; RF and IF PLL
synthesizers to generate the local frequencies; and a clocked
comparator to convert the IF signal from analog to digital. Double
conversion architecture is employed to attenuate the image signal. The
1st mixer downconverts the LNA output to the 1st IF I and Q signals
of approximately 2-MHz. After amplifying and filtering the
out-of-band spectrum, the 2nd mixer downconverts the signals again
to the 2nd IF of approximately 1-MHz. An LPF in the 2nd IF
attenuates the image which is converted to 3-MHz. The 2nd IF output
is fed to the clocked comparator, which provides binary data to the
digital baseband section.
Circuit Implementation
A. Low Noise Amplifier (LNA) and Mixer
A single-end common-source type LNA is applied. It was one of the
main challenges in single-chip GPS, since this structure is relatively
sensitive to noise from the digital baseband via the substrate. From
such a noise rejection point of view, a differential topology is preferred.
However, a cascode single-ended topology was selected to balance
the power consumption and the NF of the LNA itself. For this reason,
very careful design for substrate coupling noise was required at this
stage. Inductive degeneration is employed at the source of LNA to
generate a real term in the input impedance. The NF at the front-end

4-89114-035-6/03 2003 Symposium on VLSI Circuits Digest of Technical Papers

 stage is 4dB consuming 4mA. The LNA output is then fed to a single-
balanced mixer, that downconverts 1.575GHz signal to quadrature 1st
IF signals of approximately 2-MHz.
B. IF Filter
To attenuate the image signal, double conversion architecture is
applied. The image signal is still in-band in the 1st IF and the 2nd IF
LPF removes that which is converted to 3-MHz by the 2nd mixer. An
RC filter topology with integrators using an inverting amplifier
scheme is employed. In amplifier design targeting very low supply
voltage-- for example 1.6-V--a narrow common mode range is
certainly a more serious limitation than the output swing. The
inverting scheme, however, provides no common mode swing and, at
the same time, a rail-to-rail output capability. With this wide dynamic
range amplifier, the AGC, which has been used conventionally, has
been eliminated. As a result, low power consumption has been
achieved at this stage.
The filter characteristic is affected by the deviation of resistance and
capacitance on chip. To alleviate the effect, an automatic filter-tuning
circuit is included in order to adjust the center frequency. A successive
approximation procedure using reference frequency and master-slave
topology is employed. This tuning circuit operates with the power on.
As an example, Fig.2 shows the 2nd order LPF with 4-bit resistor
banks for the center frequency tuning. Fig.3 shows the total IF filter
characteristics. The image signal is well suppressed here. To
compensate the 2dB loss of SNR due to the 1-bit quantization at the
final stage, sharp roll-off filters are adopted to reduce equivalent noise
bandwidth effectively. A fully differential topology provides a strong
robustness against the substrate noise.
C. VCO
Reducing power of the Quadrature LO generation is one of the key
issues in minimizing the total power consumption. Conventionally
several approaches, such as a multi-stage poly phase filter, a 1/2
divider of twofold VCO oscillation frequency[3] and a quadrature LO
generator with two VCOs[2] have been used. These schemes require
much power. Fig.4 shows a quadrature LO generator, which consists
of a phase shifter combined directly with the VCO LC tank. This
simple topology reduces the number of active devices and thereby
contributes to reduction of power consumption. Two kinds of
frequency tuning procedures are applied here. One is a coarse tuning
by a capacitor bank using MOS switches and the other is a fine tuning
by MOS accumulation type varactors. The coarse tuning is done by
successive approximation at power on. After that the fine tuning by
conventional PLL procedure starts.
D. Frequency Synthesizer
The TCXO frequency employed in GPS receivers is often a multiple
of 1.023MHz, especially 16.368MHz. Conventional radio and
baseband ICs for GPS receivers usually have restrictions on the
4-89114-035-6/03
TCXO frequency. For example, they cannot use a particular
frequency or, at most, two or three. This is no problem for stand-alone
GPS receivers, but it is preferable for mobile applications to work with
the same oscillator as the mobile device. The use of a common
oscillator reduces cost and undesired radiation. We have introduced a
structure that permits any TCXO frequency, under the assumption that
the PLL synthesizer in the radio part has a programmable structure
that generates local oscillation, not with the usual fixed frequency, but
rather with any frequency in the range, for example, 1.023MHｚ +/-
125KHz.
E.Comparator
Traditionally, an AGC is needed to accept both small and large signals,
with amplification or attenuation depending on conditions at an
antenna and an external LNA. In addition, several gain stages are
needed. These blocks, however, consume a lot of power. One of the
techniques of eliminating power consumption is a wide D-range
clocked comparator. Since by using the wide D-range clocked
comparator, as shown in Fig.5, such an AGC is not necessary, the
clocked comparator technique, which is commonly used in Flash
ADC’s, is applied. This enables sensing to the level of much less than
1mV without any troublesome oscillation. The clocked comparator
digitizes the 2nd IF signal to 1-bit digital data. The losses resulting
from this 1-bit quantization are approximately 2dB of the SNR
compared to multi-bit quantization[4]. However a 1-bit quantization
provides the significant advantage of a small signal capability and a
flexible level adjustment. This scheme eliminated the need for any
AGC and an additional amplifier stage.
F. Isolating Analog from Digital Portion
Substrate coupling noise has long been a major focus of a
mixed-signal IC design. Noise transmission from the digital baseband
logic to the analog portion is the most serious issue in combining a
radio function within a large scale digital IC as a complete SoC. A
target sensitivity of the radio is -150dBm, which would be restricted
by substrate noise rather than the NF of the LNA. We have
considered the following issues as countermeasures for substrate
noise:
1) Spectrum interleaving between RF and the noise components
2) Strategic floor plan
3) Multi stage guard bands for RF portion
4) Deep N-well for RF portion
Although the GPS signal is very weak, fortunately, it is narrow band
and has a fixed frequency. We have checked and confirmed that the
harmonics of the significant TCXO frequency candidates for mobile
applications would not directly conflict with the GPS band. If
anything, the GPS signal is in a region of a valley between harmonics
peaks of the TCXO frequency. In this Radio part, a differential
architecture is applied except for the LNA and the Mixer. It provides
2003 Symposium on VLSI Circuits Digest of Technical Papers
 substrate noise robustness. We have laid out the LNA on the corner of mixer, the PLL synthesizer, the IF filter and the digitizer. The radio
the SoC, which must be the quietest location and tends to be affected part consumes 24-mW with a 1.6-V supply voltage.
by 2 sides rather than 3 sides. As is well known, using a guard band Acknowledgements
helps to reduce noise transmission; however the effectiveness is very The authors would like to acknowledge the cooperation of all
limited, since it restricts only the surface potential of the substrate. We members of this project, including the baseband hardware and
have used two main guard bands--one around the analog blocks of the software engineers. In particular, K.Miura in testing, the layout efforts
LNA, the Mixer and the VCO and the other around the radio part. of J.Ogawa and N.Kaneko are greatly appreciated, as is the CAD
These guards bands are connected to each dedicated bondpad environment, supported by F.Minezaki and H.Kondo. The authors
respectively. Analog blocks other than the LNA, the Mixer and would also like to recognize A.Iwata for his valuable comments, as
VCO behave as guard bands to separate the most sensitive RF part well as M.Nagata.
from the digital part. The remaining guard bands are placed between
each block. These are connected to proper analog grounds of mainly References
the 1st IF and 2nd IF. For this reason, especially, the IF part must be [1]K.Tanaka et al., “A High Performa GPS Solution for Mobile Use”, ION
robust against substrate and supply noise. Noise from the guard band GPS ’02, Sep. 2002.
would flow into the ground line of the IF. The parasitic capacitance [2]Farbod Behbahani et al., “A Fully Integrated Low-IF CMOS GPS Radio
associated with bondpads and electro-static discharge (ESD) circuits With On-Chip Analog Image Rejection”, IEEE J. Solid-State Circuits, vol. 37,
coupled into the substrate can significantly degrade the performance pp. 1721-1727, Dec. 2002.
of the LNA. It is, therefore, important to shield critical bondpads from [3]M.Steyaert et al, “A Fully-Integrated GPS Receiver Front-End with 40mW
the substrate. To that end, an N well is used in the P-substrate as much Power Consumption” , in Proc. ISSCC 2002., Feb.2002.
as possible. We were able to achieve implementation of single-chip [4]S,C.Fisher and K.Ghassemi, “GPS IIF-the next generation” , in Proc. IEEE,
by using a substrate coupling noise simulator, which gave us some vol.87, pp.24-47, Jan.1999.
helpful guidelines for floor planning (to lay out indivisual blocks for
LNA, Mixer, PLL, etc.) and guard band location.
BPF
Clocked
SAW LNA LPF Comp DATA
Experimental Results BPF

Radio performance is summarized in Table 1. This radio operates PSN

from 1.6V to 2V and over a wide range of temperatures from -40 to Successive
fo Adjust

85 degrees. The NF of the Radio part is 4dB when the baseband is PLL VCO PLL VCO

turned off. The NF is degraded a few additional dB when the f T CX O

baseband is activated. However the total sensitivity as a fully F ig .1 R a d io B lo c k D ia g r a m

single-chip operation is -150dBm(fTCXO=19.8MHz), which is still

very high. Fig.6 shows the 2nd IF spectrum of 1MHz. The upper chart
is the spectrum when the baseband is turned off, and the lower is the - + - +

spectrum when the baseband is turned on. Even if some spurious + - + -

signals exist, the total sensitivity remains quite good. Fig.7 shows the
relative sensitivity comparison among alternative options as follows:
A) The single-chip solution of this paper R 4R

2R 8R

B) A) + external LNA 3R R0 1 2R

C) Previous radio chip + baseband chip + external LNA F ig .2 2 n d O rde r L P F w ith 4 b it R eg iste r B an k

The single-chip sensitivity without external LNA is almost equal to

the previous sensitivity with external LNA. The single-chip solution
offers advantages of less power, less cost, small footprint and
capability to avoid an external LNA. Fig.8 shows the whole chip
GPS signal

micrograph. Fig.9 shows the enlarged view of the Radio part.

Image

Conclusion
A Complete Single-Chip GPS Receiver including Radio was Fig.3 Filter Characteristics

implemented in a pure 0.18-um CMOS process consuming 57-mW

from a 1.8-V supply. The total sensitivity as a single-chip is
-150dBm(fTCXO=19.8MHz). The radio part includes the LNA, the

4-89114-035-6/03 2003 Symposium on VLSI Circuits Digest of Technical Papers

 I+
Q+
Q-
I-

Fig.4 Quadrature LO Generator

to
IN+ Latch

VREF

IN-

Fig.5 Wide D-range Comparator

Sensitivity -150dBm @ fTCXO=19.8MHz

Power dissipation 24mW @1.6V 27mW @1.8V
NF 4dB(*)
Image Rejection 30dB
Gain(excluded comp) 100dB
Phase Noise -88dBc/Hz @100KHz offset (*)
Fig.6 2nd IF Spectrum (above: BB off, below: BB on)
Table 1 Radio Performance Summary (*)Baseband off

60
A ) T he single-chip solution of this paper
55 B ) A )+E xt.LN A
C ) P revious R adio+B B +E xt.LN A
50
（＊）Ext.LN A (N F:1.3dB ,G ain:15dB )
45
relative C /N ratio

40

35

30

25
VCO
20
-120 -125 -130 -135 -140 -145 -150

Input Level[dB m ]
F ig.7 S ensitivity as S ingle-chip(fT C X O =18.414M H z) IF Filter

LNA
RAM

Fig.9 Enlarged View of Radio Sections

Radio ROM

Fig.8 Chip Micrograph

4-89114-035-6/03 2003 Symposium on VLSI Circuits Digest of Technical Papers